Search results for "Testability"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
44	Jos van Sas, Chay Nowé, Didier Pollet, Francky Catthoor, Paul Vanoostende, Hugo De Man	Design of a C-testable booth multiplier using a realistic fault model.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	test generation, design for testability, fault modelling, Array multipliers, C-testability
44	Birgitta Lindström, A. Jefferson Offutt, Sten F. Andler	Testability of Dynamic Real-Time Systems: An Empirical Study of Constrained Execution Environment Implications.	ICST	2008	DBLP DOI BibTeX RDF
44	Liangli Ma, Houxiang Wang, Yongjie Li	Construct Metadata Model based on Coupling Information to Increase the Testability of Component-based Software.	AICCSA	2007	DBLP DOI BibTeX RDF
44	Valentina Ciriani, Anna Bernasconi 0001, Rolf Drechsler	Testability of SPP Three-Level Logic Networks in Static Fault Models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
44	Saurabh Chaudhury, Santanu Chattopadhyay, J. Srinivasa Rao	Synthesis of Finite State Machines for Low Power and Testability.	APCCAS	2006	DBLP DOI BibTeX RDF
44	Shyue-Kung Lu, Mau-Jung Lu	Enhancing Delay Fault Testability for FIR Filters Based on Realistic Sequential Cell Fault Model.	DELTA	2004	DBLP DOI BibTeX RDF
44	Magiel Bruntink, Arie van Deursen	Predicting Class Testability using Object-Oriented Metrics.	SCAM	2004	DBLP DOI BibTeX RDF
44	Petros Oikonomakos, Mark Zwolinski, Bashir M. Al-Hashimi	Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric.	DATE	2003	DBLP DOI BibTeX RDF
44	Andrzej Krasniewski	Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices.	FPL	2003	DBLP DOI BibTeX RDF
44	Irith Pomeranz, Sudhakar M. Reddy	Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
44	Srivaths Ravi 0001, Niraj K. Jha	Synthesis of System-on-a-chip for Testability.	VLSI Design	2001	DBLP DOI BibTeX RDF
44	Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie	Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
44	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	A design-for-testability technique for register-transfer level circuits using control/data flow extraction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
44	Laurence Tianruo Yang, Zebo Peng	An Improved Register-Transfer Level Functional Partitioning Approach for Testability.	EUROMICRO	1998	DBLP DOI BibTeX RDF
44	Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha	TAO: regular expression based high-level testability analysis and optimization.	ITC	1998	DBLP DOI BibTeX RDF
44	Shih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chien-Chung Tsai	A novel combinational testability analysis by considering signal correlation.	ITC	1998	DBLP DOI BibTeX RDF
44	R. D. (Shawn) Blanton, John P. Hayes	Testability Properties of Divergent Trees.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	regular circuits, interactive logic arrays, structured circuits, test generation, fault detection, fault modeling
44	Marie-Lise Flottes, R. Pires, Bruno Rouzeyre	Analyzing testability from behavioral to RT level.	ED&TC	1997	DBLP DOI BibTeX RDF
44	Kowen Lai, Christos A. Papachristou	BIST Testability Enhancement of System Level Circuits : Experience with An Industrial Design.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
44	Aiman H. El-Maleh, Janusz Rajski	Delay-fault testability preservation of the concurrent decomposition and factorization transformations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
44	Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy	Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
44	Kurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli	Synthesis for testability techniques for asynchronous circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
44	Chung-Hsing Chen, Daniel G. Saab	A novel behavioral testability measure.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
44	John W. Sheppard, William R. Simpson	Applying Testability Analysis for Integrated Diagnostics.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
43	Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou	Intrinsic response for analog module testing using an analog testability bus.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	analog testability bus, intrinsic response, design for testability, analog testing, boundary scan
43	Marie-Lise Flottes, Christian Landrault, A. Petitqueux	Design for sequential testability: an internal state reseeding approach for 100 % fault coverage.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	sequential testability, internal state reseeding, observation points, minimum DFT insertion, non-scan approach, fault efficiency, 100 percent, fault diagnosis, logic testing, controllability, controllability, design for testability, logic design, sequential circuits, automatic test pattern generation, ATPG, observability, fault coverage, flip-flops, at-speed testing, benchmark circuits, CPU time, partial reset
43	Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting	Metrology for analog module testing using analog testability bus.	ICCAD	1996	DBLP DOI BibTeX RDF	analog module, analog module testing, multiple instantiation, test response analysis, test waveform, testability bus, design for testability
43	Karim Arabi, Bozena Kaminska, Stephen K. Sunter	Design for testability of integrated operational amplifiers using oscillation-test strategy.	ICCD	1996	DBLP DOI BibTeX RDF	integrated operational amplifiers, oscillation-test strategy, vector-less test solution, test mode, oscillation frequency, nominal tolerance, digital circuitry, high fault coverage, simulation, design for testability, design for testability, oscillators, operational amplifiers, Monte Carlo analysis
43	Tapan J. Chakraborty, Vishwani D. Agrawal	Design for high-speed testability of stuck-at faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	design for high-speed testability, stuck-at fault detection, signal transition, timing hazard, multivalue algebra, dh-robust test, sequential feedback, reconvergent fanout, cycle-free sequential circuit, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, partial scan, test generation algorithm, critical path delay
43	S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault	Test configurations to enhance the testability of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	shift operation, scan register, test operation, modified flip-flops, ISCAS89 benchmarks, multiconfiguration, triconfiguration, dynamic generation, logic testing, controllability, design for testability, design for testability, sequential circuits, sequential circuits, observability, observability, DFT, fault coverage, flip-flops, minimisation, scan designs, test application time, test vector
43	Shiyi Xu, Gercy P. Dias	Testability forecasting for sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	testability forecasting, transitive closure algorithm, number of test patterns, computational complexity, fault diagnosis, logic testing, logic testing, statistical analysis, design for testability, sequential circuits, sequential circuits, logic CAD, fault coverage, regression models, automatic test software, CPU time, test generation algorithms
43	Mahsa Vahidi, Alex Orailoglu	Testability metrics for synthesis of self-testable designs and effective test plans.	VTS	1995	DBLP DOI BibTeX RDF	testability metrics, self-testable designs, effective test plans, unified metrics, synthesis phases, VLSI, VLSI, built-in self test, high level synthesis, high level synthesis, design for testability, BIST, DFT, logic CAD, integrated circuit design, benchmark designs
42	Mark Harman, André Baresel, David W. Binkley, Robert M. Hierons, Lin Hu 0005, Bogdan Korel, Phil McMinn, Marc Roper	Testability Transformation - Program Transformation to Improve Testability.	Formal Methods and Testing	2008	DBLP DOI BibTeX RDF
41	Bo Yang 0010, Kaijie Wu 0001, Ramesh Karri	Secure scan: a design-for-test architecture for crypto chips.	DAC	2005	DBLP DOI BibTeX RDF	crypto hardware, scan-based DFT, security, testability
41	Jien-Chung Lo	Analysis of a BICS-Only Concurrent Error Detection Method.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	unsafe probability, reliability, fault coverage, testability, concurrent error detection, built-in current sensors, operating speed
41	Krishnendu Chakrabarty, John P. Hayes	Balance testing and balance-testable design of logic circuits.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	built-in self testing, design for testability, fault detection, fault coverage, testing methods
39	Tomas Pecenka, Lukás Sekanina, Zdenek Kotásek	Evolution of synthetic RTL benchmark circuits with predefined testability.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	evolvable hardware, testability analysis, Benchmark circuit
39	Liang Zhao	A new approach for software testability analysis.	ICSE	2006	DBLP DOI BibTeX RDF	software testability, measure, testing effectiveness, beta distribution
39	Tomokazu Yoneda, Hisakazu Takakuwa, Hideo Fujiwara	Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	system-on-chip, power consumption, test scheduling, test access mechanism, consecutive testability
39	Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara	An Effective Design for Hierarchical Test Generation Based on Strong Testability.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	Hierarchical test generation, strong testability, datapath, test plan
39	Katherine Shu-Min Li, Chung-Len Lee 0001, Yao-Wen Chang, Chauchin Su, Jwu E. Chen	Multilevel full-chip routing with testability and yield enhancement.	SLIP	2005	DBLP DOI BibTeX RDF	multilevel routing, yield, testability
39	Avik Chakraborty	Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays.	VLSI Design	2005	DBLP DOI BibTeX RDF	Fault models, Testability, Design for test, Iterative logic arrays, Universal test sets, Reversible circuits
39	Jiang Chau Wang, Paulo Sérgio Cardoso, Jose Artur Quilici González, Marius Strum, Ricardo Pires	Datapath BIST Insertion Using Pre-Characterized Area and Testability Data.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	test library, RTL architecture, pre-computed testability, self-test
39	Syed Mahfuzul Aziz, S. J. Carr	On C-Testability of Carry Free Dividers.	DELTA	2002	DBLP DOI BibTeX RDF	Carry-free, C-Testability, Divider, Radix-2
39	Sudipto Ghosh	Towards Measurement of Testability of Concurrent Object-Oriented Programs Using Fault Insertion: A Preliminary Investigation.	SCAM	2002	DBLP DOI BibTeX RDF	Java, software testing, Concurrent programs, testability, faults, mutation analysis, test adequacy
39	Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet	Test and Testability of a Monolithic MEMS for Magnetic Field Sensing.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	design for testability, production testing, low-cost testing, MEMS testing
39	Mohammad A. Naal, Emmanuel Simeu	High-Level Synthesis Methodology for On-Line Testability Optimization.	IOLTW	2000	DBLP DOI BibTeX RDF	On-line testability, Function factorization, idle-time operation, High-level synthesis
39	Fabrizio Ferrandi, G. Fornara, Donatella Sciuto, G. Ferrara, Franco Fummi	Testability Alternatives Exploration through Functional Testing.	VTS	2000	DBLP DOI BibTeX RDF	High-level Testability Analysis, Behavioral Test Generation, VHDL, ATPG
39	Irith Pomeranz, Sudhakar M. Reddy	Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines.	DATE	1998	DBLP DOI BibTeX RDF	synchronization, design-for-testability, synchronous sequential circuits
39	Angela Krstic, Kwang-Ting Cheng	Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	resynthesis for testability, timing defects, delay testing, path delay faults, VLSI testing
39	Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre	Improving Testability of Non-Scan Designs during Behavioral Synthesis.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	behavioral level, high level synthesis, design for testability
39	Michael G. McNamer, H. Troy Nagle	ITA: An algorithm for IDDQ testability analysis.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	integrated circuit testing, testability analysis, I DDQ testing, leakage faults
39	C. P. Ravikumar, Hemant Joshi	HISCOAP: a hierarchical testability analysis tool.	VLSI Design	1995	DBLP DOI BibTeX RDF	HISCOAP, hierarchical testability analysis tool, SCOAP measure, gate-level netlist, SCOAP expression diagrams, VLSI, logic testing, controllability, controllability, sequential circuits, sequential circuits, combinational circuits, combinational circuits, observability, observability, circuit analysis computing, integrated logic circuits, VLSI circuits, functional modules, stuck at fault model
39	Abhijit Chatterjee, Jacob A. Abraham	Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	Built-in self-test, test generation, design-for-testability, iterative logic array, pseudo-exhaustive test
39	Roy S. Freedman	Testability of Software Components.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	domain testability, domain-testable program, input-output inconsistencies, small test sets, test outputs, domain-testable specification, nondomain-testable specification, formal specification, controllability, software components, program testing, observability, program specifications
38	Michiko Inoue, Takeshi Higashimura, Kenji Noda, Toshimitsu Masuzawa, Hideo Fujiwara	A High-Level Synthesis Method for Weakly Testable Data Paths.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
37	Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Robust Sequential Fault Testing of Iterative Logic Arrays.	VTS	1997	DBLP DOI BibTeX RDF	Sequential Faults, Linear-testability, Fault Modeling, Automatic Test Generation, C-testability, Iterative Logic Arrays
37	Richard M. Chou, Kewal K. Saluja	Sequential Circuit Testing: From DFT to SFT.	VLSI Design	1997	DBLP DOI BibTeX RDF	design-for-testability methods, SFT techniques, large sequential circuits, logic testing, automatic test pattern generation, ATPG, synthesis-for-testability, sequential circuit testing, DFT techniques
37	Michel Renovell, Florence Azaïs, Yves Bertrand	A design-for-test technique for multistage analog circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	design-for-test technique, multistage analog circuits, DFT approach, op-amp-based modules, testability resources, transparent paths, external I/O, local I/O, test mode, on-chip digital resources, analog response penalty, controllability, controllability, integrated circuit testing, design for testability, observability, observability, mixed-signal circuits, mixed analogue-digital integrated circuits, test management, production testing
37	Arun Balakrishnan, Srimat T. Chakradhar	Software transformations for sequential test generation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	sequential test generation, high fault coverage test sets, testability properties, inverse mapping, software engineering, logic testing, timing, design for testability, sequential circuits, sequential circuits, DFT, software model, software transformations
37	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis	Testing combinational iterative logic arrays for realistic faults.	VTS	1995	DBLP DOI BibTeX RDF	combinational iterative logic arrays, realistic faults, two-dimensional logic arrays, one-dimensional logic arrays, n-pattern tests, linear-testability, efficient test set, ILA, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, cellular arrays, logic arrays, C-testability, cell fault model
36	Xiaojun Ma, Jing Huang 0001, Cecilia Metra, Fabrizio Lombardi	Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Testing, Emerging technologies, Reversible computing, QCA
36	Jani Metsä, Mika Katara, Tommi Mikkonen	Comparing Aspects with Conventional Techniques for Increasing Testability.	ICST	2008	DBLP DOI BibTeX RDF	testing, aspects
36	Thao Nguyen, Navid Rezvani	Printed Circuit Board Assembly Test Process and Design for Testability.	ISQED	2008	DBLP DOI BibTeX RDF
36	Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen	Multilevel Full-Chip Routing With Testability and Yield Enhancement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
36	Richard Ruzicka, Josef Strnadel	Test Controller Synthesis Constrained by Circuit Testability Analysis.	DSD	2007	DBLP DOI BibTeX RDF
36	Anthony Chung, Tao Huang 0019	Two Approaches for the Improvement in Testability of Communication Protocols.	ACIS-ICIS	2005	DBLP DOI BibTeX RDF
36	Piotr Patronik	Delay Testability Properties of Circuits Implementing Threshold and Symmetric Functions.	DSD	2005	DBLP DOI BibTeX RDF
36	Junhao Shi, Görschwin Fey, Rolf Drechsler	Bridging fault testability of BDD circuits.	ASP-DAC	2005	DBLP DOI BibTeX RDF
36	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001	Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
36	Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara	Design for Testability Based on Single-Port-Change Delay Testing for Data Paths.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
36	Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel	Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
36	Mark Harman, Lin Hu 0005, Robert M. Hierons, Joachim Wegener, Harmen Sthamer, André Baresel, Marc Roper	Testability Transformation.	IEEE Trans. Software Eng.	2004	DBLP DOI BibTeX RDF	transformation, Evolutionary testing, search-based software engineering, automated test data generation
36	Görschwin Fey, Junhao Shi, Rolf Drechsler	BDD Circuit Optimization for Path Delay Fault Testability.	DSD	2004	DBLP DOI BibTeX RDF
36	Magdalena Slawiñska	Testability of Distributed Objects.	PPAM	2003	DBLP DOI BibTeX RDF
36	Benoit Baudry, Yves Le Traon, Gerson Sunyé	Testability Analysis of a UML Class Diagram.	IEEE METRICS	2002	DBLP DOI BibTeX RDF
36	Josef Strnadel, Zdenek Kotásek	Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level.	DSD	2002	DBLP DOI BibTeX RDF
36	A. N. Trahtman	A Package TESTAS for Checking Some Kinds of Testability.	CIAA	2002	DBLP DOI BibTeX RDF
36	Shyue-Kung Lu, Chien-Hung Yeh	Enhancing Delay Fault Testability for Iterative Logic Array.	PRDC	2002	DBLP DOI BibTeX RDF
36	Dilip K. Bhavsar	Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
36	Yves Le Traon, Farid Ouabdesselam, Chantal Robach	Analyzing Testability on Data Flow Designs.	ISSRE	2000	DBLP DOI BibTeX RDF
36	Sukalyan Mukherjee	Design for Testability to Achieve High Test Coverage - A Case Study.	DFT	2000	DBLP DOI BibTeX RDF
36	Janusz Sosnowski, Tomasz Wabia, Tomasz Bech	Path Delay Fault Testability Analysis.	DFT	2000	DBLP DOI BibTeX RDF
36	Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken	Manufacturability and Testability Oriented Synthesis.	VLSI Design	2000	DBLP DOI BibTeX RDF	Synthesis Optimization, CAD, System on Chip, Design for Manufacturability, High Level Test Synthesis
36	Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth	A synthesis for testability scheme for finite state machines using clock control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
36	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Hierarchical test generation and design for testability methods for ASPPs and ASIPs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
36	Marie-Lise Flottes, R. Pires, Bruno Rouzeyre	Alleviating DFT Cost Using Testability Driven HLS.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
36	Dilip K. Bhavsar, David R. Akeson, Michael K. Gowan, Daniel B. Jackson	Testability access of the high speed test features in the Alpha 21264 microprocessor.	ITC	1998	DBLP DOI BibTeX RDF
36	Marcello Dalpasso, Michele Favalli	A method for increasing the IDDQ testability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
36	Sujit Dey, Miodrag Potkonjak	Nonscan design-for-testability techniques using RT-level design information.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
36	Yves Le Traon, Chantal Robach	Testability Measurements for Data Flow Designs.	IEEE METRICS	1997	DBLP DOI BibTeX RDF
36	Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker 0001	Testability of 2-level AND/EXOR circuits.	ED&TC	1997	DBLP DOI BibTeX RDF
36	Jin-Cherng Lin, Szu-Wen Lin, Louis Huang	An Approach to Software Testability Measurement.	APSEC	1997	DBLP DOI BibTeX RDF
36	Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda	Guaranteeing Testability in Re-encoding for Low Power.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Initialization sequence, Genetic Algorithm, ATPG
36	Priyank Kalla, Maciej J. Ciesielski	Testability of Sequential Circuits with Multi-Cycle False Path.	VTS	1997	DBLP DOI BibTeX RDF
36	Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja	Incorporating performance and testability constraints during binding in high-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
36	Chung-Hsing Chen, Tanay Karnik, Daniel G. Saab	Structural and behavioral synthesis for testability techniques.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
36	Hassan A. Farhat, Steven G. From	A beta model for estimating the testability and coverage distributions of a VLSI circuit.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
36	João Paulo Teixeira 0001, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves, R. Crespo	A strategy for testability enhancement at layout level.	EURO-DAC	1990	DBLP DOI BibTeX RDF
36	Catherine H. Gebotys, Mohamed I. Elmasry	VLSI Design Synthesis with Testability.	DAC	1988	DBLP BibTeX RDF