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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2833 occurrences of 878 keywords
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Results
Found 2210 publication records. Showing 2210 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
44 | Jos van Sas, Chay Nowé, Didier Pollet, Francky Catthoor, Paul Vanoostende, Hugo De Man |
Design of a C-testable booth multiplier using a realistic fault model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 5(1), pp. 29-41, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
test generation, design for testability, fault modelling, Array multipliers, C-testability |
44 | Birgitta Lindström, A. Jefferson Offutt, Sten F. Andler |
Testability of Dynamic Real-Time Systems: An Empirical Study of Constrained Execution Environment Implications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICST ![In: First International Conference on Software Testing, Verification, and Validation, ICST 2008, Lillehammer, Norway, April 9-11, 2008, pp. 112-120, 2008, IEEE Computer Society, 978-0-7695-3127-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
44 | Liangli Ma, Houxiang Wang, Yongjie Li |
Construct Metadata Model based on Coupling Information to Increase the Testability of Component-based Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICCSA ![In: 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 13-16 May 2007, Amman, Jordan, pp. 24-31, 2007, IEEE Computer Society, 1-4244-1030-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
44 | Valentina Ciriani, Anna Bernasconi 0001, Rolf Drechsler |
Testability of SPP Three-Level Logic Networks in Static Fault Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 2241-2248, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
44 | Saurabh Chaudhury, Santanu Chattopadhyay, J. Srinivasa Rao |
Synthesis of Finite State Machines for Low Power and Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1434-1437, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
44 | Shyue-Kung Lu, Mau-Jung Lu |
Enhancing Delay Fault Testability for FIR Filters Based on Realistic Sequential Cell Fault Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 2nd IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2004), 28-30 January 2004, Perth, Australia, pp. 416-418, 2004, IEEE Computer Society, 0-7695-2081-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
44 | Magiel Bruntink, Arie van Deursen |
Predicting Class Testability using Object-Oriented Metrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCAM ![In: 4th IEEE International Workshop on Source Code Analysis and Manipulation (SCAM 2004), 15-16 September 2004, Chicago, IL, USA, pp. 136-145, 2004, IEEE Computer Society, 0-7695-2144-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
44 | Petros Oikonomakos, Mark Zwolinski, Bashir M. Al-Hashimi |
Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10596-10601, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
44 | Andrzej Krasniewski |
Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 828-838, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
44 | Irith Pomeranz, Sudhakar M. Reddy |
Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(5), pp. 679-689, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
44 | Srivaths Ravi 0001, Niraj K. Jha |
Synthesis of System-on-a-chip for Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 149-156, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
44 | Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie |
Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9), pp. 1327-1340, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
44 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
A design-for-testability technique for register-transfer level circuits using control/data flow extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8), pp. 706-723, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
44 | Laurence Tianruo Yang, Zebo Peng |
An Improved Register-Transfer Level Functional Partitioning Approach for Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 24th EUROMICRO '98 Conference, Engineering Systems and Software for the Next Decade, 25-27 August 1998, Vesteras, Sweden, pp. 10107-, 1998, IEEE Computer Society, 0-8186-8646-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
44 | Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha |
TAO: regular expression based high-level testability analysis and optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 331-340, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
44 | Shih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chien-Chung Tsai |
A novel combinational testability analysis by considering signal correlation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 658-667, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
44 | R. D. (Shawn) Blanton, John P. Hayes |
Testability Properties of Divergent Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(3), pp. 197-209, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
regular circuits, interactive logic arrays, structured circuits, test generation, fault detection, fault modeling |
44 | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre |
Analyzing testability from behavioral to RT level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 158-165, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
44 | Kowen Lai, Christos A. Papachristou |
BIST Testability Enhancement of System Level Circuits : Experience with An Industrial Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 219-, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
44 | Aiman H. El-Maleh, Janusz Rajski |
Delay-fault testability preservation of the concurrent decomposition and factorization transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5), pp. 582-590, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
44 | Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy |
Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5), pp. 531-546, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
44 | Kurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli |
Synthesis for testability techniques for asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12), pp. 1569-1577, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
44 | Chung-Hsing Chen, Daniel G. Saab |
A novel behavioral testability measure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(12), pp. 1960-1970, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
44 | John W. Sheppard, William R. Simpson |
Applying Testability Analysis for Integrated Diagnostics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 9(3), pp. 65-78, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
43 | Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou |
Intrinsic response for analog module testing using an analog testability bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(2), pp. 226-243, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
analog testability bus, intrinsic response, design for testability, analog testing, boundary scan |
43 | Marie-Lise Flottes, Christian Landrault, A. Petitqueux |
Design for sequential testability: an internal state reseeding approach for 100 % fault coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 404-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
sequential testability, internal state reseeding, observation points, minimum DFT insertion, non-scan approach, fault efficiency, 100 percent, fault diagnosis, logic testing, controllability, controllability, design for testability, logic design, sequential circuits, automatic test pattern generation, ATPG, observability, fault coverage, flip-flops, at-speed testing, benchmark circuits, CPU time, partial reset |
43 | Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting |
Metrology for analog module testing using analog testability bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 594-599, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
analog module, analog module testing, multiple instantiation, test response analysis, test waveform, testability bus, design for testability |
43 | Karim Arabi, Bozena Kaminska, Stephen K. Sunter |
Design for testability of integrated operational amplifiers using oscillation-test strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 40-45, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
integrated operational amplifiers, oscillation-test strategy, vector-less test solution, test mode, oscillation frequency, nominal tolerance, digital circuitry, high fault coverage, simulation, design for testability, design for testability, oscillators, operational amplifiers, Monte Carlo analysis |
43 | Tapan J. Chakraborty, Vishwani D. Agrawal |
Design for high-speed testability of stuck-at faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 53-56, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
design for high-speed testability, stuck-at fault detection, signal transition, timing hazard, multivalue algebra, dh-robust test, sequential feedback, reconvergent fanout, cycle-free sequential circuit, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, partial scan, test generation algorithm, critical path delay |
43 | S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault |
Test configurations to enhance the testability of sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 160-168, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
shift operation, scan register, test operation, modified flip-flops, ISCAS89 benchmarks, multiconfiguration, triconfiguration, dynamic generation, logic testing, controllability, design for testability, design for testability, sequential circuits, sequential circuits, observability, observability, DFT, fault coverage, flip-flops, minimisation, scan designs, test application time, test vector |
43 | Shiyi Xu, Gercy P. Dias |
Testability forecasting for sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 199-205, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
testability forecasting, transitive closure algorithm, number of test patterns, computational complexity, fault diagnosis, logic testing, logic testing, statistical analysis, design for testability, sequential circuits, sequential circuits, logic CAD, fault coverage, regression models, automatic test software, CPU time, test generation algorithms |
43 | Mahsa Vahidi, Alex Orailoglu |
Testability metrics for synthesis of self-testable designs and effective test plans. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 170-175, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
testability metrics, self-testable designs, effective test plans, unified metrics, synthesis phases, VLSI, VLSI, built-in self test, high level synthesis, high level synthesis, design for testability, BIST, DFT, logic CAD, integrated circuit design, benchmark designs |
42 | Mark Harman, André Baresel, David W. Binkley, Robert M. Hierons, Lin Hu 0005, Bogdan Korel, Phil McMinn, Marc Roper |
Testability Transformation - Program Transformation to Improve Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods and Testing ![In: Formal Methods and Testing, An Outcome of the FORTEST Network, Revised Selected Papers, pp. 320-344, 2008, Springer, 978-3-540-78916-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Bo Yang 0010, Kaijie Wu 0001, Ramesh Karri |
Secure scan: a design-for-test architecture for crypto chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 135-140, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
crypto hardware, scan-based DFT, security, testability |
41 | Jien-Chung Lo |
Analysis of a BICS-Only Concurrent Error Detection Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(3), pp. 241-253, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
unsafe probability, reliability, fault coverage, testability, concurrent error detection, built-in current sensors, operating speed |
41 | Krishnendu Chakrabarty, John P. Hayes |
Balance testing and balance-testable design of logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(1), pp. 71-86, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
built-in self testing, design for testability, fault detection, fault coverage, testing methods |
39 | Tomas Pecenka, Lukás Sekanina, Zdenek Kotásek |
Evolution of synthetic RTL benchmark circuits with predefined testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(3), pp. 54:1-54:21, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
evolvable hardware, testability analysis, Benchmark circuit |
39 | Liang Zhao |
A new approach for software testability analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSE ![In: 28th International Conference on Software Engineering (ICSE 2006), Shanghai, China, May 20-28, 2006, pp. 985-988, 2006, ACM, 1-59593-375-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
software testability, measure, testing effectiveness, beta distribution |
39 | Tomokazu Yoneda, Hisakazu Takakuwa, Hideo Fujiwara |
Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 150-155, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
system-on-chip, power consumption, test scheduling, test access mechanism, consecutive testability |
39 | Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara |
An Effective Design for Hierarchical Test Generation Based on Strong Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 288-293, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Hierarchical test generation, strong testability, datapath, test plan |
39 | Katherine Shu-Min Li, Chung-Len Lee 0001, Yao-Wen Chang, Chauchin Su, Jwu E. Chen |
Multilevel full-chip routing with testability and yield enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 29-36, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
multilevel routing, yield, testability |
39 | Avik Chakraborty |
Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 249-254, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Fault models, Testability, Design for test, Iterative logic arrays, Universal test sets, Reversible circuits |
39 | Jiang Chau Wang, Paulo Sérgio Cardoso, Jose Artur Quilici González, Marius Strum, Ricardo Pires |
Datapath BIST Insertion Using Pre-Characterized Area and Testability Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(4), pp. 333-344, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
test library, RTL architecture, pre-computed testability, self-test |
39 | Syed Mahfuzul Aziz, S. J. Carr |
On C-Testability of Carry Free Dividers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 417-424, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Carry-free, C-Testability, Divider, Radix-2 |
39 | Sudipto Ghosh |
Towards Measurement of Testability of Concurrent Object-Oriented Programs Using Fault Insertion: A Preliminary Investigation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCAM ![In: 2nd IEEE International Workshop on Source Code Analysis and Manipulation (SCAM 2002), 1 October 2002, Montreal, Canada, pp. 17-25, 2002, IEEE Computer Society, 0-7695-1793-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Java, software testing, Concurrent programs, testability, faults, mutation analysis, test adequacy |
39 | Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet |
Test and Testability of a Monolithic MEMS for Magnetic Field Sensing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(5), pp. 439-450, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
design for testability, production testing, low-cost testing, MEMS testing |
39 | Mohammad A. Naal, Emmanuel Simeu |
High-Level Synthesis Methodology for On-Line Testability Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 201-206, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
On-line testability, Function factorization, idle-time operation, High-level synthesis |
39 | Fabrizio Ferrandi, G. Fornara, Donatella Sciuto, G. Ferrara, Franco Fummi |
Testability Alternatives Exploration through Functional Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 423-430, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
High-level Testability Analysis, Behavioral Test Generation, VHDL, ATPG |
39 | Irith Pomeranz, Sudhakar M. Reddy |
Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 983-984, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
synchronization, design-for-testability, synchronous sequential circuits |
39 | Angela Krstic, Kwang-Ting Cheng |
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(1), pp. 43-54, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
resynthesis for testability, timing defects, delay testing, path delay faults, VLSI testing |
39 | Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre |
Improving Testability of Non-Scan Designs during Behavioral Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(1), pp. 29-42, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
behavioral level, high level synthesis, design for testability |
39 | Michael G. McNamer, H. Troy Nagle |
ITA: An algorithm for IDDQ testability analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(3), pp. 287-298, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
integrated circuit testing, testability analysis, I DDQ testing, leakage faults |
39 | C. P. Ravikumar, Hemant Joshi |
HISCOAP: a hierarchical testability analysis tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 272-277, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
HISCOAP, hierarchical testability analysis tool, SCOAP measure, gate-level netlist, SCOAP expression diagrams, VLSI, logic testing, controllability, controllability, sequential circuits, sequential circuits, combinational circuits, combinational circuits, observability, observability, circuit analysis computing, integrated logic circuits, VLSI circuits, functional modules, stuck at fault model |
39 | Abhijit Chatterjee, Jacob A. Abraham |
Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(4), pp. 351-372, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
Built-in self-test, test generation, design-for-testability, iterative logic array, pseudo-exhaustive test |
39 | Roy S. Freedman |
Testability of Software Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 17(6), pp. 553-564, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
domain testability, domain-testable program, input-output inconsistencies, small test sets, test outputs, domain-testable specification, nondomain-testable specification, formal specification, controllability, software components, program testing, observability, program specifications |
38 | Michiko Inoue, Takeshi Higashimura, Kenji Noda, Toshimitsu Masuzawa, Hideo Fujiwara |
A High-Level Synthesis Method for Weakly Testable Data Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 40-45, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
37 | Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis |
Robust Sequential Fault Testing of Iterative Logic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 238-244, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Sequential Faults, Linear-testability, Fault Modeling, Automatic Test Generation, C-testability, Iterative Logic Arrays |
37 | Richard M. Chou, Kewal K. Saluja |
Sequential Circuit Testing: From DFT to SFT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 274-278, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
design-for-testability methods, SFT techniques, large sequential circuits, logic testing, automatic test pattern generation, ATPG, synthesis-for-testability, sequential circuit testing, DFT techniques |
37 | Michel Renovell, Florence Azaïs, Yves Bertrand |
A design-for-test technique for multistage analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 113-119, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
design-for-test technique, multistage analog circuits, DFT approach, op-amp-based modules, testability resources, transparent paths, external I/O, local I/O, test mode, on-chip digital resources, analog response penalty, controllability, controllability, integrated circuit testing, design for testability, observability, observability, mixed-signal circuits, mixed analogue-digital integrated circuits, test management, production testing |
37 | Arun Balakrishnan, Srimat T. Chakradhar |
Software transformations for sequential test generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 266-, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
sequential test generation, high fault coverage test sets, testability properties, inverse mapping, software engineering, logic testing, timing, design for testability, sequential circuits, sequential circuits, DFT, software model, software transformations |
37 | Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis |
Testing combinational iterative logic arrays for realistic faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 35-41, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
combinational iterative logic arrays, realistic faults, two-dimensional logic arrays, one-dimensional logic arrays, n-pattern tests, linear-testability, efficient test set, ILA, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, cellular arrays, logic arrays, C-testability, cell fault model |
36 | Xiaojun Ma, Jing Huang 0001, Cecilia Metra, Fabrizio Lombardi |
Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 297-311, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Testing, Emerging technologies, Reversible computing, QCA |
36 | Jani Metsä, Mika Katara, Tommi Mikkonen |
Comparing Aspects with Conventional Techniques for Increasing Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICST ![In: First International Conference on Software Testing, Verification, and Validation, ICST 2008, Lillehammer, Norway, April 9-11, 2008, pp. 387-395, 2008, IEEE Computer Society, 978-0-7695-3127-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
testing, aspects |
36 | Thao Nguyen, Navid Rezvani |
Printed Circuit Board Assembly Test Process and Design for Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 594-599, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
36 | Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen |
Multilevel Full-Chip Routing With Testability and Yield Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9), pp. 1625-1636, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Richard Ruzicka, Josef Strnadel |
Test Controller Synthesis Constrained by Circuit Testability Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 626-633, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Anthony Chung, Tao Huang 0019 |
Two Approaches for the Improvement in Testability of Communication Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACIS-ICIS ![In: 4th Annual ACIS International Conference on Computer and Information Science (ICIS 2005), 14-16 July 2005, Jeju Island, South Korea, pp. 562-565, 2005, IEEE Computer Society, 0-7695-2296-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Piotr Patronik |
Delay Testability Properties of Circuits Implementing Threshold and Symmetric Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 289-297, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Junhao Shi, Görschwin Fey, Rolf Drechsler |
Bridging fault testability of BDD circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 188-191, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001 |
Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 404-409, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara |
Design for Testability Based on Single-Port-Change Delay Testing for Data Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 254-259, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel |
Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 2005 NASA / DoD Conference on Evolvable Hardware (EH 2005), 29 June - 1 July 2005, Washington, DC, USA, pp. 51-58, 2005, IEEE Computer Society, 0-7695-2399-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Mark Harman, Lin Hu 0005, Robert M. Hierons, Joachim Wegener, Harmen Sthamer, André Baresel, Marc Roper |
Testability Transformation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 30(1), pp. 3-16, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
transformation, Evolutionary testing, search-based software engineering, automated test data generation |
36 | Görschwin Fey, Junhao Shi, Rolf Drechsler |
BDD Circuit Optimization for Path Delay Fault Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France, pp. 168-172, 2004, IEEE Computer Society, 0-7695-2203-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Magdalena Slawiñska |
Testability of Distributed Objects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPAM ![In: Parallel Processing and Applied Mathematics, 5th International Conference, PPAM 2003, Czestochowa, Poland, September 7-10, 2003. Revised Papers, pp. 413-418, 2003, Springer, 3-540-21946-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Benoit Baudry, Yves Le Traon, Gerson Sunyé |
Testability Analysis of a UML Class Diagram. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE METRICS ![In: 8th IEEE International Software Metrics Symposium (METRICS 2002), 4-7 June 2002, Ottawa, Canada, pp. 54-, 2002, IEEE Computer Society, 0-7695-1339-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
36 | Josef Strnadel, Zdenek Kotásek |
Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 166-173, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
36 | A. N. Trahtman |
A Package TESTAS for Checking Some Kinds of Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIAA ![In: Implementation and Application of Automata, 7th International Conference, CIAA 2002, Tours, France, July 3-5, 2002, Revised Papers, pp. 228-232, 2002, Springer, 3-540-40391-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
36 | Shyue-Kung Lu, Chien-Hung Yeh |
Enhancing Delay Fault Testability for Iterative Logic Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 16-18 December 2002, Tsukuba-City, Ibarski, Japan, pp. 283-292, 2002, IEEE Computer Society, 0-7695-1852-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
36 | Dilip K. Bhavsar |
Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 17(2), pp. 94-99, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
36 | Yves Le Traon, Farid Ouabdesselam, Chantal Robach |
Analyzing Testability on Data Flow Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSRE ![In: 11th International Symposium on Software Reliability Engineering (ISSRE 2000), 8-11 October 2000, San Jose, CA, USA, pp. 162-173, 2000, IEEE Computer Society, 0-7695-0807-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
36 | Sukalyan Mukherjee |
Design for Testability to Achieve High Test Coverage - A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings, pp. 320-328, 2000, IEEE Computer Society, 0-7695-0719-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
36 | Janusz Sosnowski, Tomasz Wabia, Tomasz Bech |
Path Delay Fault Testability Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings, pp. 338-, 2000, IEEE Computer Society, 0-7695-0719-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
36 | Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken |
Manufacturability and Testability Oriented Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 185-191, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Synthesis Optimization, CAD, System on Chip, Design for Manufacturability, High Level Test Synthesis |
36 | Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth |
A synthesis for testability scheme for finite state machines using clock control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(12), pp. 1780-1792, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
36 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
Hierarchical test generation and design for testability methods for ASPPs and ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(3), pp. 357-370, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
36 | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre |
Alleviating DFT Cost Using Testability Driven HLS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 46-51, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
36 | Dilip K. Bhavsar, David R. Akeson, Michael K. Gowan, Daniel B. Jackson |
Testability access of the high speed test features in the Alpha 21264 microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 487-495, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
36 | Marcello Dalpasso, Michele Favalli |
A method for increasing the IDDQ testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10), pp. 1186-1188, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
36 | Sujit Dey, Miodrag Potkonjak |
Nonscan design-for-testability techniques using RT-level design information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(12), pp. 1488-1506, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
36 | Yves Le Traon, Chantal Robach |
Testability Measurements for Data Flow Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE METRICS ![In: 4th IEEE International Software Metrics Symposium (METRICS 1997), November 5-7, 1997, Albuquerque, NM, USA, pp. 91-98, 1997, IEEE Computer Society, 0-8186-8093-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
36 | Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker 0001 |
Testability of 2-level AND/EXOR circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 548-553, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
36 | Jin-Cherng Lin, Szu-Wen Lin, Louis Huang |
An Approach to Software Testability Measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APSEC ![In: 4th Asia-Pacific Software Engineering and International Computer Science Conference (APSEC '97 / ICSC '97), 2-5 December 1997, Clear Water Bay, Hong Kong, pp. 515-516, 1997, IEEE Computer Society, 0-8186-8271-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
36 | Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda |
Guaranteeing Testability in Re-encoding for Low Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 30-35, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Initialization sequence, Genetic Algorithm, ATPG |
36 | Priyank Kalla, Maciej J. Ciesielski |
Testability of Sequential Circuits with Multi-Cycle False Path. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 322-328, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
36 | Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja |
Incorporating performance and testability constraints during binding in high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10), pp. 1212-1225, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
36 | Chung-Hsing Chen, Tanay Karnik, Daniel G. Saab |
Structural and behavioral synthesis for testability techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(6), pp. 777-785, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
36 | Hassan A. Farhat, Steven G. From |
A beta model for estimating the testability and coverage distributions of a VLSI circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(4), pp. 550-554, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
36 | João Paulo Teixeira 0001, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves, R. Crespo |
A strategy for testability enhancement at layout level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 413-417, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
36 | Catherine H. Gebotys, Mohamed I. Elmasry |
VLSI Design Synthesis with Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 16-21, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
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