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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2239 occurrences of 940 keywords
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Results
Found 7472 publication records. Showing 7472 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
52 | Feng Gao 0017, John P. Hayes |
Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
52 | Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy 0001 |
Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
52 | Kaviraj Chopra, Sarma B. K. Vrudhula |
Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
52 | Preetham Lakshmikanthan, Adrian Nunez |
A Novel Methodology to Reduce Leakage Power in CMOS Complementary Circuits. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
52 | Akhilesh Kumar, Mohab Anis |
An analytical state dependent leakage power model for FPGAs. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
52 | Sarvesh Bhardwaj, Yu Cao 0001, Sarma B. K. Vrudhula |
LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
52 | Yu Wang 0002, Hai Lin, Huazhong Yang, Rong Luo, Hui Wang 0004 |
Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
52 | Hong Luo, Huazhong Yang, Rong Luo |
Accurate and Fast Estimation of Junction Band-to-Band Leakage in Nanometer-Scale MOSFET. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
52 | Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar |
Gate oxide leakage and delay tradeoffs for dual-Tox circuits. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy 0001 |
Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy 0001 |
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Peng Li 0001, Yangdong Deng, Lawrence T. Pileggi |
Temperature-Dependent Optimization of Cache Leakage Power Dissipation. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Mohab Anis, Mohamed H. Abu-Rahma |
Leakage Current Variability in Nanometer Technologies, invited. |
IWSOC |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Hongliang Chang, Sachin S. Sapatnekar |
Full-chip analysis of leakage power under process variations, including spatial correlations. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Navid Azizi, Farid N. Najm |
An Asymmetric SRAM Cell to Lower Gate Leakage. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
52 | Chintan Patel, Abhishek Singh 0001, Jim Plusquellic |
Defect detection under Realistic Leakage Models using Multiple IDDQ Measurement. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
52 | James T. Kao, Siva G. Narendra, Anantha P. Chandrakasan |
Subthreshold leakage modeling and reduction techniques. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
52 | Stefanos Kaxiras, Zhigang Hu, Margaret Martonosi |
Cache decay: exploiting generational behavior to reduce cache leakage power. |
ISCA |
2001 |
DBLP DOI BibTeX RDF |
|
52 | Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy 0001 |
Models and algorithms for bounds on leakage in CMOS circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
52 | M. Zhang, Stafford E. Tavares, L. Lorne Campbell |
Information Leakage of Boolean Functions and Its Relationship to Other Cryptographic Criteria. |
CCS |
1994 |
DBLP DOI BibTeX RDF |
|
51 | Hyunhee Kim, Jung Ho Ahn, Jihong Kim 0001 |
Replication-aware leakage management in chip multiprocessors with private L2 cache. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
leakage power management, chip multiprocessors, L2 caches |
51 | Ting Zhu 0001, Ziguo Zhong, Yu Gu 0001, Tian He 0001, Zhi-Li Zhang |
Leakage-aware energy synchronization for wireless sensor networks. |
MobiSys |
2009 |
DBLP DOI BibTeX RDF |
ultra-capacitor, wireless sensor networks, energy, leakage |
51 | Vikas Kaushal, Quentin Diduck, Martin Margala |
Study of leakage current mechanisms in ballistic deflection transistors. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
ballistic transport, current leakage mechanism, deflection transistors, silvaco simulation, geometry, monte carlo simulation |
51 | Vineeth Veetil, Dennis Sylvester, David T. Blaauw, Saumil Shah, Steffen Rochel |
Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
statistical leakage, Monte Carlo, variance reduction |
51 | Lei Cheng 0001, Deming Chen, Martin D. F. Wong |
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
Input vector control, gate replacement, leakage reduction |
51 | Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum |
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors. |
CASES |
2008 |
DBLP DOI BibTeX RDF |
multiple sleep mode, peripheral circuits, cache, embedded processor, leakage power |
51 | Maziar Goudarzi, Tohru Ishihara |
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
asymmetric sram, leakage, instruction cache, register renaming |
51 | Tao Li, Wenjun Zhang 0001, Zhiping Yu |
Full-chip leakage analysis in nano-scale technologies: mechanisms, variation sources, and verification. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
leakage modeling, variation source, statistical analysis |
51 | Andrew B. Kahng, Swamy Muddu, Puneet Sharma |
Detailed placement for leakage reduction using systematic through-pitch variation. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
aCLV, through-pitch, leakage, lithography, detailed placement |
51 | Juan M. Cebrian, Juan L. Aragón, José M. García 0001, Stefanos Kaxiras |
Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors. |
Conf. Computing Frontiers |
2007 |
DBLP DOI BibTeX RDF |
leakage, value prediction, energy efficient architectures, cache decay |
51 | Yi-Ping You, Chingren Lee, Jenq Kuen Lee |
Compilers for leakage power reduction. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
Compilers for low power, power-gating mechanisms, leakage-power reduction |
51 | Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. Massoud |
An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
gate oxide tunneling, low power circuit design, subthreshold leakage, dual threshold voltage |
51 | Saumil Shah, Puneet Gupta 0001, Andrew B. Kahng |
Standard cell library optimization for leakage reduction. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
gate-length biasing, library optimization, leakage reduction |
51 | Lei Cheng 0001, Liang Deng, Deming Chen, Martin D. F. Wong |
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
gate replacement, input vector control, leakage reduction |
51 | Yan Meng, Timothy Sherwood, Ryan Kastner |
Exploring the limits of leakage power reduction in caches. |
ACM Trans. Archit. Code Optim. |
2005 |
DBLP DOI BibTeX RDF |
cache intervals, leakage power, Limits |
51 | Lin Yuan, Gang Qu 0001 |
Enhanced leakage reduction Technique by gate replacement. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
MLV, gate replacement, leakage reduction |
51 | Arifur Rahman, Vijay Polavarapuv |
Evaluation of low-leakage design techniques for field programmable gate arrays. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
FPGA, leakage power, multiplexer |
51 | Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir |
Analytical models for leakage power estimation of memory array structures. |
CODES+ISSS |
2004 |
DBLP DOI BibTeX RDF |
estimation, SRAMs, leakage power |
51 | Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin |
Adapting instruction level parallelism for optimizing leakage in VLIW architectures. |
LCTES |
2003 |
DBLP DOI BibTeX RDF |
power supply gating, instruction level parallelism, instruction scheduling, VLIW architecture, leakage energy, functional units |
51 | Guangyu Chen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mario Wolczko |
Tracking object life cycle for leakage energy optimization. |
CODES+ISSS |
2003 |
DBLP DOI BibTeX RDF |
Java, cache, leakage energy |
51 | Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy 0001 |
A forward body-biased low-leakage SRAM cache: device and architecture considerations. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
forward body-biasing, super high VT, SRAM, leakage power |
51 | Haihua Su, Frank Liu 0001, Anirudh Devgan, Emrah Acar, Sani R. Nassif |
Full chip leakage estimation considering power supply and temperature variations. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
supply voltage variation, leakage power, thermal analysis |
51 | Fatih Hamzaoglu, Mircea R. Stan |
Circuit-level techniques to control gate leakage for sub-100nm CMOS. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
low power, MTCMOS, gate leakage, domino circuits |
51 | David Scott, Shaoping Tang, Song Zhao, Mahalingam Nandakumar |
Device Physics Impact on Low Leakage, High Speed DSP Design Techniques (invited). |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
standby, GIDL, leakage, tunneling, subthreshold, current |
51 | Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park |
Leakage Minimization Technique for Nanoscale CMOS VLSI. |
IEEE Des. Test Comput. |
2007 |
DBLP DOI BibTeX RDF |
nanometer CMOS, cell characterization, gate-tunneling current, input pattern generation, leakage power, subthreshold leakage current |
51 | Yu-Shiang Lin, Dennis Sylvester |
Runtime leakage power estimation technique for combinational circuits. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
subthreshold leakage analysis, runtime leakage power estimation technique, dynamic estimation methods, static estimation methods, combinational circuits, error estimation, SPICE simulations |
51 | Frank Sill, Jiaxi You, Dirk Timmermann |
Design of mixed gates for leakage reduction. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
mixed gates, leakage current, threshold voltage, gate leakage |
51 | Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy 0001 |
Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
double-gate devices, quantum effect, stacking effect, estimation, SRAM, gate leakage, subthreshold leakage |
49 | Dongwoo Lee, Wesley Kwong, David T. Blaauw, Dennis Sylvester |
Analysis and minimization techniques for total leakage considering gate oxide leakage. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
|
48 | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Optimal sleep transistor synthesis under timing and area constraints. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
row-based, clustering, leakage power, power-gating, standard cell, sleep transistor |
48 | Mark Hempstead, Gu-Yeon Wei, David M. Brooks |
Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations. |
CASES |
2006 |
DBLP DOI BibTeX RDF |
wireless sensor networks, low power, system architecture, technology scaling, leakage power reduction |
46 | Xiaochen Guo, Engin Ipek, Tolga Soyata |
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing. |
ISCA |
2010 |
DBLP DOI BibTeX RDF |
STT-MRAM, power-efficiency |
46 | Yu Wang 0002, Xiaoming Chen 0003, Wenping Wang, Varsha Balakrishnan, Yu Cao 0001, Yuan Xie 0001, Huazhong Yang |
On the efficacy of input Vector Control to mitigate NBTI effects and leakage power. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
46 | Joël Alwen, Yevgeniy Dodis, Daniel Wichs |
Leakage-Resilient Public-Key Cryptography in the Bounded-Retrieval Model. |
CRYPTO |
2009 |
DBLP DOI BibTeX RDF |
|
46 | Shilpa Bhoj, Dinesh Bhatia |
Early stage FPGA interconnect leakage power estimation. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
46 | Harmander Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka |
Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Meng Wang 0005, Zili Shao, Chun Xue, Edwin Hsing-Mean Sha |
Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors. |
RTCSA |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Afshin Nourivand, Chunyan Wang 0004, M. Omair Ahmad |
An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu |
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Lava P. Kumar, Baquer Mazhari |
Optimum Supply Voltages for Minimization of Leakage Currents in SRAM in Stand-by Mode. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
46 | Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry |
Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units. |
MICRO |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Jinwen Xi, Peixin Zhong |
A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy Models. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
network-on-chip, SystemC, energy model |
46 | Houman Homayoun, Ted H. Szymanski |
Reducing the Instruction Queue Leakage Power in Superscalar Processors. |
CCECE |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Sanjeev K. Jain, Pankaj Agarwal |
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Yu Wang 0002, Hui Wang 0004, Huazhong Yang |
Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Balaji Vaidyanathan, Suresh Srinivasan, Yuan Xie 0001, Narayanan Vijaykrishnan, Rong Luo |
Leakage Optimized DECAP Design for FPGAs. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy 0001 |
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
46 | Dongwoo Lee, David T. Blaauw, Dennis Sylvester |
Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
46 | J. Derakhshandeh, Nasser Masoumi, B. Kasiri, Y. Farazmand, Akbarzadeh, S. Aghnoot |
A Precise Model for Leakage Power Estimation in VLSI Circuits. |
IWSOC |
2005 |
DBLP DOI BibTeX RDF |
|
46 | Jun-Cheol Park, Vincent John Mooney III, Philipp Pfeiffenberger |
Sleepy Stack Reduction of Leakage Power. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
46 | John C. Lach, Jason Brandon, Kevin Skadron |
A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs. |
ICCD |
2004 |
DBLP DOI BibTeX RDF |
|
46 | Mohan G. Kabadi, Ranjani Parthasarathi |
Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache Subsystem. |
Asia-Pacific Computer Systems Architecture Conference |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Nam Sung Kim, Krisztián Flautner, David T. Blaauw, Trevor N. Mudge |
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. |
MICRO |
2002 |
DBLP DOI BibTeX RDF |
|
46 | Steve Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman |
Managing static leakage energy in microprocessor functional units. |
MICRO |
2002 |
DBLP DOI BibTeX RDF |
|
46 | Afshin Abdollahi, Massoud Pedram, Farzan Fallah |
Runtime mechanisms for leakage current reduction in CMOS VLSI circuits1, 2. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
|
46 | Chandramouli Gopalakrishnan, Srinivas Katkoori |
Behavioral synthesis of datapaths with low leakage power. |
ISCAS (4) |
2002 |
DBLP DOI BibTeX RDF |
|
46 | Wen-Tsong Shiue |
Leakage power estimation and minimization in VLSI circuits. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
45 | Xuan-Lun Huang, Chen-Yuan Yang, Jiun-Lang Huang |
Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
?? modulation, analog/mixed-signal testing, integrator leakage, diagnosis, design-for-test (DfT) |
45 | Michael J. Anderson, Azadeh Davoodi, Jungseob Lee, Abhishek A. Sinkar, Nam Sung Kim |
Statistical static timing analysis considering leakage variability in power gated designs. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
process variations, leakage, power gating, ssta |
45 | Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao |
Dose map and placement co-optimization for timing yield enhancement and leakage power reduction. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
dose map, placement, timing yield, leakage power reduction |
45 | Olga Golubeva, Mirko Loghi, Enrico Macii, Massimo Poncino |
Locality-driven architectural cache sub-banking for leakage energy reduction. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
banked cache, memory hierarchy, leakage reduction, architectural optimization |
45 | Jacopo Giorgetti, Giuseppe Scotti, Andrea Simonetti, Alessandro Trifiletti |
Analysis of data dependence of leakage current in CMOS cryptographic hardware. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
leakage power consumption, side channel analysis, cryptographic hardware |
45 | Domenik Helms, Günter Ehmen, Wolfgang Nebel |
Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
modeling, process variation, leakage, state dependence |
45 | Xin Li 0001, Jiayong Le, Lawrence T. Pileggi |
Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
statistical analysis, leakage power |
45 | Frank Sill, Frank Grassert, Dirk Timmermann |
Total leakage power optimization with improved mixed gates. |
SBCCI |
2005 |
DBLP DOI BibTeX RDF |
MVT, leakage currents, threshold voltage |
45 | Jia-Jhe Li, Yuan-Shin Hwang |
Snug set-associative caches: reducing leakage power while improving performance. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
leakage power, set-associative caches |
45 | Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan |
Reducing leakage energy in FPGAs using region-constrained placement. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
region-constrained placement, FPGA, leakage power |
45 | Amir Amirabadi, Javid Jaffari, Ali Afzali-Kusha, Mehrdad Nourani, Ali Khaki-Firooz |
Leakage current reduction by new technique in standby mode. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
subthreshold current, low power, leakage current, digital integrated circuits, static power |
45 | Puneet Gupta 0001, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester |
Selective gate-length biasing for cost-effective runtime leakage control. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
power, layout, manufacturability, leakage, OPC, lithography |
45 | Yongjun Xu, Zuying Luo, Zhiguo Chen, Xiaowei Li 0001 |
Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
stack effect, leakage current simulation, propagation of signal probability, macromodeling |
45 | Jie S. Hu, A. Nadgir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir |
Exploiting program hotspots and code sequentiality for instruction cache leakage management. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
leakage power, cache design |
45 | Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy 0001, Shekhar Borkar |
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
DSM leakage control and scaling trends, RBB, high performance RF design, non-minimum L |
45 | Ankur Srivastava 0001 |
Simultaneous Vt selection and assignment for leakage optimization. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
thresh-hold voltage, linear programming, leakage power |
45 | Imad A. Ferzli, Farid N. Najm |
Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
statistical analysis, leakage current, power grid, voltage drop |
45 | Navid Azizi, Andreas Moshovos, Farid N. Najm |
Low-leakage asymmetric-cell SRAM. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
low-leakage, low-power, SRAM, dual-Vt |
45 | Rahul Kumar, C. P. Ravikumar |
Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
Power Estimation, Leakage Power, Linear Regression, Deep Submicron |
45 | Saibal Mukhopadhyay, Kaushik Roy 0001 |
Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
band-to-band tunneling, variability, Monte Carlo, threshold voltage, gate leakage, subthreshold leakage |
45 | Alodeep Sanyal, Ashesh Rastogi, Wei Chen, Sandip Kundu |
An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading Effects. |
IEEE Trans. Computers |
2010 |
DBLP DOI BibTeX RDF |
band-to-band-tunneling leakage, loading effect, Newton-Raphson method, gate leakage, Subthreshold leakage |
43 | Janakiraman Viraraghavan, Bishnu Prasad Das, Bharadwaj Amrutur |
Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Tao Li, Zhiping Yu |
Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
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