Search results for "scan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
44	Chunsheng Liu, Krishnendu Chakrabarty	A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis.	DATE	2003	DBLP DOI BibTeX RDF
44	Irith Pomeranz	On the use of random limited-scan to improve at-speed randompattern testing of scan circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
43	Thomas W. Williams, Kenneth P. Parker	Design for Testability - A Survey.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	Built-In Logic Block Observation (BILBO), Level Sensitive Scan Design (LSSD), Random Access Scan, Scan/Set Logic, testing, test generation, self test, Signature Analysis, Scan Path
42	Jacob Savir	Module level weighted random patterns.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	module level self-test architecture, pseudorandom pattern generator, universal weighting generator, scan latch, near-optimal weight, signal pins, weight control function, self-test time, logic testing, probability, integrated circuit testing, automatic testing, multivalued logic circuits, boundary scan testing, scan test, weighted random patterns, multiple input signature register
41	Massimo Bilancia, Silvestro Montrone, Paola Perchinunno	A Model-Based Scan Statistics for Detecting Geographical Clustering of Disease.	ICCSA (1)	2009	DBLP DOI BibTeX RDF	Disease clustering, Model-based scan statistics, BYM model, Lung cancer mortality, Spatial scan statistics
41	Yuri Dotsenko, Naga K. Govindaraju, Peter-Pike J. Sloan, Charles Boyd, John Manferdelli	Fast scan algorithms on graphics processors.	ICS	2008	DBLP DOI BibTeX RDF	all-prefix-sum, segmented scan, parallel algorithm, GPU, GPGPU, scan, HPC, many-core
41	King Leong Lee, Nadir Z. Basturkmen, Srikanth Venkataraman	Diagnosis of Scan Clock Failures.	VTS	2008	DBLP DOI BibTeX RDF	scan clock, diagnosis, scan chain
41	Young-Ho Choi, Se-Young Oh	Map building through pseudo dense scan matching using visual sonar data.	Auton. Robots	2007	DBLP DOI BibTeX RDF	Robust visual sonar, Pseudo dense scan, Adaptive scan matching, Trajectory correction
41	Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda	Systematic Scan Reconfiguration.	ASP-DAC	2007	DBLP DOI BibTeX RDF	systematic scan reconfiguration, test data compression technique, single-stuck fault test sets, transition fault test sets, scan chains
41	Arun Balakrishnan, Srimat T. Chakradhar	Retiming with logic duplication transformation: theory and an application to partial scan.	VLSI Design	1996	DBLP DOI BibTeX RDF	logic duplication transformation, partial scan application, RLD configurations, RLD transformation, testability metrics, scan flip-flops, sequential circuit design, linear programming, timing, integer programming, logic design, sequential circuits, logic CAD, polynomial time algorithm, integer linear program, flip-flops, retiming, integrated circuit design, circuit CAD, integrated logic circuits, objective function
40	Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi	A Selective Trigger Scan Architecture for VLSI Testing.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Delay Testing, Test Compression, Test Application Time, Scan Test, Test Data Volume, Test Power
40	Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang	A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	profiling, design for testability, Diagnosis, fault, scan chain
40	Anshuman Chandra, Rohit Kapur	Bounded Adjacent Fill for Low Capture Power Scan Testing.	VTS	2008	DBLP DOI BibTeX RDF	capture power, random fill, shift power, test, low power, scan
40	Arno Wagner, Thomas Dübendorfer, Roman Hiestand, Christoph Göldi, Bernhard Plattner	A Fast Worm Scan Detection Tool for VPN Congestion Avoidance.	DIMVA	2006	DBLP DOI BibTeX RDF	Bro, detection, worm, Scan, gateway, VPN
40	Christian Wimmer, Hanspeter Mössenböck	Optimized interval splitting in a linear scan register allocator.	VEE	2005	DBLP DOI BibTeX RDF	linear scan, java, optimization, compilers, graph-coloring, register allocation, just-in-time compilation
40	Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian	Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	relay propagation test, multiprocessor systems, Boundary scan
40	Sambhunath Biswas	Hilbert Scan and Image Compression.	ICPR	2000	DBLP DOI BibTeX RDF	Hilbert scan, Hilbert image, Bezier-Bernstein polynomial, Huffman coding
40	Ranganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba	Static Compaction Techniques to Control Scan Vector Power Dissipation.	VTS	2000	DBLP DOI BibTeX RDF	Static Compaction, Test Vector Compaction, Heat Minimization, Low Power, Built-In Self-Test, Design-for-Testability, Integrated Circuits, switching activity, Scan Chains, Peak power, Embedded Cores, Digital Testing
40	Omri Traub, Glenn H. Holloway, Michael D. Smith 0001	Quality and Speed in Linear-scan Register Allocation.	PLDI	1998	DBLP DOI BibTeX RDF	binpacking, global register allocation, linear scan, graph coloring
40	Yuejian Wu	Diagnosis of Scan Chain Failures.	DFT	1998	DBLP DOI BibTeX RDF	scan chain designs, fault diagnosis, design for testability
40	Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, Janak H. Patel	Partial Scan Selection Based on Dynamic Reachability and Observability Information.	VLSI Design	1998	DBLP DOI BibTeX RDF	test generation, DFT, partial scan
40	Wang-Dauh Tseng, Kuochen Wang	Testable Design and Testing of MCMs Based on Multifrequency Scan.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	boundary scan architecture, multifrequency test, smart substrate, technology mixed, design for testability, VHDL, multichip module
40	A. L. Narasimha Reddy, James C. Wyllie, Ravi Wijayaratne	Disk scheduling in a multimedia I/O system.	ACM Trans. Multim. Comput. Commun. Appl.	2005	DBLP DOI BibTeX RDF	I/O systems, performance evaluation, real-time, multimedia applications, disk scheduling
40	Ozgur Sinanoglu, Alex Orailoglu	Aggressive Test Power Reduction Through Test Stimuli Transformation.	ICCD	2003	DBLP DOI BibTeX RDF
40	Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz	A Low Power Pseudo-Random BIST Technique.	ICCD	2002	DBLP DOI BibTeX RDF
40	Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz	Detectability of internal bridging faults in scan chains.	ASP-DAC	2009	DBLP DOI BibTeX RDF
40	Anshuman Chandra, Yasunari Kanzawa, Rohit Kapur	Proactive management of X's in scan chains for compression.	ISQED	2009	DBLP DOI BibTeX RDF
40	Ho Fai Ko, Nicola Nicolici	Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
40	Ozgur Sinanoglu	Scan Architecture With Align-Encode.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
40	Vandana Pursnani Janeja, Vijayalakshmi Atluri	Random Walks to Identify Anomalous Free-Form Spatial Scan Windows.	IEEE Trans. Knowl. Data Eng.	2008	DBLP DOI BibTeX RDF
40	Hongyou Bian, Weijun Liu, Lun Li, Jinting Xu, Fengjie Tian	Research on a New Kind of Adaptive Parallel Scan Method in Laser Metal Deposition Shaping.	CSSE (2)	2008	DBLP DOI BibTeX RDF
40	Kasper Pedersen	Dobrushin Conditions for Systematic Scan with Block Dynamics.	MFCS	2007	DBLP DOI BibTeX RDF
40	Shubhabrata Sengupta, Mark J. Harris, Yao Zhang 0001, John D. Owens	Scan primitives for GPU computing.	Graphics Hardware	2007	DBLP DOI BibTeX RDF
40	Pattarasinee Bhattarakosol, Vasin Suttichaya	Multiple Equivalent Scale Scan: An Enhancing Technique for Malware Detection.	ICSNC	2007	DBLP DOI BibTeX RDF
40	Vladimir Pekar, Daniel Bystrov, Harald S. Heese, Sebastian P. M. Dries, Stefan Schmidt 0001, Rüdiger Grewer, Chiel J. den Harder, René C. Bergmans, Arjan W. Simonetti, Arianne van Muiswinkel	Automated Planning of Scan Geometries in Spine MRI Scans.	MICCAI (1)	2007	DBLP DOI BibTeX RDF
40	Lifeng He, Yuyan Chao, Kenji Suzuki 0001	A Run-Based Two-Scan Labeling Algorithm.	ICIAR	2007	DBLP DOI BibTeX RDF	label equivalence, run data, pattern recognition, connected components, linear-time algorithm, Labeling algorithm
40	Nan-Cheng Lai, Sying-Jyan Wang, Y.-H. Fu	Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
40	Hao Yang 0004, James Shu, Xiaoqiao Meng, Songwu Lu	SCAN: self-organized network-layer security in mobile ad hoc networks.	IEEE J. Sel. Areas Commun.	2006	DBLP DOI BibTeX RDF
40	Jeremy Lee, Mohammad Tehranipoor, Jim Plusquellic	A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks.	VTS	2006	DBLP DOI BibTeX RDF
40	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy 0001	Low-power scan design using first-level supply gating.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
40	Shantanu Gupta, Tarang Vaish, Santanu Chattopadhyay	Flip-flop chaining architecture for power-efficient scan during test application.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
40	Jinkyu Lee 0005, Nur A. Touba	Low Power BIST Based on Scan Partitioning.	DFT	2005	DBLP DOI BibTeX RDF
40	Yu Huang 0005, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung	Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis.	DATE	2004	DBLP DOI BibTeX RDF
40	Ozgur Sinanoglu, Alex Orailoglu	Scan Power Minimization through Stimulus and Response Transformations.	DATE	2004	DBLP DOI BibTeX RDF
40	Shalini Ghosh, Eric W. MacDonald, Sugato Basu, Nur A. Touba	Low-power weighted pseudo-random BIST using special scan cells.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	weighted pseudo-random testing, low power, built-in self-test
40	Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu	Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing.	ITC	2004	DBLP DOI BibTeX RDF
40	Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi	Scan Test of IP Cores in an ATE Environment.	DELTA	2004	DBLP DOI BibTeX RDF
40	Anshuman Chandra, Krishnendu Chakrabarty	A unified approach to reduce SOC test data volume, scan power and testing time.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
40	Ching-Hwa Cheng	Design Scan Test Strategy for Single Phase Dynamic Circuits.	DFT	2003	DBLP DOI BibTeX RDF
40	Yu Huang 0005, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung	Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault.	ITC	2003	DBLP DOI BibTeX RDF
40	Ranganathan Sankaralingam, Nur A. Touba	Inserting Test Points to Control Peak Power During Scan Testing.	DFT	2002	DBLP DOI BibTeX RDF
40	Ranganathan Sankaralingam, Nur A. Touba	Reducing Test Power During Test Using Programmable Scan Chain Disable.	DELTA	2002	DBLP DOI BibTeX RDF
40	Ondrej Novák, Jiri Nosek	Test-per-Clock Testing of the Circuits with Scan.	IOLTW	2001	DBLP DOI BibTeX RDF
40	Ranganathan Sankaralingam, Nur A. Touba, Bahram Pouya	Reducing Power Dissipation during Test Using Scan Chain Disable.	VTS	2001	DBLP DOI BibTeX RDF
40	Pamela Renton, Michael A. Greenspan, Hoda A. ElMaraghy, Hassen Zghal	Plan-N-Scan: A Robotic System for Collision-Free Autonomous Exploration and Workspace Mapping.	J. Intell. Robotic Syst.	1999	DBLP DOI BibTeX RDF	autonomous exploration, laser-based scanning, gaze planning, voxel maps, robots, collision detection, motion planning
40	Junichi Hirase, Naoki Shindou, Kouji Akahori	Scan Chain Diagnosis Using IDDQ Current Measurement.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
40	Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel	A BIST Structure to Test Delay Faults in a Scan Environment.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
40	José M. Miranda	A BIST and Boundary-Scan Economics Framework.	IEEE Des. Test Comput.	1997	DBLP DOI BibTeX RDF
40	C. P. Ravikumar, Rajamani Rajarajan	Genetic Algorithms for Scan Path Design.	VLSI Design	1996	DBLP DOI BibTeX RDF
40	Sujit Dey, Miodrag Potkonjak	Non-scan design-for-testability of RT-level data paths.	ICCAD	1994	DBLP DOI BibTeX RDF
40	Abu S. M. Hassan, Vinod K. Agarwal, Benoit Nadeau-Dostie, Janusz Rajski	BIST of PCB interconnects using boundary-scan architecture.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
40	Bulent I. Dervisoglu	Application of scan hardware and software for debug and diagnostics in a workstation environment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
39	Irith Pomeranz, Sudhakar M. Reddy	Scan-BIST based on transition probabilities for circuits with single and multiple scan chains.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
39	Mihir A. Shah, Janak H. Patel	Enhancement of the Illinois Scan Architecture for Use with Multiple Scan Inputs.	ISVLSI	2004	DBLP DOI BibTeX RDF
39	Takaki Yoshida, Masafumi Watari	MD-SCAN Method for Low Power Scan Testing.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
37	J. Treurniet	Detecting low-profile scans in TCP anomaly event data.	PST	2006	DBLP DOI BibTeX RDF	distributed scan detection, scan detection, slow scan detection, network security, TCP, anomaly detection
37	Il-soo Lee, Tony Ambler	Two efficient methods to reduce power and testing time.	ISLPED	2005	DBLP DOI BibTeX RDF	reordering scan latches, scan architecture, power, testing time
36	Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara	New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	scan and non-scan, fault efficiency, ATPG
36	Bruce S. Greene, Samiha Mourad	Partial Scan Testing on the Register-Transfer Level.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	RT-level, fault coverage, partial scan, scan design, graph reduction
36	O. A. Petlin, Stephen B. Furber	Scan testing of asynchronous sequential circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits
36	Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel	Cyclic stress tests for full scan circuits.	VTS	1995	DBLP DOI BibTeX RDF	cyclic stress tests, fully testable unpackaged dies, burn-in process, cyclic input sequences, stress related problems, ISCAS89 benchmark circuits, monitored burn-in problems, IC reliability, VLSI, VLSI, logic testing, integrated circuit testing, CMOS, CMOS logic circuits, boundary scan testing, MCMs, integrated circuit reliability, full scan circuits
36	Bapiraju Vinnakota, Nicholas J. Stessman	Reducing test application time in scan design schemes.	VTS	1995	DBLP DOI BibTeX RDF	scan design schemes, computationally intractable problem, test vector correlation, graph theory, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic testing, fault simulation, fault coverage, correlation methods, boundary scan testing, test times, test application time, heuristic techniques
36	O. A. Petlin, Stephen B. Furber	Scan testing of micropipelines.	VTS	1995	DBLP DOI BibTeX RDF	asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines
36	Nazar S. Haider, Nick Kanopoulos	Efficient board interconnect testing using the split boundary scan register.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	IEEE std. 1149.1-1990, split boundary scan register, BIST, boundary scan
36	Bulent I. Dervisoglu	Features of a Scan and Clock Resource chip for providing access to board-level test functions.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	diagnostics bus, design-for-testability, scan, boundary scan, pseudorandom testing
36	Shiao-Li Tsao, Ya-Lien Cheng	Improving Channel Scanning Procedures for WLAN Handoffs.	EUC Workshops	2007	DBLP DOI BibTeX RDF	channel scan, WLAN, mobility management, handoff
36	Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy	Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	output response compression, Built-in self-test, scan design
35	Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas	Gating internal nodes to reduce power during scan shift.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	gating internal nodes, scan shift power reduction, low power test
35	Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara	Graph theoretic approach for scan cell reordering to minimize peak shift power.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	power droop, scan chain reordering, peak power
35	Khadija Houerbi Ramah, Kavé Salamatian, Farouk Kamoun	Scan Surveillance in Internet Networks.	Networking	2009	DBLP DOI BibTeX RDF	scan monitoring, Networks, anomaly detection, Information Theory
35	Ho Fai Ko, Nicola Nicolici	Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Skewed-load, Scan division, At-speed test, Low-power test
35	Nabil Badereddine, Zhanglei Wang, Patrick Girard 0001, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault	A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	DfT, Scan, Test data compression, Low power testing
35	Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	At-speed scan testing, Capture switching activity, X-filling, Test cube, ATPG, Low power testing
35	Rohit Kapur, Subhasish Mitra, Thomas W. Williams	Historical Perspective on Scan Compression.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	scan compression, test data volume reduction, IC testing, test application time reduction
35	Chao-Wen Tzeng, Shi-Yu Huang	UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	multicasting, broadcasting, DFT, test compression, scan test
35	Fei Wang, Yu Hu 0001, Xiaowei Li 0001	Adaptive Diagnostic Pattern Generation for Scan Chains.	DELTA	2008	DBLP DOI BibTeX RDF	very large scale integration (VLSI), testing, diagnosis, Boolean satisfiability, scan chain
35	David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre	Securing Scan Control in Crypto Chips.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Crypto-chips, Security, Scan
35	Markus Seuring	Combining Scan Test and Built-in Self Test.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	MBIST, BIST, scan test, production test, stress test
35	Ismet Bayraktaroglu, Alex Orailoglu	The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Fault diagnosis, finite field arithmetic, scan-based BIST
35	Amit M. Sheth, Jacob Savir	Scan Latch Design for Test Applications.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	shift register latch, scan design, hardware overhead, LSSD
35	Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan	Multimode scan: Test per clock BIST for IP cores.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	SoC, BIST, scan, digital testing
35	Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka	A SoC Test Strategy Based on a Non-Scan DFT Method.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	non-scan DFT, high level design and test, SoC test
35	Andrzej Rucinski 0002, Barbara Dziurla-Rucinska	Boundary Scan as a Test Solution in Microelectronics Curricula.	DELTA	2002	DBLP DOI BibTeX RDF	IEEE 1149.4 standard, Education, Boundary scan
35	Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel	A Scan-BIST Structure to Test Delay Faults in Sequential Circuits.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	BIST, delay faults, scan design
35	Tsung-Chu Huang, Kuen-Jong Lee	An Input Control Technique for Power Reduction in Scan Circuits During Test Application.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	ATPG, VLSI testing, Power Minimization, Low-power Test, Full-scan
35	Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs	Identification of unsettable flip-flops for partial scan and faster ATPG.	ICCAD	1996	DBLP DOI BibTeX RDF	ISCAS89 circuits, deterministic test generation, difficult-to-set hip-hops, hip-hops, state elements, state justification, transformed circuits, unsettable flip-flops identification, logic testing, ATPG, partial scan, sequential circuits test generation
35	Shang-E Tai, Debashis Bhattacharya	A three-stage partial scan design method to ease ATPG.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	minimum feed back vertex set, design for testability, partial scan design
35	Jung-Cheun Lien, Melvin A. Breuer	An optimal scheduling algorithm for testing interconnect using boundary scan.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	Boundary scan, test scheduling, interconnect test
35	Arno Kunzmann, Hans-Joachim Wunderlich	An analytical approach to the partial scan problem.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	partial scan path, sequential test generation, design for testability
35	Boxue Yin, Dong Xiang, Zhen Chen	New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets.	VLSI Design	2009	DBLP DOI BibTeX RDF