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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 3962 occurrences of 1873 keywords
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Results
Found 7741 publication records. Showing 7739 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
44 | Chunsheng Liu, Krishnendu Chakrabarty |
A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10230-10237, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
44 | Irith Pomeranz |
On the use of random limited-scan to improve at-speed randompattern testing of scan circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(9), pp. 1068-1076, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
43 | Thomas W. Williams, Kenneth P. Parker |
Design for Testability - A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(1), pp. 2-15, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
Built-In Logic Block Observation (BILBO), Level Sensitive Scan Design (LSSD), Random Access Scan, Scan/Set Logic, testing, test generation, self test, Signature Analysis, Scan Path |
42 | Jacob Savir |
Module level weighted random patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 274-278, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
module level self-test architecture, pseudorandom pattern generator, universal weighting generator, scan latch, near-optimal weight, signal pins, weight control function, self-test time, logic testing, probability, integrated circuit testing, automatic testing, multivalued logic circuits, boundary scan testing, scan test, weighted random patterns, multiple input signature register |
41 | Massimo Bilancia, Silvestro Montrone, Paola Perchinunno |
A Model-Based Scan Statistics for Detecting Geographical Clustering of Disease. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (1) ![In: Computational Science and Its Applications - ICCSA 2009, International Conference, Seoul, Korea, June 29-July 2, 2009, Proceedings, Part I, pp. 353-368, 2009, Springer, 978-3-642-02453-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Disease clustering, Model-based scan statistics, BYM model, Lung cancer mortality, Spatial scan statistics |
41 | Yuri Dotsenko, Naga K. Govindaraju, Peter-Pike J. Sloan, Charles Boyd, John Manferdelli |
Fast scan algorithms on graphics processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 22nd Annual International Conference on Supercomputing, ICS 2008, Island of Kos, Greece, June 7-12, 2008, pp. 205-213, 2008, ACM, 978-1-60558-158-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
all-prefix-sum, segmented scan, parallel algorithm, GPU, GPGPU, scan, HPC, many-core |
41 | King Leong Lee, Nadir Z. Basturkmen, Srikanth Venkataraman |
Diagnosis of Scan Clock Failures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 67-72, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
scan clock, diagnosis, scan chain |
41 | Young-Ho Choi, Se-Young Oh |
Map building through pseudo dense scan matching using visual sonar data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Auton. Robots ![In: Auton. Robots 23(4), pp. 293-304, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Robust visual sonar, Pseudo dense scan, Adaptive scan matching, Trajectory correction |
41 | Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda |
Systematic Scan Reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 738-743, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
systematic scan reconfiguration, test data compression technique, single-stuck fault test sets, transition fault test sets, scan chains |
41 | Arun Balakrishnan, Srimat T. Chakradhar |
Retiming with logic duplication transformation: theory and an application to partial scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 296-302, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
logic duplication transformation, partial scan application, RLD configurations, RLD transformation, testability metrics, scan flip-flops, sequential circuit design, linear programming, timing, integer programming, logic design, sequential circuits, logic CAD, polynomial time algorithm, integer linear program, flip-flops, retiming, integrated circuit design, circuit CAD, integrated logic circuits, objective function |
40 | Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi |
A Selective Trigger Scan Architecture for VLSI Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(3), pp. 316-328, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Delay Testing, Test Compression, Test Application Time, Scan Test, Test Data Volume, Test Power |
40 | Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang |
A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(1), pp. 9:1-9:27, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
profiling, design for testability, Diagnosis, fault, scan chain |
40 | Anshuman Chandra, Rohit Kapur |
Bounded Adjacent Fill for Low Capture Power Scan Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 131-138, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
capture power, random fill, shift power, test, low power, scan |
40 | Arno Wagner, Thomas Dübendorfer, Roman Hiestand, Christoph Göldi, Bernhard Plattner |
A Fast Worm Scan Detection Tool for VPN Congestion Avoidance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DIMVA ![In: Detection of Intrusions and Malware & Vulnerability Assessment, Third International Conference, DIMVA 2006, Berlin, Germany, July 13-14, 2006, Proceedings, pp. 181-194, 2006, Springer, 3-540-36014-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Bro, detection, worm, Scan, gateway, VPN |
40 | Christian Wimmer, Hanspeter Mössenböck |
Optimized interval splitting in a linear scan register allocator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VEE ![In: Proceedings of the 1st International Conference on Virtual Execution Environments, VEE 2005, Chicago, IL, USA, June 11-12, 2005, pp. 132-141, 2005, ACM, 1-59593-047-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
linear scan, java, optimization, compilers, graph-coloring, register allocation, just-in-time compilation |
40 | Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian |
Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(10), pp. 1007-1019, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
relay propagation test, multiprocessor systems, Boundary scan |
40 | Sambhunath Biswas |
Hilbert Scan and Image Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPR ![In: 15th International Conference on Pattern Recognition, ICPR'00, Barcelona, Spain, September 3-8, 2000., pp. 3211-3214, 2000, IEEE Computer Society, 0-7695-0750-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Hilbert scan, Hilbert image, Bezier-Bernstein polynomial, Huffman coding |
40 | Ranganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba |
Static Compaction Techniques to Control Scan Vector Power Dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 35-42, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Static Compaction, Test Vector Compaction, Heat Minimization, Low Power, Built-In Self-Test, Design-for-Testability, Integrated Circuits, switching activity, Scan Chains, Peak power, Embedded Cores, Digital Testing |
40 | Omri Traub, Glenn H. Holloway, Michael D. Smith 0001 |
Quality and Speed in Linear-scan Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN '98 Conference on Programming Language Design and Implementation (PLDI), Montreal, Canada, June 17-19, 1998, pp. 142-151, 1998, ACM, 0-89791-987-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
binpacking, global register allocation, linear scan, graph coloring |
40 | Yuejian Wu |
Diagnosis of Scan Chain Failures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 217-, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
scan chain designs, fault diagnosis, design for testability |
40 | Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, Janak H. Patel |
Partial Scan Selection Based on Dynamic Reachability and Observability Information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 174-180, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
test generation, DFT, partial scan |
40 | Wang-Dauh Tseng, Kuochen Wang |
Testable Design and Testing of MCMs Based on Multifrequency Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 75-, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
boundary scan architecture, multifrequency test, smart substrate, technology mixed, design for testability, VHDL, multichip module |
40 | A. L. Narasimha Reddy, James C. Wyllie, Ravi Wijayaratne |
Disk scheduling in a multimedia I/O system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Multim. Comput. Commun. Appl. ![In: ACM Trans. Multim. Comput. Commun. Appl. 1(1), pp. 37-59, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
I/O systems, performance evaluation, real-time, multimedia applications, disk scheduling |
40 | Ozgur Sinanoglu, Alex Orailoglu |
Aggressive Test Power Reduction Through Test Stimuli Transformation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 542-547, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
40 | Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz |
A Low Power Pseudo-Random BIST Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 468-473, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
40 | Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
Detectability of internal bridging faults in scan chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 678-683, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
40 | Anshuman Chandra, Yasunari Kanzawa, Rohit Kapur |
Proactive management of X's in scan chains for compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 260-265, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
40 | Ho Fai Ko, Nicola Nicolici |
Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11), pp. 2092-2097, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
40 | Ozgur Sinanoglu |
Scan Architecture With Align-Encode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12), pp. 2303-2316, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
40 | Vandana Pursnani Janeja, Vijayalakshmi Atluri |
Random Walks to Identify Anomalous Free-Form Spatial Scan Windows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Knowl. Data Eng. ![In: IEEE Trans. Knowl. Data Eng. 20(10), pp. 1378-1392, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
40 | Hongyou Bian, Weijun Liu, Lun Li, Jinting Xu, Fengjie Tian |
Research on a New Kind of Adaptive Parallel Scan Method in Laser Metal Deposition Shaping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSSE (2) ![In: International Conference on Computer Science and Software Engineering, CSSE 2008, Volume 2: Software Engineering, December 12-14, 2008, Wuhan, China, pp. 1012-1015, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
40 | Kasper Pedersen |
Dobrushin Conditions for Systematic Scan with Block Dynamics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MFCS ![In: Mathematical Foundations of Computer Science 2007, 32nd International Symposium, MFCS 2007, Ceský Krumlov, Czech Republic, August 26-31, 2007, Proceedings, pp. 264-275, 2007, Springer, 978-3-540-74455-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Shubhabrata Sengupta, Mark J. Harris, Yao Zhang 0001, John D. Owens |
Scan primitives for GPU computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Graphics Hardware ![In: Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Conference on Graphics Hardware 2007, San Diego, California, USA, August 4-5, 2007, pp. 97-106, 2007, Eurographics Association, 978-1-59593-625-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Pattarasinee Bhattarakosol, Vasin Suttichaya |
Multiple Equivalent Scale Scan: An Enhancing Technique for Malware Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSNC ![In: Proceedings of the Second International Conference on Systems and Networks Communications (ICSNC 2007), August 25-31, 2007, Cap Esterel, French Riviera, France, pp. 71, 2007, IEEE Computer Society, 0-7695-2938-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Vladimir Pekar, Daniel Bystrov, Harald S. Heese, Sebastian P. M. Dries, Stefan Schmidt 0001, Rüdiger Grewer, Chiel J. den Harder, René C. Bergmans, Arjan W. Simonetti, Arianne van Muiswinkel |
Automated Planning of Scan Geometries in Spine MRI Scans. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICCAI (1) ![In: Medical Image Computing and Computer-Assisted Intervention - MICCAI 2007, 10th International Conference, Brisbane, Australia, October 29 - November 2, 2007, Proceedings, Part I, pp. 601-608, 2007, Springer, 978-3-540-75756-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Lifeng He, Yuyan Chao, Kenji Suzuki 0001 |
A Run-Based Two-Scan Labeling Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIAR ![In: Image Analysis and Recognition, 4th International Conference, ICIAR 2007, Montreal, Canada, August 22-24, 2007, Proceedings, pp. 131-142, 2007, Springer, 978-3-540-74258-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
label equivalence, run data, pattern recognition, connected components, linear-time algorithm, Labeling algorithm |
40 | Nan-Cheng Lai, Sying-Jyan Wang, Y.-H. Fu |
Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2586-2594, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Hao Yang 0004, James Shu, Xiaoqiao Meng, Songwu Lu |
SCAN: self-organized network-layer security in mobile ad hoc networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Sel. Areas Commun. ![In: IEEE J. Sel. Areas Commun. 24(2), pp. 261-273, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Jeremy Lee, Mohammad Tehranipoor, Jim Plusquellic |
A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 94-99, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy 0001 |
Low-power scan design using first-level supply gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(3), pp. 384-395, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
40 | Shantanu Gupta, Tarang Vaish, Santanu Chattopadhyay |
Flip-flop chaining architecture for power-efficient scan during test application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 410-413, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
40 | Jinkyu Lee 0005, Nur A. Touba |
Low Power BIST Based on Scan Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 33-41, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
40 | Yu Huang 0005, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung |
Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1072-1077, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Ozgur Sinanoglu, Alex Orailoglu |
Scan Power Minimization through Stimulus and Response Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 404-409, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Shalini Ghosh, Eric W. MacDonald, Sugato Basu, Nur A. Touba |
Low-power weighted pseudo-random BIST using special scan cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 86-91, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
weighted pseudo-random testing, low power, built-in self-test |
40 | Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu |
Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1118-1127, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi |
Scan Test of IP Cores in an ATE Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 2nd IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2004), 28-30 January 2004, Perth, Australia, pp. 281-286, 2004, IEEE Computer Society, 0-7695-2081-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Anshuman Chandra, Krishnendu Chakrabarty |
A unified approach to reduce SOC test data volume, scan power and testing time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3), pp. 352-363, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
40 | Ching-Hwa Cheng |
Design Scan Test Strategy for Single Phase Dynamic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 199-, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
40 | Yu Huang 0005, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung |
Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 319-328, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
40 | Ranganathan Sankaralingam, Nur A. Touba |
Inserting Test Points to Control Peak Power During Scan Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 138-146, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
40 | Ranganathan Sankaralingam, Nur A. Touba |
Reducing Test Power During Test Using Programmable Scan Chain Disable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 159-166, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
40 | Ondrej Novák, Jiri Nosek |
Test-per-Clock Testing of the Circuits with Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 9-11 July 2001, Taormina, Italy, pp. 90-, 2001, IEEE Computer Society, 0-7695-1290-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
40 | Ranganathan Sankaralingam, Nur A. Touba, Bahram Pouya |
Reducing Power Dissipation during Test Using Scan Chain Disable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 319-325, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
40 | Pamela Renton, Michael A. Greenspan, Hoda A. ElMaraghy, Hassen Zghal |
Plan-N-Scan: A Robotic System for Collision-Free Autonomous Exploration and Workspace Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 24(3), pp. 207-234, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
autonomous exploration, laser-based scanning, gaze planning, voxel maps, robots, collision detection, motion planning |
40 | Junichi Hirase, Naoki Shindou, Kouji Akahori |
Scan Chain Diagnosis Using IDDQ Current Measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 153-157, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
40 | Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel |
A BIST Structure to Test Delay Faults in a Scan Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 435-439, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
40 | José M. Miranda |
A BIST and Boundary-Scan Economics Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 14(3), pp. 17-23, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
40 | C. P. Ravikumar, Rajamani Rajarajan |
Genetic Algorithms for Scan Path Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 118-121, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
40 | Sujit Dey, Miodrag Potkonjak |
Non-scan design-for-testability of RT-level data paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 640-645, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
40 | Abu S. M. Hassan, Vinod K. Agarwal, Benoit Nadeau-Dostie, Janusz Rajski |
BIST of PCB interconnects using boundary-scan architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(10), pp. 1278-1288, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
40 | Bulent I. Dervisoglu |
Application of scan hardware and software for debug and diagnostics in a workstation environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(6), pp. 612-620, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
39 | Irith Pomeranz, Sudhakar M. Reddy |
Scan-BIST based on transition probabilities for circuits with single and multiple scan chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3), pp. 591-596, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
39 | Mihir A. Shah, Janak H. Patel |
Enhancement of the Illinois Scan Architecture for Use with Multiple Scan Inputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 167-172, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
39 | Takaki Yoshida, Masafumi Watari |
MD-SCAN Method for Low Power Scan Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 80-85, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
37 | J. Treurniet |
Detecting low-profile scans in TCP anomaly event data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PST ![In: Proceedings of the 2006 International Conference on Privacy, Security and Trust: Bridge the Gap Between PST Technologies and Business Services, PST 2006, Markham, Ontario, Canada, October 30 - November 1, 2006, pp. 17, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
distributed scan detection, scan detection, slow scan detection, network security, TCP, anomaly detection |
37 | Il-soo Lee, Tony Ambler |
Two efficient methods to reduce power and testing time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 167-172, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
reordering scan latches, scan architecture, power, testing time |
36 | Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara |
New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(3), pp. 315-323, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
scan and non-scan, fault efficiency, ATPG |
36 | Bruce S. Greene, Samiha Mourad |
Partial Scan Testing on the Register-Transfer Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(6), pp. 613-626, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
RT-level, fault coverage, partial scan, scan design, graph reduction |
36 | O. A. Petlin, Stephen B. Furber |
Scan testing of asynchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 224-229, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits |
36 | Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel |
Cyclic stress tests for full scan circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 89-94, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
cyclic stress tests, fully testable unpackaged dies, burn-in process, cyclic input sequences, stress related problems, ISCAS89 benchmark circuits, monitored burn-in problems, IC reliability, VLSI, VLSI, logic testing, integrated circuit testing, CMOS, CMOS logic circuits, boundary scan testing, MCMs, integrated circuit reliability, full scan circuits |
36 | Bapiraju Vinnakota, Nicholas J. Stessman |
Reducing test application time in scan design schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 367-373, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
scan design schemes, computationally intractable problem, test vector correlation, graph theory, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic testing, fault simulation, fault coverage, correlation methods, boundary scan testing, test times, test application time, heuristic techniques |
36 | O. A. Petlin, Stephen B. Furber |
Scan testing of micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 296-303, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines |
36 | Nazar S. Haider, Nick Kanopoulos |
Efficient board interconnect testing using the split boundary scan register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(2), pp. 181-189, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
IEEE std. 1149.1-1990, split boundary scan register, BIST, boundary scan |
36 | Bulent I. Dervisoglu |
Features of a Scan and Clock Resource chip for providing access to board-level test functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(1), pp. 107-115, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
diagnostics bus, design-for-testability, scan, boundary scan, pseudorandom testing |
36 | Shiao-Li Tsao, Ya-Lien Cheng |
Improving Channel Scanning Procedures for WLAN Handoffs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC Workshops ![In: Emerging Directions in Embedded and Ubiquitous Computing, EUC 2007 Workshops: TRUST, WSOC, NCUS, UUWSN, USN, ESO, and SECUBIQ, Taipei, Taiwan, December 17-20, 2007, Proceedings, pp. 285-296, 2007, Springer, 978-3-540-77089-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
channel scan, WLAN, mobility management, handoff |
36 | Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy |
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(1), pp. 83-88, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
output response compression, Built-in self-test, scan design |
35 | Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas |
Gating internal nodes to reduce power during scan shift. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 79-84, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
gating internal nodes, scan shift power reduction, low power test |
35 | Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara |
Graph theoretic approach for scan cell reordering to minimize peak shift power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 73-78, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
power droop, scan chain reordering, peak power |
35 | Khadija Houerbi Ramah, Kavé Salamatian, Farouk Kamoun |
Scan Surveillance in Internet Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networking ![In: NETWORKING 2009, 8th International IFIP-TC 6 Networking Conference, Aachen, Germany, May 11-15, 2009. Proceedings, pp. 614-625, 2009, Springer, 978-3-642-01398-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
scan monitoring, Networks, anomaly detection, Information Theory |
35 | Ho Fai Ko, Nicola Nicolici |
Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(4), pp. 393-403, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Skewed-load, Scan division, At-speed test, Low-power test |
35 | Nabil Badereddine, Zhanglei Wang, Patrick Girard 0001, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault |
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(4), pp. 353-364, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
DfT, Scan, Test data compression, Low power testing |
35 | Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita |
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(4), pp. 379-391, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
At-speed scan testing, Capture switching activity, X-filling, Test cube, ATPG, Low power testing |
35 | Rohit Kapur, Subhasish Mitra, Thomas W. Williams |
Historical Perspective on Scan Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(2), pp. 114-120, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
scan compression, test data volume reduction, IC testing, test application time reduction |
35 | Chao-Wen Tzeng, Shi-Yu Huang |
UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(2), pp. 132-140, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
multicasting, broadcasting, DFT, test compression, scan test |
35 | Fei Wang, Yu Hu 0001, Xiaowei Li 0001 |
Adaptive Diagnostic Pattern Generation for Scan Chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 129-132, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
very large scale integration (VLSI), testing, diagnosis, Boolean satisfiability, scan chain |
35 | David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre |
Securing Scan Control in Crypto Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(5), pp. 457-464, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Crypto-chips, Security, Scan |
35 | Markus Seuring |
Combining Scan Test and Built-in Self Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(3), pp. 297-299, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
MBIST, BIST, scan test, production test, stress test |
35 | Ismet Bayraktaroglu, Alex Orailoglu |
The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(1), pp. 61-75, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Fault diagnosis, finite field arithmetic, scan-based BIST |
35 | Amit M. Sheth, Jacob Savir |
Scan Latch Design for Test Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(2), pp. 213-216, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
shift register latch, scan design, hardware overhead, LSSD |
35 | Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan |
Multimode scan: Test per clock BIST for IP cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 8(4), pp. 491-505, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
SoC, BIST, scan, digital testing |
35 | Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka |
A SoC Test Strategy Based on a Non-Scan DFT Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 305-310, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
non-scan DFT, high level design and test, SoC test |
35 | Andrzej Rucinski 0002, Barbara Dziurla-Rucinska |
Boundary Scan as a Test Solution in Microelectronics Curricula. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 214-218, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
IEEE 1149.4 standard, Education, Boundary scan |
35 | Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel |
A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(1-2), pp. 95-102, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
BIST, delay faults, scan design |
35 | Tsung-Chu Huang, Kuen-Jong Lee |
An Input Control Technique for Power Reduction in Scan Circuits During Test Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 315-320, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
ATPG, VLSI testing, Power Minimization, Low-power Test, Full-scan |
35 | Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs |
Identification of unsettable flip-flops for partial scan and faster ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 63-66, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
ISCAS89 circuits, deterministic test generation, difficult-to-set hip-hops, hip-hops, state elements, state justification, transformed circuits, unsettable flip-flops identification, logic testing, ATPG, partial scan, sequential circuits test generation |
35 | Shang-E Tai, Debashis Bhattacharya |
A three-stage partial scan design method to ease ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 7(1-2), pp. 95-104, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
minimum feed back vertex set, design for testability, partial scan design |
35 | Jung-Cheun Lien, Melvin A. Breuer |
An optimal scheduling algorithm for testing interconnect using boundary scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(1), pp. 117-130, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
Boundary scan, test scheduling, interconnect test |
35 | Arno Kunzmann, Hans-Joachim Wunderlich |
An analytical approach to the partial scan problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 1(2), pp. 163-174, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
partial scan path, sequential test generation, design for testability |
35 | Boxue Yin, Dong Xiang, Zhen Chen |
New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 221-226, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
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