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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 1444 occurrences of 813 keywords
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Results
Found 4301 publication records. Showing 4296 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
15 | Russell Tessier, Snigdha Jana |
Incremental compilation for parallel logic verification systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(5), pp. 623-636, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
15 | J. Bryan Lewis, Ivo Bolsens, Rudy Lauwereins, Chris Wheddon, Bhusan Gupta, Yankin Tanurhan |
Reconfigurable SoC - What Will it Look Like? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 660-662, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Sudhakar Yalamanchili |
The Customization Landscape for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2002, 9th International Conference, Bangalore, India, December 18-21, 2002, Proceedings, pp. 693-696, 2002, Springer, 3-540-00303-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Helena Krupnova, Veronique Meurou, Christophe Barnichon, Carlos Serra, Farid Morsi |
How Fast Is Rapid FPGA-based Prototyping: Lessons and Challenges from the Digital TV Design Prototyping Project. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 26-35, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Sandeep Dhar, Dragan Maksimovic, Bruno Kranzen |
Closed-loop adaptive voltage scaling controller for standard-cell ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 103-107, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
delay-line, variable-voltage, low-power, energy-efficient, design methodology, circuit design, standard-cell, DC-DC converter |
15 | Shih-Hsu Huang, Chu-Liao Wang |
An effective floorplan-based power distribution network design methodology under reliability constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 353-356, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Sornavalli Ramanathan, Rituparna Mandal |
Low Power Solution for Wireless Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 615-618, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
2.5G, Multi-Vt, CMOS, 3G |
15 | Peter Hallschmid, Steven J. E. Wilton |
Detailed routing architectures for embedded programmable logic IP cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 69-74, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
FPGA, programmable logic, detailed routing, SoC design, embedded cores |
15 | Josef Schmid, Timo Schüring, Christoph Smalla |
Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 337-342, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Sabyasachi Sengupta, Somavalli Ramanathan, Biswadeep Chatterjee, Dibyendu Goswami |
Minimizing Area and Maximizing Porosity for Cell Layouts Using Innovative Routing Strategies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 353-358, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Ioannis Andreadis |
A Color Coordinate Normalizer Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 28(1-2), pp. 181-196, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
real-time imaging, pattern recognition, color |
15 | Shantanu Tarafdar, Miriam Leeser |
A data-centric approach to high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11), pp. 1251-1267, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Michael Reinhardt, Michael Santarini |
What is Design Quality? How can Quality in Electronic Design be Quantified? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 31-, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Luiz André Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, Ben Verghese |
Piranha: a scalable architecture based on single-chip multiprocessing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada, pp. 282-293, 2000, IEEE Computer Society, 978-1-58113-232-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Adel Baganne, Jean Luc Philippe, Eric Martin 0001 |
A Co-Design Methodology for Telecommunication Systems: A Case Study of an Acoustic Echo Canceller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 22(1), pp. 21-29, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Jung Hyun Choi, Sergio Bampi |
OTA Amplifiers Design on Digital Sea-of-Transistors Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 776-777, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Jose Luis Nunez, Claudia Feregrino, Simon R. Jones, Stephen Bateman |
The X-MatchLITE FPGA-Based Data Compressor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1126-1132, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Romain Kamdem, Alain Fonkoua, Andre Zenatti |
Hardware/Software Partitioning of Multirate System Using Static Scheduling Theory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 640-645, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
code-sign, scheduling, real time, Codesign, hardware/software partitioning, target architecture |
15 | Jens-Peter Kaps, Christof Paar |
Fast DES Implementation for FPGAs and Its Application to a Universal Key-Search Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Selected Areas in Cryptography ![In: Selected Areas in Cryptography '98, SAC'98, Kingston, Ontario, Canada, August 17-18, 1998, Proceedings, pp. 234-247, 1998, Springer, 3-540-65894-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Helena Krupnova, Vu DucAnh Dinh, Gabriele Saucier |
A Knowledge-Based System for Prototyping on FPFAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings, pp. 89-98, 1998, Springer, 3-540-64948-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Tsuneo Ikedo, William L. Martens |
Multimedia Processor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMCS ![In: IEEE International Conference on Multimedia Computing and Systems, ICMCS 1998, Austin, Texas, USA, June 28 - July 1, 1998, pp. 316-325, 1998, IEEE Computer Society, 0-8186-8557-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
15 | J. Patrick Brennan, Alvar Dean, Stephan Kenyon, Sebastian Ventrone |
Low power methodology and design techniques for processor design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 268-273, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Marco Cavadini, Matthias Wosnitza, Markus Thaler, Gerhard Tröster |
A Multiprocessor System for Real Time High Resolution Image Correlation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 384-391, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
15 | Josef Fleischmann, Rolf Schlagenhaft, Martin Peller, Norbert Fröhlich |
OLIVIA: Objectoriented Logicsimulation Implementing the VITAL Standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 13-15 March 1997, Urbana, IL, USA, pp. 51-, 1997, IEEE Computer Society, 0-8186-7904-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
15 | Mani B. Srivastava, Anantha P. Chandrakasan, Robert W. Brodersen |
Predictive system shutdown and other architectural techniques for energy efficient programmable computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(1), pp. 42-55, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
15 | Mani B. Srivastava, Robert W. Brodersen |
System level hardware module generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(1), pp. 20-35, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
15 | Chun-Chao Yeh, Chun-Hsing Wu, Jie-Yong Juang |
Design and implementation of a multicomputer interconnection network using FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 3rd IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '95), 19-21 April 1995, Napa Valley, CA, USA, pp. 56-60, 1995, IEEE Computer Society, 0-8186-7086-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
15 | Yao-Wen Chang, Shashidhar Thakur, Kai Zhu 0001, D. F. Wong 0001 |
A new global routing algorithm for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 356-361, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
15 | Jef L. van Meerbergen, Paul E. R. Lippens, B. T. McSweeney, Wim F. J. Verhaegh, Albert van der Werf, A. van Zanten |
Architectural strategies for high-throughput applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 5(2-3), pp. 201-220, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
15 | Alfred E. Dunlop |
Will Cell Generation Displace Standard Cells? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 528, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
15 | Nan Hua, Eric Norige, Sailesh Kumar, Bill Lynch |
Non-crypto Hardware Hash Functions for High Performance Networking ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: 2011 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), Brooklyn, NY, USA, October 3-4, 2011, pp. 156-166, 2011, IEEE Computer Society, 978-1-4577-1454-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
Networking ASIC, Evaluation, Hash Function |
15 | B. K. Mishra 0001, Sandhya Save |
Novel CAD Design Methodology for Two Stage Opamp with Noise-Power Balance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAP ![In: 2010 International Conference on Signal Acquisition and Processing, ICSAP 2010, Bangalore, India, February 9-10, 2010, pp. 287-290, 2010, IEEE Computer Society, 978-0-7695-3960-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Analog circuit designs methodologies, Analog design automation, Op-amps, AMS, Simulated Annealing, CAD, SoC, ASIC, SPICE, EDA tools |
15 | Jihene Malek, Abderrahim Sebri, Souhir Mabrouk, Kholdoun Torki, Rached Tourki |
Automated Breast Cancer Diagnosis Based on GVF-Snake Segmentation, Wavelet Features Extraction and Fuzzy Classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 55(1-3), pp. 49-66, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
The automatic diagnosis of breast cancer, GVF-Snake, Wavelet feature extraction, Segmentation, ASIC, Hardware implementation, Fuzzy classifiers |
15 | Pankaj Bhagawat, Rajballav Dash, Gwan S. Choi |
Array like runtime reconfigurable MIMO detectors for 802.11n WLAN: a design case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 751-756, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fixed sphere decoding (FSD) algorithm, on-the-fly reconfigurability, ASIC, MIMO systems, 802.11n |
15 | Miroslav Knezevic, Ingrid Verbauwhede |
Hardware evaluation of the Luffa hash family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WESS ![In: Proceedings of the 4th Workshop on Embedded Systems Security, WESS 2009, Grenoble, France, October 15, 2009, 2009, ACM, 978-1-60558-700-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Luffa hash algorithm, SHA-3 competition, ASIC implementations |
15 | Bella Dubrov, Haggai Eran, Ari Freund 0001, Edward F. Mark, Shyam Ramji, Timothy A. Schell |
Pin Assignment Using Stochastic Local Search Constraint Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CP ![In: Principles and Practice of Constraint Programming - CP 2009, 15th International Conference, CP 2009, Lisbon, Portugal, September 20-24, 2009, Proceedings, pp. 35-49, 2009, Springer, 978-3-642-04243-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
ASIC, Constraint Programming, EDA, Stochastic Local Search, Chip Design, Pin Assignment |
15 | Yang Sun 0001, Joseph R. Cavallaro |
High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 445-450, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
mimo detection, VLSI architecture, ASIC design |
15 | Mahmoud Moadeli, Partha P. Maji, Wim Vanderbauwhede |
Quarc: A High-Efficiency Network on-Chip Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA ![In: The IEEE 23rd International Conference on Advanced Information Networking and Applications, AINA 2009, Bradford, United Kingdom, May 26-29, 2009, pp. 98-105, 2009, IEEE Computer Society, 978-0-7695-3638-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Quarc, Network On Chip, ASIC |
15 | Pachara V. Rao, Cyril Prasanna Raj, S. Ravi 0001 |
VLSI Design and Analysis of Multipliers for Low Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IIH-MSP ![In: Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2009), Kyoto, Japan, 12-14 September, 2009, Proceedings, pp. 1354-1357, 2009, IEEE Computer Society, 978-1-4244-4717-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Low Power, Delay, CMOS, Multipliers, Area, ASIC Implementation |
15 | Kevin Fan, Hyunchul Park 0001, Manjunath Kudlur, Scott A. Mahlke |
Modulo scheduling for highly customized datapaths to increase hardware reusability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Sixth International Symposium on Code Generation and Optimization (CGO 2008), April 5-9, 2008, Boston, MA, USA, pp. 124-133, 2008, ACM, 978-1-59593-978-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
programmable asic, modulo scheduling, loop accelerator |
15 | Pil Woo Chun, Jamin Islam, Valeri Kirischian, Lev Kirischian |
Improving Cost-Effectiveness Using a Micro-level Static Architecture for Stream Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 368-373, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, ASIC, cost-effectiveness, run-time reconfiguration, stream application |
15 | Dai Yamamoto, Jun Yajima, Kouichi Itoh |
A Very Compact Hardware Implementation of the MISTY1 Block Cipher. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2008, 10th International Workshop, Washington, D.C., USA, August 10-13, 2008. Proceedings, pp. 315-330, 2008, Springer, 978-3-540-85052-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
MISTY1, Compact Implementation, Block cipher, Hardware, ASIC |
15 | Florian Auernhammer, Patricia Sagmeister |
Design optimization of a highly parallel InfiniBand host channel adapter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: Proceedings of the 2008 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2008, San Jose, California, USA, November 6-7, 2008, pp. 171-180, 2008, ACM, 978-1-60558-346-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
HCA, host channel adapter, optimization, design, pipeline, ASIC, InfiniBand |
15 | Osman Musa Abdulkarim, Maitham Shams |
A symmetric mos current-mode logic universal gate for high speed applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 212-215, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
MCML, SCL, VLSI, ASIC |
15 | Zhan Guo, Peter Nilsson 0001 |
A VLSI Architecture of the Square Root Algorithm for V-BLAST Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 44(3), pp. 219-230, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
square root algorithm, VLSI, wireless LAN, ASIC, MIMO, fixed-point, 3G, HSDPA, CORDIC, BLAST |
15 | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko |
Yield enhancements of design-specific FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 93-100, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
design-specific FPGA, interconnect faults, interconnect utilization, yield enhancement, yield prediction, structured ASIC, FPGA interconnect |
15 | Steven Swanson, Andrew Putnam, Martha Mercaldi, Ken Michelson, Andrew Petersen 0001, Andrew Schwerin, Mark Oskin, Susan J. Eggers |
Area-Performance Trade-offs in Tiled Dataflow Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 33rd International Symposium on Computer Architecture (ISCA 2006), June 17-21, 2006, Boston, MA, USA, pp. 314-326, 2006, IEEE Computer Society, 0-7695-2608-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
WaveScalar, ASIC, RTL, Dataflow computing |
15 | David E. Taylor, Andreas Herkersdorf, Andreas C. Döring, Gero Dittmann |
Robust header compression (ROHC) in next-generation network processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 13(4), pp. 755-768, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
ROHC, hardware assist, FPGA, ASIC, network processor, ASIP, reconfigurable hardware, header compression |
15 | Rob Roy, Debashis Bhattacharya, Vamsi Boppana |
Transistor-Level Optimization of Digital Designs with Flex Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 38(2), pp. 53-61, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
ASIC design methodology, integrated circuit design, power optimization, design and test, high-performance design |
15 | Tsung-Han Tsai 0001, Ya-Chau Yang, Chun-Nan Liu |
A Hardware/Software Co-Design of MP3 Audio Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 41(1), pp. 111-127, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
IMDCT, Filterbank, VLSI, DSP, ASIC, MPEG, Co-Design, MP3 |
15 | Alexander B. Smirnov, Alexander Taubin, Ming Su, Mark G. Karpovsky |
An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 6-9 June 2005, St. Malo, France, pp. 68-76, 2005, IEEE Computer Society, 0-7695-2363-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
asynchronous EDA, QDI, synthesis, ASIC, HDL |
15 | Alireza Hodjat, David Hwang 0001, Bo-Cheng Lai, Kris Tiri, Ingrid Verbauwhede |
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 60-63, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
crypto-processor, security, FPGA, VLSI, cryptography, advanced encryption standard (AES), ASIC, hardware architectures |
15 | Hamid Fadishei, Morteza Saheb Zamani, Masoud Sabaei |
A novel reconfigurable hardware architecture for IP address lookup. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: Proceedings of the 2005 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2005, Princeton, New Jersey, USA, October 16-18, 2005, pp. 81-90, 2005, ACM, 1-59593-082-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
field-programmable gate array (FPGA), application specific integrated circuit (ASIC), hashing, reconfigurable hardware, longest prefix matching, IP address lookup |
15 | José Vieira do Vale Neto |
Design sequence for a LC-tank voltage controlled oscillator in CMOS for RF. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 76-81, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
LC-tank, ASIC, CMOS, VCO, radio frequency |
15 | Victor V. Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno |
Design methodology for semi custom processor cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 448-452, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
design, methodology, synthesis, microprocessor, ASIC, core |
15 | Nobuyuki Ohba, Kohji Takano |
An SoC design methodology using FPGAs and embedded microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 747-752, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
mixed-level verification, SoC, ASIC, FPGA prototyping |
15 | Changchun Shi, Robert W. Brodersen |
Automated fixed-point data-type optimization tool for signal processing and communication systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 478-483, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
optimization, FPGA, digital signal processing, ASIC, communication systems, fixed-point arithmetic |
15 | Akashi Satoh, Kohji Takano |
A Scalable Dual-Field Elliptic Curve Cryptographic Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(4), pp. 449-460, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
high-speed hardware, Elliptic curve cryptography, public key cryptography, Montgomery multiplication, Galois field, ASIC implementation |
15 | Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen |
Design theory and implementation for low-power segmented bus systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 8(1), pp. 38-54, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
OLA tree, bus graph model, bus segmentation, bus segmentation cell, low-power design flow, low-power design, ASIC design |
15 | Leon Stok, John M. Cohn |
There is life left in ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003, pp. 48-50, 2003, ACM, 1-58113-650-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
design cost, ASIC, design tools |
15 | Binu K. Mathew, Al Davis, Zhen Fang 0002 |
A low-power accelerator for the SPHINX 3 speech recognition system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 210-219, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
embedded systems, speech recognition, low power design, ASIC, special purpose hardware |
15 | Krishna Sekar, Kanishka Lahiri, Sujit Dey |
Dynamic Platform Management for Configurable Platform-Based System-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 641-649, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
ASIC |
15 | Stephan Held, Bernhard Korte, Jens Maßberg, Matthias Ringe, Jens Vygen |
Clock Scheduling and Clocktree Construction for High Performance ASICS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 232-240, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
ASIC |
15 | Slavek Bulach, Anton Brauchle, Hans-Jörg Pfleiderer, Zdenek Kucerovsky |
Design and Implementation of Discrete Event Control Systems: A Petri Net Based Hardware Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Discret. Event Dyn. Syst. ![In: Discret. Event Dyn. Syst. 12(3), pp. 287-309, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Petri nets, ASIC, DES, event-driven, programmable controller |
15 | Daniela De Venuto, Michael J. Ohletz, Bruno Riccò |
Digital Window Comparator DfT Scheme for Mixed-Signal ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(2), pp. 121-128, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
mixed-signal ASIC, window comparator, GO/NOGO test, signal level evaluation, DfT |
15 | H. Safiri, Majid Ahmadi, Graham A. Jullien, William C. Miller |
A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 31(2), pp. 91-100, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
genetic algorithm, ASIC, digital filter, integer multiplication, common subexpressions |
15 | Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee |
PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 188-197, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FPGA, low-power, compiler, SoC, synthesis, pipelining, VHDL, IP, ASIC, high-performance, FSM, Verilog, HDL, levelization |
15 | William C. Athas, Lynn Youngs, Andrew Reinhart |
Compact models for estimating microprocessor frequency and power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 313-318, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
VLSI, low-power, microprocessors, ASIC, power estimation, curve-fitting, delay modeling |
15 | Zhuo Gao, Ji Luo 0003, Hu Huang 0001, Wei Zhang, Joseph B. Bernstein |
Reliable Laser Programmable Gate Array Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 252-256, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Laser Programmable Gate Array (LPGA), Laser Field-Programmable Gate Array (LFPGA), MakeLink technology, laser-induced/laser programmable anti-fuse, digital ASIC design, low electrical resistance anti-fuse, Field-Programmable Gate Array (FPGA) |
15 | Nick Richardson, Lun Bin Huang, Razak Hossain, Tommy Zounes, Naresh Soni, Julian Lewis |
The iCOREtm 520 MHz synthesizable CPU core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 640-645, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
high-frequency, st20, cache, synthesis, pipeline, embedded, ASIC, branch-prediction, microarchitecture, CPU |
15 | Anton Chichkov, Dirk Merlier, Peter Cox |
Current Testing Procedure for Deep Submicron Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(3-4), pp. 219-224, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
ASIC testing, IDDQ, deep submicron |
15 | Farhad Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu |
DFT closure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 8-9, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
area requirement, power requirement, timing closure flow, logic testing, SoC, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, ASIC, testability |
15 | Holger Blume, Hans-Martin Blüthgen, Christiane Henning, Patrick Osterloh |
Integration of High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 66-, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
reconfigurable coprocessor board, multimedia, VLSI, DSP, digital signal processing, ASIC, CMOS |
15 | Hoda S. Abdel-Aty-Zohdy, Mahmoud Al-Nsour |
Digital Neural Processing Unit for Electronic Nose. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 236-237, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Neural Networks, Reinforcement Learning, ASIC, Digital Design, Electronic Nose |
15 | Dennis Sylvester, Kurt Keutzer |
Getting to the bottom of deep submicron. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1998, San Jose, CA, USA, November 8-12, 1998, pp. 203-211, 1998, ACM / IEEE Computer Society, 1-58113-008-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
ASIC, power dissipation, signal integrity, interconnect modeling, wirelength, gate delay, CMOS scaling |
15 | Yufeng Luo, Tjahjadi Wongsonegoro, Adnan Aziz |
Hybrid Techniques for Fast Functional Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 664-667, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
ASIC verification, simulation, emulation |
15 | Franco Fummi, Donatella Sciuto |
Implicit test pattern generation constrained to cellular automata embedding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 54-59, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
implicit test pattern generation, cellular automata embedding, test sequence identification, autonomous finite state machine, off-line self-testable circuit, BIST strategy, deterministic test sequences, MCNC benchmarks, controller, built-in self test, stuck-at faults, ASIC design, circuit under test |
15 | Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda |
Cellular automata for deterministic sequential test pattern generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 60-67, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
deterministic sequential test pattern generation, cellular automaton identification, hardware structure, area occupation, ASIC testing, evolutionary algorithm, cellular automata, BIST, fault coverage, stuck-at faults, FSM, deterministic automata |
15 | Man-Fai Yu, Joel Darnauer, Wayne Wei-Ming Dai |
Interchangeable pin routing with application to package layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 668-673, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
BGA, all-angle wiring, interchangeable pin routing, min-cost max-flow heuristic, multiple layers, octilinear wiring, package layout, pin redistribution, prerouted nets, rectilinear wiring, test fixture routing, triangulated routing network, CAD, NP-complete, ASIC, circuit layout CAD, speed, PGA, input output, routing problems |
15 | Karim Arabi, Bozena Kaminska |
Oscillation-test strategy for analog and mixed-signal integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 476-482, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
circuit oscillations, oscillation test strategy, analog ICs, low-cost test method, oscillation frequency deviation, wafer-probe testing, final production testing, ASIC testing, integrated circuit testing, operational amplifiers, analogue integrated circuits, mixed analogue-digital integrated circuits, production testing, analogue-digital conversion, mixed-signal ICs |
15 | Rong Zeng, Xiang-jun Dong, Mingfa Zhu |
Wormhole Routing and its Chip Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), June 12-14, 1996, Beijing, China, pp. 553-555, 1996, IEEE Computer Society, 0-8186-7460-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Dawning 1000, nWRC series, message passing, wormhole routing, router, ASIC design |
15 | Myung Hoon Sunwoo, Soohwan Ong, Byungdug Ahn, Kyungwoo Lee |
Design and Implementation of a Parallel Image Processor Chip for a SIMD Array Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 66-75, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
SIMD Array Processors, ASIC Chip, Image Processing, VLSI Design, VLSI Architectures |
15 | Peter C. Maxwell |
The use of IDDQ testing in low stuck-at coverage situations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 84-88, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
stuck-at coverage situations, quality goal, graded coverage, composite metric, fault diagnosis, logic testing, logic tests, integrated circuit testing, automatic testing, application specific integrated circuits, ASIC, CMOS logic circuits, IDDQ testing, IC testing |
15 | Ti-Yen Yen, Wayne H. Wolf |
Sensitivity-driven co-synthesis of distributed embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 4-9, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
application software architecture, communicating periodic processes, gradient-search algorithm, local sensitivity, priority prediction method, process allocation, real-time distributed embedded systems, sensitivity-driven co-synthesis, software engineering, real-time systems, distributed processing, logic design, ASICs, ASIC, processor scheduling, performance estimates, process scheduling, arbitrary topology, communication links, CPU time, heterogeneous distributed systems |
15 | Michael Harrington, Arun K. Somani |
Synchronizing Hypercube Networks in the Presence of Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(10), pp. 1175-1183, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
hypercube networks synchronisation, redundant results, fault tolerant hardware synchronization schemes, multistage synchronizers, Proteus parallel computer system, circuit switching communication network, reliability, fault tolerant computing, application specific integrated circuits, synchronisation, hypercube networks, distributed networks, phased locked loops, fault tolerant systems, Byzantine faults, synchronous programs, ASIC design |
15 | Ramesh Karri, Alex Orailoglu |
Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 29th Design Automation Conference, Anaheim, California, USA, June 8-12, 1992., pp. 662-665, 1992, IEEE Computer Society Press, 0-8186-2822-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP BibTeX RDF |
ASIC |
15 | Wonjong Kim, Joohack Lee, Hyunchul Shin |
A New Hierarchical Layout Compactor Using Simplified Graph Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 29th Design Automation Conference, Anaheim, California, USA, June 8-12, 1992., pp. 323-326, 1992, IEEE Computer Society Press, 0-8186-2822-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP BibTeX RDF |
ASIC |
15 | Wayne H. Wolf, Andrés Takach, Chun-Yao Huang, Richard Manno, Ephrem Wu |
The Princeton University Behavioral Synthesis System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 29th Design Automation Conference, Anaheim, California, USA, June 8-12, 1992., pp. 182-187, 1992, IEEE Computer Society Press, 0-8186-2822-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP BibTeX RDF |
ASIC |
15 | Liwu Li 0001, T. Anthony Marsland |
A parallel algorithm for finding a maximum flow in 0-1 networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Conference on Computer Science ![In: Proceedings of the 15th ACM Annual Conference on Computer Science, St. Louis, Missouri, USA, February 16-19, 1987, pp. 231-234, 1987, ACM, 0-89791-218-7. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
ASIC |
14 | Cai Li, Haochang Zhi, Kaiyue Yang, Junyi Qian, Zhihao Yan, Lixuan Zhu, Chao Chen, Xi Wang 0009, Weiwei Shan |
A 0.61-μW Fully Integrated Keyword-Spotting ASIC With Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(3), pp. 867-877, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | James Lin, Long Pham, Ran Tao, A. Gutmann, Shanglin Guo, Adam Cywar, Adam Spirer, Johan Mansson, Khiem Nguyen |
A Low-Power, Wide-Bandwidth, Three-Axis MEMS Accelerometer ASIC Using Beyond-Resonant-Frequency Sensing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(3), pp. 774-783, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Yannick M. Hopf, Djalma Simões dos Santos, Boudewine W. Ossenkoppele, Mehdi Soozande, Emile Noothout, Zu-Yao Chang, Chao Chen 0019, Hendrik J. Vos, Johan G. Bosch, Martin D. Verweij, Nico de Jong, Michiel A. P. Pertijs |
A Pitch-Matched High-Frame-Rate Ultrasound Imaging ASIC for Catheter-Based 3-D Probes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(2), pp. 476-491, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Jundong Feng, Junchao Wang, Yubin Zhu, Kaining Han |
A Hybrid Chaotic Encryption ASIC With Dynamic Precision for Internet of Things. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Internet Things J. ![In: IEEE Internet Things J. 11(1), pp. 1148-1163, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Adriaan Peetermans, Ingrid Verbauwhede |
Characterization of Oscillator Phase Noise Arising From Multiple Sources for ASIC True Random Number Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 71(3), pp. 1144-1157, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Asimina Koutra, Vasileios Tenentes |
Multi-Vt-Based Energy Efficiency Optimization for ASIC Designs of the Double Secure Hash Algorithm Toward a Sustainable Bitcoin Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 71(3), pp. 1596-1600, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Shoorangiz Bagherzadeh, Hassan Daryanavard, Mohammad R. Semati |
A novel multiplier-less convolution core for YOLO CNN ASIC implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Real Time Image Process. ![In: J. Real Time Image Process. 21(2), pp. 45, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Lucas Daudt Franck, Gabriel Augusto Ginja, João Paulo Carmo, José A. Afonso 0001, Maximiliam Luppe |
Custom ASIC Design for SHA-256 Using Open-Source Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. ![In: Comput. 13(1), pp. 9, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Alexander Frank, Bart Kootte, Thorsten Göttsche, Peter Jutte, Jean Schleipen, Paul Dijkstra, Eckardt Bihler, Joachim N. Burghartz, Jens Anders |
A 97-Channel Read-Out ASIC for an Electrophysiological Mapping Catheter With an Optical Link. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Biomed. Circuits Syst. ![In: IEEE Trans. Biomed. Circuits Syst. 18(1), pp. 76-88, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Emil Goh, Maoyang Xiang, I-Chyn Wey, Tee Hui Teo |
From English to ASIC: Hardware Implementation with Large Language Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2403.07039, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Daniel Fallnich, Christian Lanius, Shutao Zhang, Tobias Gemmeke |
Efficient ASIC Architecture for Low Latency Classic McEliece Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Trans. Cryptogr. Hardw. Embed. Syst. ![In: IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024(2), pp. 403-425, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
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