Search results for "ASIC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	Russell Tessier, Snigdha Jana	Incremental compilation for parallel logic verification systems.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
15	J. Bryan Lewis, Ivo Bolsens, Rudy Lauwereins, Chris Wheddon, Bhusan Gupta, Yankin Tanurhan	Reconfigurable SoC - What Will it Look Like?	DATE	2002	DBLP DOI BibTeX RDF
15	Sudhakar Yalamanchili	The Customization Landscape for Embedded Systems.	HiPC	2002	DBLP DOI BibTeX RDF
15	Helena Krupnova, Veronique Meurou, Christophe Barnichon, Carlos Serra, Farid Morsi	How Fast Is Rapid FPGA-based Prototyping: Lessons and Challenges from the Digital TV Design Prototyping Project.	FPL	2002	DBLP DOI BibTeX RDF
15	Sandeep Dhar, Dragan Maksimovic, Bruno Kranzen	Closed-loop adaptive voltage scaling controller for standard-cell ASICs.	ISLPED	2002	DBLP DOI BibTeX RDF	delay-line, variable-voltage, low-power, energy-efficient, design methodology, circuit design, standard-cell, DC-DC converter
15	Shih-Hsu Huang, Chu-Liao Wang	An effective floorplan-based power distribution network design methodology under reliability constraints.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
15	Sornavalli Ramanathan, Rituparna Mandal	Low Power Solution for Wireless Applications.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	2.5G, Multi-Vt, CMOS, 3G
15	Peter Hallschmid, Steven J. E. Wilton	Detailed routing architectures for embedded programmable logic IP cores.	FPGA	2001	DBLP DOI BibTeX RDF	FPGA, programmable logic, detailed routing, SoC design, embedded cores
15	Josef Schmid, Timo Schüring, Christoph Smalla	Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling Flow.	ISQED	2001	DBLP DOI BibTeX RDF
15	Sabyasachi Sengupta, Somavalli Ramanathan, Biswadeep Chatterjee, Dibyendu Goswami	Minimizing Area and Maximizing Porosity for Cell Layouts Using Innovative Routing Strategies.	VLSI Design	2001	DBLP DOI BibTeX RDF
15	Ioannis Andreadis	A Color Coordinate Normalizer Chip.	J. Intell. Robotic Syst.	2000	DBLP DOI BibTeX RDF	real-time imaging, pattern recognition, color
15	Shantanu Tarafdar, Miriam Leeser	A data-centric approach to high-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
15	Michael Reinhardt, Michael Santarini	What is Design Quality? How can Quality in Electronic Design be Quantified?	ISQED	2000	DBLP DOI BibTeX RDF
15	Luiz André Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, Ben Verghese	Piranha: a scalable architecture based on single-chip multiprocessing.	ISCA	2000	DBLP DOI BibTeX RDF
15	Adel Baganne, Jean Luc Philippe, Eric Martin 0001	A Co-Design Methodology for Telecommunication Systems: A Case Study of an Acoustic Echo Canceller.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
15	Jung Hyun Choi, Sergio Bampi	OTA Amplifiers Design on Digital Sea-of-Transistors Array.	DATE	1999	DBLP DOI BibTeX RDF
15	Jose Luis Nunez, Claudia Feregrino, Simon R. Jones, Stephen Bateman	The X-MatchLITE FPGA-Based Data Compressor.	EUROMICRO	1999	DBLP DOI BibTeX RDF
15	Romain Kamdem, Alain Fonkoua, Andre Zenatti	Hardware/Software Partitioning of Multirate System Using Static Scheduling Theory.	ICCD	1999	DBLP DOI BibTeX RDF	code-sign, scheduling, real time, Codesign, hardware/software partitioning, target architecture
15	Jens-Peter Kaps, Christof Paar	Fast DES Implementation for FPGAs and Its Application to a Universal Key-Search Machine.	Selected Areas in Cryptography	1998	DBLP DOI BibTeX RDF
15	Helena Krupnova, Vu DucAnh Dinh, Gabriele Saucier	A Knowledge-Based System for Prototyping on FPFAs.	FPL	1998	DBLP DOI BibTeX RDF
15	Tsuneo Ikedo, William L. Martens	Multimedia Processor Architecture.	ICMCS	1998	DBLP DOI BibTeX RDF
15	J. Patrick Brennan, Alvar Dean, Stephan Kenyon, Sebastian Ventrone	Low power methodology and design techniques for processor design.	ISLPED	1998	DBLP DOI BibTeX RDF
15	Marco Cavadini, Matthias Wosnitza, Markus Thaler, Gerhard Tröster	A Multiprocessor System for Real Time High Resolution Image Correlation.	ASAP	1997	DBLP DOI BibTeX RDF
15	Josef Fleischmann, Rolf Schlagenhaft, Martin Peller, Norbert Fröhlich	OLIVIA: Objectoriented Logicsimulation Implementing the VITAL Standard.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
15	Mani B. Srivastava, Anantha P. Chandrakasan, Robert W. Brodersen	Predictive system shutdown and other architectural techniques for energy efficient programmable computation.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
15	Mani B. Srivastava, Robert W. Brodersen	System level hardware module generation.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
15	Chun-Chao Yeh, Chun-Hsing Wu, Jie-Yong Juang	Design and implementation of a multicomputer interconnection network using FPGAs.	FCCM	1995	DBLP DOI BibTeX RDF
15	Yao-Wen Chang, Shashidhar Thakur, Kai Zhu 0001, D. F. Wong 0001	A new global routing algorithm for FPGAs.	ICCAD	1994	DBLP DOI BibTeX RDF
15	Jef L. van Meerbergen, Paul E. R. Lippens, B. T. McSweeney, Wim F. J. Verhaegh, Albert van der Werf, A. van Zanten	Architectural strategies for high-throughput applications.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
15	Alfred E. Dunlop	Will Cell Generation Displace Standard Cells?	DAC	1988	DBLP BibTeX RDF
15	Nan Hua, Eric Norige, Sailesh Kumar, Bill Lynch	Non-crypto Hardware Hash Functions for High Performance Networking ASICs.	ANCS	2011	DBLP DOI BibTeX RDF	Networking ASIC, Evaluation, Hash Function
15	B. K. Mishra 0001, Sandhya Save	Novel CAD Design Methodology for Two Stage Opamp with Noise-Power Balance.	ICSAP	2010	DBLP DOI BibTeX RDF	Analog circuit designs methodologies, Analog design automation, Op-amps, AMS, Simulated Annealing, CAD, SoC, ASIC, SPICE, EDA tools
15	Jihene Malek, Abderrahim Sebri, Souhir Mabrouk, Kholdoun Torki, Rached Tourki	Automated Breast Cancer Diagnosis Based on GVF-Snake Segmentation, Wavelet Features Extraction and Fuzzy Classification.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	The automatic diagnosis of breast cancer, GVF-Snake, Wavelet feature extraction, Segmentation, ASIC, Hardware implementation, Fuzzy classifiers
15	Pankaj Bhagawat, Rajballav Dash, Gwan S. Choi	Array like runtime reconfigurable MIMO detectors for 802.11n WLAN: a design case study.	ASP-DAC	2009	DBLP DOI BibTeX RDF	fixed sphere decoding (FSD) algorithm, on-the-fly reconfigurability, ASIC, MIMO systems, 802.11n
15	Miroslav Knezevic, Ingrid Verbauwhede	Hardware evaluation of the Luffa hash family.	WESS	2009	DBLP DOI BibTeX RDF	Luffa hash algorithm, SHA-3 competition, ASIC implementations
15	Bella Dubrov, Haggai Eran, Ari Freund 0001, Edward F. Mark, Shyam Ramji, Timothy A. Schell	Pin Assignment Using Stochastic Local Search Constraint Programming.	CP	2009	DBLP DOI BibTeX RDF	ASIC, Constraint Programming, EDA, Stochastic Local Search, Chip Design, Pin Assignment
15	Yang Sun 0001, Joseph R. Cavallaro	High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	mimo detection, VLSI architecture, ASIC design
15	Mahmoud Moadeli, Partha P. Maji, Wim Vanderbauwhede	Quarc: A High-Efficiency Network on-Chip Architecture.	AINA	2009	DBLP DOI BibTeX RDF	Quarc, Network On Chip, ASIC
15	Pachara V. Rao, Cyril Prasanna Raj, S. Ravi 0001	VLSI Design and Analysis of Multipliers for Low Power.	IIH-MSP	2009	DBLP DOI BibTeX RDF	Low Power, Delay, CMOS, Multipliers, Area, ASIC Implementation
15	Kevin Fan, Hyunchul Park 0001, Manjunath Kudlur, Scott A. Mahlke	Modulo scheduling for highly customized datapaths to increase hardware reusability.	CGO	2008	DBLP DOI BibTeX RDF	programmable asic, modulo scheduling, loop accelerator
15	Pil Woo Chun, Jamin Islam, Valeri Kirischian, Lev Kirischian	Improving Cost-Effectiveness Using a Micro-level Static Architecture for Stream Applications.	DELTA	2008	DBLP DOI BibTeX RDF	FPGA, ASIC, cost-effectiveness, run-time reconfiguration, stream application
15	Dai Yamamoto, Jun Yajima, Kouichi Itoh	A Very Compact Hardware Implementation of the MISTY1 Block Cipher.	CHES	2008	DBLP DOI BibTeX RDF	MISTY1, Compact Implementation, Block cipher, Hardware, ASIC
15	Florian Auernhammer, Patricia Sagmeister	Design optimization of a highly parallel InfiniBand host channel adapter.	ANCS	2008	DBLP DOI BibTeX RDF	HCA, host channel adapter, optimization, design, pipeline, ASIC, InfiniBand
15	Osman Musa Abdulkarim, Maitham Shams	A symmetric mos current-mode logic universal gate for high speed applications.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	MCML, SCL, VLSI, ASIC
15	Zhan Guo, Peter Nilsson 0001	A VLSI Architecture of the Square Root Algorithm for V-BLAST Detection.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	square root algorithm, VLSI, wireless LAN, ASIC, MIMO, fixed-point, 3G, HSDPA, CORDIC, BLAST
15	Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko	Yield enhancements of design-specific FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	design-specific FPGA, interconnect faults, interconnect utilization, yield enhancement, yield prediction, structured ASIC, FPGA interconnect
15	Steven Swanson, Andrew Putnam, Martha Mercaldi, Ken Michelson, Andrew Petersen 0001, Andrew Schwerin, Mark Oskin, Susan J. Eggers	Area-Performance Trade-offs in Tiled Dataflow Architectures.	ISCA	2006	DBLP DOI BibTeX RDF	WaveScalar, ASIC, RTL, Dataflow computing
15	David E. Taylor, Andreas Herkersdorf, Andreas C. Döring, Gero Dittmann	Robust header compression (ROHC) in next-generation network processors.	IEEE/ACM Trans. Netw.	2005	DBLP DOI BibTeX RDF	ROHC, hardware assist, FPGA, ASIC, network processor, ASIP, reconfigurable hardware, header compression
15	Rob Roy, Debashis Bhattacharya, Vamsi Boppana	Transistor-Level Optimization of Digital Designs with Flex Cells.	Computer	2005	DBLP DOI BibTeX RDF	ASIC design methodology, integrated circuit design, power optimization, design and test, high-performance design
15	Tsung-Han Tsai 0001, Ya-Chau Yang, Chun-Nan Liu	A Hardware/Software Co-Design of MP3 Audio Decoder.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	IMDCT, Filterbank, VLSI, DSP, ASIC, MPEG, Co-Design, MP3
15	Alexander B. Smirnov, Alexander Taubin, Ming Su, Mark G. Karpovsky	An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library.	ACSD	2005	DBLP DOI BibTeX RDF	asynchronous EDA, QDI, synthesis, ASIC, HDL
15	Alireza Hodjat, David Hwang 0001, Bo-Cheng Lai, Kris Tiri, Ingrid Verbauwhede	A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	crypto-processor, security, FPGA, VLSI, cryptography, advanced encryption standard (AES), ASIC, hardware architectures
15	Hamid Fadishei, Morteza Saheb Zamani, Masoud Sabaei	A novel reconfigurable hardware architecture for IP address lookup.	ANCS	2005	DBLP DOI BibTeX RDF	field-programmable gate array (FPGA), application specific integrated circuit (ASIC), hashing, reconfigurable hardware, longest prefix matching, IP address lookup
15	José Vieira do Vale Neto	Design sequence for a LC-tank voltage controlled oscillator in CMOS for RF.	SBCCI	2004	DBLP DOI BibTeX RDF	LC-tank, ASIC, CMOS, VCO, radio frequency
15	Victor V. Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno	Design methodology for semi custom processor cores.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	design, methodology, synthesis, microprocessor, ASIC, core
15	Nobuyuki Ohba, Kohji Takano	An SoC design methodology using FPGAs and embedded microprocessors.	DAC	2004	DBLP DOI BibTeX RDF	mixed-level verification, SoC, ASIC, FPGA prototyping
15	Changchun Shi, Robert W. Brodersen	Automated fixed-point data-type optimization tool for signal processing and communication systems.	DAC	2004	DBLP DOI BibTeX RDF	optimization, FPGA, digital signal processing, ASIC, communication systems, fixed-point arithmetic
15	Akashi Satoh, Kohji Takano	A Scalable Dual-Field Elliptic Curve Cryptographic Processor.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	high-speed hardware, Elliptic curve cryptography, public key cryptography, Montgomery multiplication, Galois field, ASIC implementation
15	Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen	Design theory and implementation for low-power segmented bus systems.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	OLA tree, bus graph model, bus segmentation, bus segmentation cell, low-power design flow, low-power design, ASIC design
15	Leon Stok, John M. Cohn	There is life left in ASICs.	ISPD	2003	DBLP DOI BibTeX RDF	design cost, ASIC, design tools
15	Binu K. Mathew, Al Davis, Zhen Fang 0002	A low-power accelerator for the SPHINX 3 speech recognition system.	CASES	2003	DBLP DOI BibTeX RDF	embedded systems, speech recognition, low power design, ASIC, special purpose hardware
15	Krishna Sekar, Kanishka Lahiri, Sujit Dey	Dynamic Platform Management for Configurable Platform-Based System-on-Chips.	ICCAD	2003	DBLP DOI BibTeX RDF	ASIC
15	Stephan Held, Bernhard Korte, Jens Maßberg, Matthias Ringe, Jens Vygen	Clock Scheduling and Clocktree Construction for High Performance ASICS.	ICCAD	2003	DBLP DOI BibTeX RDF	ASIC
15	Slavek Bulach, Anton Brauchle, Hans-Jörg Pfleiderer, Zdenek Kucerovsky	Design and Implementation of Discrete Event Control Systems: A Petri Net Based Hardware Approach.	Discret. Event Dyn. Syst.	2002	DBLP DOI BibTeX RDF	Petri nets, ASIC, DES, event-driven, programmable controller
15	Daniela De Venuto, Michael J. Ohletz, Bruno Riccò	Digital Window Comparator DfT Scheme for Mixed-Signal ICs.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	mixed-signal ASIC, window comparator, GO/NOGO test, signal level evaluation, DfT
15	H. Safiri, Majid Ahmadi, Graham A. Jullien, William C. Miller	A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic Programming.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	genetic algorithm, ASIC, digital filter, integer multiplication, common subexpressions
15	Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee	PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations.	CASES	2002	DBLP DOI BibTeX RDF	FPGA, low-power, compiler, SoC, synthesis, pipelining, VHDL, IP, ASIC, high-performance, FSM, Verilog, HDL, levelization
15	William C. Athas, Lynn Youngs, Andrew Reinhart	Compact models for estimating microprocessor frequency and power.	ISLPED	2002	DBLP DOI BibTeX RDF	VLSI, low-power, microprocessors, ASIC, power estimation, curve-fitting, delay modeling
15	Zhuo Gao, Ji Luo 0003, Hu Huang 0001, Wei Zhang, Joseph B. Bernstein	Reliable Laser Programmable Gate Array Technology.	ISQED	2002	DBLP DOI BibTeX RDF	Laser Programmable Gate Array (LPGA), Laser Field-Programmable Gate Array (LFPGA), MakeLink technology, laser-induced/laser programmable anti-fuse, digital ASIC design, low electrical resistance anti-fuse, Field-Programmable Gate Array (FPGA)
15	Nick Richardson, Lun Bin Huang, Razak Hossain, Tommy Zounes, Naresh Soni, Julian Lewis	The iCOREtm 520 MHz synthesizable CPU core.	DAC	2002	DBLP DOI BibTeX RDF	high-frequency, st20, cache, synthesis, pipeline, embedded, ASIC, branch-prediction, microarchitecture, CPU
15	Anton Chichkov, Dirk Merlier, Peter Cox	Current Testing Procedure for Deep Submicron Devices.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	ASIC testing, IDDQ, deep submicron
15	Farhad Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu	DFT closure.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	area requirement, power requirement, timing closure flow, logic testing, SoC, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, ASIC, testability
15	Holger Blume, Hans-Martin Blüthgen, Christiane Henning, Patrick Osterloh	Integration of High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality.	ASAP	2000	DBLP DOI BibTeX RDF	reconfigurable coprocessor board, multimedia, VLSI, DSP, digital signal processing, ASIC, CMOS
15	Hoda S. Abdel-Aty-Zohdy, Mahmoud Al-Nsour	Digital Neural Processing Unit for Electronic Nose.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	Neural Networks, Reinforcement Learning, ASIC, Digital Design, Electronic Nose
15	Dennis Sylvester, Kurt Keutzer	Getting to the bottom of deep submicron.	ICCAD	1998	DBLP DOI BibTeX RDF	ASIC, power dissipation, signal integrity, interconnect modeling, wirelength, gate delay, CMOS scaling
15	Yufeng Luo, Tjahjadi Wongsonegoro, Adnan Aziz	Hybrid Techniques for Fast Functional Simulation.	DAC	1998	DBLP DOI BibTeX RDF	ASIC verification, simulation, emulation
15	Franco Fummi, Donatella Sciuto	Implicit test pattern generation constrained to cellular automata embedding.	VTS	1997	DBLP DOI BibTeX RDF	implicit test pattern generation, cellular automata embedding, test sequence identification, autonomous finite state machine, off-line self-testable circuit, BIST strategy, deterministic test sequences, MCNC benchmarks, controller, built-in self test, stuck-at faults, ASIC design, circuit under test
15	Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda	Cellular automata for deterministic sequential test pattern generation.	VTS	1997	DBLP DOI BibTeX RDF	deterministic sequential test pattern generation, cellular automaton identification, hardware structure, area occupation, ASIC testing, evolutionary algorithm, cellular automata, BIST, fault coverage, stuck-at faults, FSM, deterministic automata
15	Man-Fai Yu, Joel Darnauer, Wayne Wei-Ming Dai	Interchangeable pin routing with application to package layout.	ICCAD	1996	DBLP DOI BibTeX RDF	BGA, all-angle wiring, interchangeable pin routing, min-cost max-flow heuristic, multiple layers, octilinear wiring, package layout, pin redistribution, prerouted nets, rectilinear wiring, test fixture routing, triangulated routing network, CAD, NP-complete, ASIC, circuit layout CAD, speed, PGA, input output, routing problems
15	Karim Arabi, Bozena Kaminska	Oscillation-test strategy for analog and mixed-signal integrated circuits.	VTS	1996	DBLP DOI BibTeX RDF	circuit oscillations, oscillation test strategy, analog ICs, low-cost test method, oscillation frequency deviation, wafer-probe testing, final production testing, ASIC testing, integrated circuit testing, operational amplifiers, analogue integrated circuits, mixed analogue-digital integrated circuits, production testing, analogue-digital conversion, mixed-signal ICs
15	Rong Zeng, Xiang-jun Dong, Mingfa Zhu	Wormhole Routing and its Chip Design.	ISPAN	1996	DBLP DOI BibTeX RDF	Dawning 1000, nWRC series, message passing, wormhole routing, router, ASIC design
15	Myung Hoon Sunwoo, Soohwan Ong, Byungdug Ahn, Kyungwoo Lee	Design and Implementation of a Parallel Image Processor Chip for a SIMD Array Processor.	ASAP	1995	DBLP DOI BibTeX RDF	SIMD Array Processors, ASIC Chip, Image Processing, VLSI Design, VLSI Architectures
15	Peter C. Maxwell	The use of IDDQ testing in low stuck-at coverage situations.	VTS	1995	DBLP DOI BibTeX RDF	stuck-at coverage situations, quality goal, graded coverage, composite metric, fault diagnosis, logic testing, logic tests, integrated circuit testing, automatic testing, application specific integrated circuits, ASIC, CMOS logic circuits, IDDQ testing, IC testing
15	Ti-Yen Yen, Wayne H. Wolf	Sensitivity-driven co-synthesis of distributed embedded systems.	ISSS	1995	DBLP DOI BibTeX RDF	application software architecture, communicating periodic processes, gradient-search algorithm, local sensitivity, priority prediction method, process allocation, real-time distributed embedded systems, sensitivity-driven co-synthesis, software engineering, real-time systems, distributed processing, logic design, ASICs, ASIC, processor scheduling, performance estimates, process scheduling, arbitrary topology, communication links, CPU time, heterogeneous distributed systems
15	Michael Harrington, Arun K. Somani	Synchronizing Hypercube Networks in the Presence of Faults.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	hypercube networks synchronisation, redundant results, fault tolerant hardware synchronization schemes, multistage synchronizers, Proteus parallel computer system, circuit switching communication network, reliability, fault tolerant computing, application specific integrated circuits, synchronisation, hypercube networks, distributed networks, phased locked loops, fault tolerant systems, Byzantine faults, synchronous programs, ASIC design
15	Ramesh Karri, Alex Orailoglu	Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs.	DAC	1992	DBLP BibTeX RDF	ASIC
15	Wonjong Kim, Joohack Lee, Hyunchul Shin	A New Hierarchical Layout Compactor Using Simplified Graph Models.	DAC	1992	DBLP BibTeX RDF	ASIC
15	Wayne H. Wolf, Andrés Takach, Chun-Yao Huang, Richard Manno, Ephrem Wu	The Princeton University Behavioral Synthesis System.	DAC	1992	DBLP BibTeX RDF	ASIC
15	Liwu Li 0001, T. Anthony Marsland	A parallel algorithm for finding a maximum flow in 0-1 networks.	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF	ASIC
14	Cai Li, Haochang Zhi, Kaiyue Yang, Junyi Qian, Zhihao Yan, Lixuan Zhu, Chao Chen, Xi Wang 0009, Weiwei Shan	A 0.61-μW Fully Integrated Keyword-Spotting ASIC With Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
14	James Lin, Long Pham, Ran Tao, A. Gutmann, Shanglin Guo, Adam Cywar, Adam Spirer, Johan Mansson, Khiem Nguyen	A Low-Power, Wide-Bandwidth, Three-Axis MEMS Accelerometer ASIC Using Beyond-Resonant-Frequency Sensing.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
14	Yannick M. Hopf, Djalma Simões dos Santos, Boudewine W. Ossenkoppele, Mehdi Soozande, Emile Noothout, Zu-Yao Chang, Chao Chen 0019, Hendrik J. Vos, Johan G. Bosch, Martin D. Verweij, Nico de Jong, Michiel A. P. Pertijs	A Pitch-Matched High-Frame-Rate Ultrasound Imaging ASIC for Catheter-Based 3-D Probes.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
14	Jundong Feng, Junchao Wang, Yubin Zhu, Kaining Han	A Hybrid Chaotic Encryption ASIC With Dynamic Precision for Internet of Things.	IEEE Internet Things J.	2024	DBLP DOI BibTeX RDF
14	Adriaan Peetermans, Ingrid Verbauwhede	Characterization of Oscillator Phase Noise Arising From Multiple Sources for ASIC True Random Number Generation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
14	Asimina Koutra, Vasileios Tenentes	Multi-Vt-Based Energy Efficiency Optimization for ASIC Designs of the Double Secure Hash Algorithm Toward a Sustainable Bitcoin Network.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
14	Shoorangiz Bagherzadeh, Hassan Daryanavard, Mohammad R. Semati	A novel multiplier-less convolution core for YOLO CNN ASIC implementation.	J. Real Time Image Process.	2024	DBLP DOI BibTeX RDF
14	Lucas Daudt Franck, Gabriel Augusto Ginja, João Paulo Carmo, José A. Afonso 0001, Maximiliam Luppe	Custom ASIC Design for SHA-256 Using Open-Source Tools.	Comput.	2024	DBLP DOI BibTeX RDF
14	Alexander Frank, Bart Kootte, Thorsten Göttsche, Peter Jutte, Jean Schleipen, Paul Dijkstra, Eckardt Bihler, Joachim N. Burghartz, Jens Anders	A 97-Channel Read-Out ASIC for an Electrophysiological Mapping Catheter With an Optical Link.	IEEE Trans. Biomed. Circuits Syst.	2024	DBLP DOI BibTeX RDF
14	Emil Goh, Maoyang Xiang, I-Chyn Wey, Tee Hui Teo	From English to ASIC: Hardware Implementation with Large Language Model.	CoRR	2024	DBLP DOI BibTeX RDF
14	Daniel Fallnich, Christian Lanius, Shutao Zhang, Tobias Gemmeke	Efficient ASIC Architecture for Low Latency Classic McEliece Decoding.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2024	DBLP DOI BibTeX RDF