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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2833 occurrences of 878 keywords
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Results
Found 2210 publication records. Showing 2210 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
29 | Shiyi Xu, Peter Waignjo, Percy G. Dias, Bole Shi |
Testability Prediction for Sequential Circuits Using Neural Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 48-, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
29 | Abhijit Chatterjee, Naveena Nagi |
Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 388-392, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
29 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 534-539, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
29 | Chunduri Rama Mohan, Partha Pratim Chakrabarti |
EARTH: combined state assignment of PLA-based FSM's targeting area and testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(7), pp. 727-731, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
29 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
A design for testability technique for RTL circuits using control/data flow extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 329-336, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
29 | Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal |
Improving Circuit Testability by Clock Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA, pp. 288-293, 1996, IEEE Computer Society, 0-8186-7502-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
29 | Shaahin Hessabi, Mohamed Y. Osman, Mohamed I. Elmasry |
Differential BiCMOS logic circuits: fault characterization and design-for-testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(3), pp. 437-445, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
29 | Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel |
Sequential circuit testability enhancement using a nonscan approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(2), pp. 333-338, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
29 | Miquel Roca 0001, Antonio Rubio 0001 |
Current testability analysis of feedback bridging faults in CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(10), pp. 1299-1305, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
29 | Vincenzo Piuri, Mariagiovanna Sami, Donatella Sciuto |
Testability of artificial neural networks: A behavioral approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(2), pp. 179-190, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
behavioral testing, neural error models, controllability, observability, feed-forward neural networks |
29 | Sujit Dey, Vijay Gangaram, Miodrag Potkonjak |
A controller-based design-for-testability technique for controller-data path circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 534-540, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
29 | Vivek Chickermane, Jaushin Lee, Janak H. Patel |
Addressing design for testability at the architectural level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(7), pp. 920-934, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
29 | Sujit Dey, Miodrag Potkonjak |
Non-scan design-for-testability of RT-level data paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 640-645, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
29 | Kaushik De, Prithviraj Banerjee |
PREST: a system for logic partitioning and resynthesis for testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(4), pp. 514-525, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
29 | Irith Pomeranz, Zvi Kohavi |
A limited exponential complexity algorithm for increasing the testability of digital circuits by testing-module insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(2), pp. 247-259, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
29 | William R. Simpson, John W. Sheppard |
System Testability Assessment for Integrated Diagnostics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 9(1), pp. 40-54, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
29 | Joachim Hartmann |
The Random Testability of the n-Input AND Gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STACS ![In: STACS 91, 8th Annual Symposium on Theoretical Aspects of Computer Science, Hamburg, Germany, February 14-16, 1991, Proceedings, pp. 488-498, 1991, Springer, 3-540-53709-0. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
29 | Noriyuki Ito |
Automatic Incorporation of On-Chip Testability Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 529-534, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
29 | T. Ghewala |
CrossCheck: A Cell Based VLSI Testability Solution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 706-709, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
29 | Larry Carter, Leendert M. Huisman, Tom W. Williams |
TRIM: testability range by ignoring the memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1), pp. 38-49, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
29 | Hans-Joachim Wunderlich |
PROTEST: a tool for probabilistic testability analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 204-211, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
27 | Tianmei Li 0001, Xiaosheng Si, Zonghao Yang, Hong Pei, Yuzhe Ma |
NHPP Testability Growth Model Considering Testability Growth Effort, Rectifying Delay, and Imperfect Correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 9072-9083, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
27 | Chia Yee Ooi, Hideo Fujiwara |
A New Design-for-Testability Method Based on Thru-Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 27(5), pp. 583-598, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
27 | Dong Xiang, Yi Xu |
Cost-Effective Non-Scan Design for Testability for Actual Testability Improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 19th International Conference on Computer Design (ICCD 2001), VLSI in Computers and Processors, 23-26 September 2001, Austin, TX, USA, Proceedings, pp. 154-160, 2001, IEEE Computer Society, 0-7695-1200-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Rachida Dssouli, Kamel Karoui, Kassem Saleh, Omar Cherkaoui |
Communications software design for testability: specification transformations and testability measures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Softw. Technol. ![In: Inf. Softw. Technol. 41(11-12), pp. 729-743, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Sandhya Seshadri, Michael S. Hsiao |
An integrated approach to behavioral-level design-for-testability using value-range and variable testability techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1999, Atlantic City, NJ, USA, 27-30 September 1999, pp. 858-867, 1999, IEEE Computer Society, 0-7803-5753-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Mohamed Jamoussi, Bozena Kaminska |
M-Testability: An Approach for Data-Path Testability Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDAC-ETC-EUROASIC ![In: EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France, pp. 449-455, 1994, IEEE Computer Society, 0-8186-5410-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
27 | Mohamed Jamoussi, Bozena Kaminska |
Data Path Testability Evaluation via Functional Testability Measures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994, pp. 301-306, 1994, IEEE Computer Society, 0-8186-4990-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
27 | Mohamed Jamoussi, Bozena Kaminska |
A Functional-level Testability Evaluation Using a New M-Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1993 IEEE International Symposium on Circuits and Systems, ISCAS 1993, Chicago, Illinois, USA, May 3-6, 1993, pp. 1611-1614, 1993, IEEE, 0-7803-1281-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
27 | M. Jamoussi, B. Kaminaka, D. Mukhedkar |
A New Variable Testability Measure: a Concept for Data-Flow Testability Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Fifth International Conference on VLSI Design, VLSI Design 1992, Bangalore, India, January 4-7, 1992, pp. 239-244, 1992, IEEE Computer Society, 0-8186-2465-5. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
27 | Colin Maunder |
Bargain for testability researchers: Tsui, F FLSI/VLSI testability design McGrawHill, New York, NY, USA (1987) £49.95 pp 702. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 11(9), pp. 519, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
27 | Ting-Hua Chen, Melvin A. Breuer |
Automatic Design for Testability Via Testability Measures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(1), pp. 3-11, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
26 | V. Loukusa |
Embedded System Level Self-Test for Mixed-Signal IO Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(4-6), pp. 463-470, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
IO connectivity, DFT, histogram, testability, self-test, mixed-signal, system level |
26 | Shiy Xu, E. Edirisuriya |
A New Way of Detecting Reconvergent Fanout Branch Pairs in Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 354-357, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Fanout branch, Reconvergence, Testability, Testable Design, Fanout |
26 | José M. Sempere, Pedro GarcÃa 0001 |
Learning Locally Testable Even Linear Languages from Positive Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICGI ![In: Grammatical Inference: Algorithms and Applications, 6th International Colloquium: ICGI 2002, Amsterdam, The Netherlands, September 23-25, 2002, Proceedings, pp. 225-236, 2002, Springer, 3-540-44239-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Learning from positive data, local testability, even linear languages |
26 | Shiyi Xu, Wei Cen |
Forecasting the efficiency of test generation algorithms for digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 179-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms |
26 | Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu |
Design of C-Testable Multipliers Based on the Modified Booth Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 42-47, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
modified Booth Algorithm, c-testable design, design for testability, multiplier, exhaustive testing, cell fault model |
26 | Wei Liang Huang, Fred J. Meyer, Fabrizio Lombardi |
Multiple fault detection in logic resources of FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 186-194, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
logic resources, AND tree, OR tree, CLB test generation, field programmable gate arrays, fault model, configurability, testability, programmability, multiple fault detection, SRAM-based FPGA |
26 | Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri |
On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 547-563, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model |
26 | Harry Hengster, Rolf Drechsler, Bernd Becker 0001, Stefan Eckrich, Tonja Pfeiffer |
AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 148-, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
EXOR based synthesis, synthesis for testability, delay optimization |
26 | Mou Hu |
Design of One-Vector Testable Binary Systems Based on Ternary Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 62-67, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
ternary circuits, MOS circuit, logic testing, built-in self-test, design for testability, multiple-valued logic |
26 | Arun Balakrishnan, Srimat T. Chakradhar |
Retiming with logic duplication transformation: theory and an application to partial scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 296-302, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
logic duplication transformation, partial scan application, RLD configurations, RLD transformation, testability metrics, scan flip-flops, sequential circuit design, linear programming, timing, integer programming, logic design, sequential circuits, logic CAD, polynomial time algorithm, integer linear program, flip-flops, retiming, integrated circuit design, circuit CAD, integrated logic circuits, objective function |
26 | Tong Liu 0007, Wei-Kang Huang, Fabrizio Lombardi |
Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995, pp. 125-131, 1995, ACM, 0-89791-743-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
constant testability, FPGA, testing, manufacturing |
26 | Debesh K. Das, Bhargab B. Bhattacharya |
Testable design of non-scan sequential circuits using extra logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 176-, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
nonscan sequential circuits, sequentially redundant faults, multiple stuck-at-fault model, augmented logic, performance evaluation, logic testing, redundancy, test generation, design for testability, logic design, sequential circuits, logic synthesis, synchronous sequential circuits, benchmark circuits, testable design |
26 | Bulent I. Dervisoglu |
Features of a Scan and Clock Resource chip for providing access to board-level test functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(1), pp. 107-115, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
diagnostics bus, design-for-testability, scan, boundary scan, pseudorandom testing |
26 | Arno Kunzmann, Hans-Joachim Wunderlich |
An analytical approach to the partial scan problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 1(2), pp. 163-174, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
partial scan path, sequential test generation, design for testability |
24 | Janusz Sosnowski, Lukasz Tupaj |
CPU Testability in Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Fifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010, Ho Chi Minh City, Vietnam, January 13-15, 2010, pp. 108-112, 2010, IEEE Computer Society, 978-0-7695-3978-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
CPU testing, embedded systems, testability, software-based-self-test |
24 | Alberto González-Sanchez 0002, Éric Piel, Hans-Gerhard Groß |
RiTMO: A Method for Runtime Testability Measurement and Optimisation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QSIC ![In: Proceedings of the Ninth International Conference on Quality Software, QSIC 2009, Jeju, Korea, August 24-25, 2009, pp. 377-382, 2009, IEEE Computer Society, 978-0-7695-3828-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
runtime testability, cig, runtime testing, optimization |
24 | Roberta Coelho, Uirá Kulesza, Arndt von Staa |
Improving architecture testability with patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OOPSLA Companion ![In: Companion to the 20th Annual ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications, OOPSLA 2005, October 16-20, 2005, San Diego, CA, USA, pp. 114-115, 2005, ACM, 1-59593-193-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
testability, architectural patterns, test patterns |
24 | Rolf Drechsler, Junhao Shi, Görschwin Fey |
MuTaTe: an efficient design for testability technique for multiplexor based circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 80-83, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
multiplexor based circuits, design for testability, logic synthesis, BDDs, decision diagrams |
24 | Robert M. Hierons, T.-H. Kim, Hasan Ural |
Expanding an Extended Finite State Machine to aid Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPSAC ![In: 26th International Computer Software and Applications Conference (COMPSAC 2002), Prolonging Software Life: Development and Redevelopment, 26-29 August 2002, Oxford, England, Proceedings, pp. 334-342, 2002, IEEE Computer Society, 0-7695-1727-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
testability, extended finite state machine, infeasible paths |
24 | Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja, Hideo Fujiwara |
Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 300-305, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Complete fault efficiency, Design for testability, Data path, Hierarchical test |
24 | Franco Fummi, Donatella Sciuto, Micaela Serra |
Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(12), pp. 1305-1323, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
sequential circuits, functional testing, Synthesis for testability, logic minimization, redundant faults, redundancies removal |
24 | Yves Le Traon, Daniel Deveaux, Jean-Marc Jézéquel |
Self-Testable Components: From Pragmatic Tests to Design-for-Testability Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TOOLS (29) ![In: TOOLS Europe 1999: 29th International Conference on Technology of Object-Oriented Languages and Systems, 7-10 June 1999, Nancy, France, pp. 96-107, 1999, IEEE Computer Society, 0-7695-0275-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
testing, design-for-testability, self-test, design by contract, reusable components |
24 | Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò |
Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(1), pp. 7-22, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
CMOS, testability, Bridging fault, self-checking circuits, checker |
24 | Wuudiann Ke, Premachandran R. Menon |
Multifault and delay-fault testability of multilevel circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(3), pp. 333-336, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
testing, testability, delay-faults, multiple stuck-at faults |
24 | VÃctor H. Champac, Joan Figueras |
Testability of floating gate defects in sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 202-207, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
floating gate defect testability, logic detectability conditions, defective transistors, logically untestable branches, scan path cell, CMOS latch cell, scan path flip-flops, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, simulated results, flip-flops, CMOS logic circuits, integrated circuit modelling, I/sub DDQ/ testing |
24 | Gueesang Lee, Mary Jane Irwin, Robert Michael Owens |
Polynomial Time Testability of Circuits Generated by Input Decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(2), pp. 201-210, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
input decomposition, logic synthesis tool, fault detection problem, complexity, logic testing, test generation, combinational circuits, logic CAD, testability, stuck-at fault, polynomial time, combinatorial circuits |
24 | Bernhard Eschermann |
Enhancing on-line testability during synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(1), pp. 105-116, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
BIST, synthesis for testability, control flow checking, controller synthesis |
24 | Sam M. Kim, Robert McNaughton, Robert McCloskey |
A Polynomial Time Algorithm for the Local Testability Problem of Deterministic Finite Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 40(10), pp. 1087-1093, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
local testability, locally testable language, nonnegative integer, prefix, suffix, computational complexity, polynomial time algorithm, formal languages, finite automata, word, deterministic finite automata, deterministic automata, substrings |
24 | Irith Pomeranz, Zvi Kohavi |
Polynomial Complexity Algorithms for Increasing the Testability of Digital Circuits by Testing Module Insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 40(11), pp. 1198-1214, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
polynomial complexity algorithms, testing-module insertion, test set merging, fanout free circuits, computational complexity, logic testing, partitioning, combinational circuits, logic CAD, testability, digital circuits, combinatorial circuits, single stuck-at faults, test generation algorithm, placement algorithm |
24 | Bjørg Reppen, Einar J. Aas |
Combined probabilistic testability calculation and compact test generation for PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(3), pp. 215-227, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
probabilistic testability, Fault coverage, test pattern generation, programmable logic arrays |
24 | Abhijit Chatterjee, Jacob A. Abraham |
The Testability of Generalized Counters Under Multiple Faulty Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(11), pp. 1378-1385, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
generalized counters, multiple faulty cells, counting circuits, logic testing, fault model, testability, adders, full adders |
24 | Jacob Savir, William H. McAnney |
Random Pattern Testability of Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(3), pp. 291-300, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
combinational logic networks, logic testing, delay faults, combinatorial circuits, latches, random pattern testability, system clocks |
24 | Saied Bozorgui-Nesbat, Edward J. McCluskey |
Lower Overhead Design for Testability of Programmable Logic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(4), pp. 379-383, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
test generation for PLA's, PLA testing, Design for testability, programmable logic arrays (PLA) |
24 | Jacob Savir |
Good Controllability and Observability Do Not Guarantee Good Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 32(12), pp. 1198-1200, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
Controllability, observability, random testing, testability, deterministic testing |
24 | Robert W. Priester, James B. Clary |
New Measures of Testability and Test Complexity for Linear Analog Failure Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 30(11), pp. 884-888, 1981. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
test point allocation, fault diagnosis experiment design, test complexity measure, testability measure, Automatic test program generation |
24 | George Markowsky |
Syndrome-Testability Can be Achieved by Circuit Modification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 30(8), pp. 604-606, 1981. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
syndrome testability, Circuit modification, stuck-at-faults |
24 | Chantal Robach, Gabriele Saucier, J. Lebrun |
Processor Testability and Design Consequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 25(6), pp. 645-652, 1976. The full citation details ...](Pics/full.jpeg) |
1976 |
DBLP DOI BibTeX RDF |
Hardcore, microdiagnosis, test microprograms, testability, processor design |
23 | Tali Kaufman, Madhu Sudan 0001 |
Algebraic property testing: the role of invariance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 40th Annual ACM Symposium on Theory of Computing, Victoria, British Columbia, Canada, May 17-20, 2008, pp. 403-412, 2008, ACM, 978-1-60558-047-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
error-correcting codes, locally testable codes, sublinear time algorithms |
23 | Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001 |
Low-Power and testable circuit synthesis using Shannon decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(4), pp. 47, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Shannon expansion, dynamic supply gating, test coverage, Design-for-test, IDDQ, noise immunity, test power |
23 | Görschwin Fey, Anna Bernasconi 0001, Valentina Ciriani, Rolf Drechsler |
On the Construction of Small Fully Testable Circuits with Low Depth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 563-569, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz |
Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 79-82, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Varun Arora, Indranil Sengupta 0001 |
A Unified Approach to Partial Scan Design using Genetic Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 414-421, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Julian P. Murphy, Alexandre V. Bystrov, Alexandre Yakovlev |
Power-Balanced Self Checking Circuits for Cryptographic Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 157-162, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis |
Test Generation Methodology for High-Speed Floating Point Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 227-232, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Abdil Rashid Mohamed, Zebo Peng, Petru Eles |
A Heuristic for Wiring-Aware Built-In Self-Test Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France, pp. 408-415, 2004, IEEE Computer Society, 0-7695-2203-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
BIST insertion, wiring area, test synthesis |
23 | Laurence Tianruo Yang, Jon C. Muzio |
Testing Methodologies for Embedded Systems and Systems-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, First International Conference, ICESS 2004, Hangzhou, China, December 9-10, 2004, Revised Selected Papers, pp. 15-24, 2004, Springer, 3-540-28128-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Sunwoong Yang, MoonJoon Kim, JaeHeung Park, Hoon Chang |
A Study on Methodology for Enhancing Reliability of Datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (1) ![In: Computational Science and Its Applications - ICCSA 2004, International Conference, Assisi, Italy, May 14-17, 2004, Proceedings, Part I, pp. 73-80, 2004, Springer, 3-540-22054-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Matthew L. King, Kewal K. Saluja |
Testing Micropipelined Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 329-338, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Haibo Wang 0005, Suchitra Kulkarni, Spyros Tragoudas |
On-line Testing Field Programmable Analog Array Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1340-1348, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Eli Ben-Sasson, Madhu Sudan 0001 |
Robust Locally Testable Codes and Products of Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPROX-RANDOM ![In: Approximation, Randomization, and Combinatorial Optimization, Algorithms and Techniques, 7th International Workshop on Approximation Algorithms for Combinatorial Optimization Problems, APPROX 2004, and 8th International Workshop on Randomization and Computation, RANDOM 2004, Cambridge, MA, USA, August 22-24, 2004, Proceedings, pp. 286-297, 2004, Springer, 3-540-22894-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada |
Practical Fault Coverage of Supply Current Tests for Bipolar ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 2nd IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2004), 28-30 January 2004, Perth, Australia, pp. 189-194, 2004, IEEE Computer Society, 0-7695-2081-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Jin-Fu Li 0001, Cheng-Wen Wu |
Efficient FFT network testing and diagnosis schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(3), pp. 267-278, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
23 | M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor |
Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 138-147, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
compact test sets, ATPG, fault coverage, stuck-at faults, test length, Test point insertion, gate-delay faults |
23 | Xiaowei Li 0001, Paul Y. S. Cheung |
Data Path Synthesis for BIST with Low Area Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 275-278, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell |
A Complete Characterization of Path Delay Faults through Stuck-at Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 492-497, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Alex Orailoglu |
Microarchitectural synthesis for rapid BIST testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(6), pp. 573-586, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
23 | Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik |
A Hybrid Algorithm for Test Point Selection for Scan-Based BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 478-483, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
23 | William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
Delay fault coverage, test set size, and performance trade-offs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(1), pp. 32-44, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
23 | Nai-Chi Lee |
A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(4), pp. 361-368, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
23 | Srinivas Devadas, Kurt Keutzer |
Synthesis of robust delay-fault-testable circuits: theory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(1), pp. 87-101, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
23 | Frans P. M. Beenker, Barry J. Dekker, Richard Stans, Max van der Star |
Implementing Macro Test in Silicon Compiler Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 7(2), pp. 41-51, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
23 | Kurt Keutzer, Sharad Malik, Alexander Saldanha |
Is Redundancy Necessary to Reduce Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 228-234, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
23 | Srinivas Devadas, Kurt Keutzer |
Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 221-227, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
23 | Micaela Serra, Jon C. Muzio |
Space compaction for multiple-output circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(10), pp. 1105-1113, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
23 | Wei-Kang Huang, Fabrizio Lombardi |
On an improved design approach for C-testable orthogonal iterative arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(5), pp. 609-615, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
22 | Muhammad Nummer, Manoj Sachdev |
DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10212-10217, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
high-performance testing, design for testability, Delay-fault testing, design for delay testability |
22 | Tomokazu Yoneda, Hideo Fujiwara |
Design for Consecutive Transparency of Cores in System-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 287-292, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
consecutive transparency, design for testability, system-on a chip, register transfer level, test access mechanism, consecutive testability |
22 | Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi |
False-Path Removal Using Delay Fault Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(5), pp. 463-476, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
design for testability, fault simulation, Delay testing, path delay faults, synthesis for testability, redundancy removal |
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