Search results for "Testability"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
29	Shiyi Xu, Peter Waignjo, Percy G. Dias, Bole Shi	Testability Prediction for Sequential Circuits Using Neural Network.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF
29	Abhijit Chatterjee, Naveena Nagi	Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial.	VLSI Design	1997	DBLP DOI BibTeX RDF
29	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs.	DAC	1997	DBLP DOI BibTeX RDF
29	Chunduri Rama Mohan, Partha Pratim Chakrabarti	EARTH: combined state assignment of PLA-based FSM's targeting area and testability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
29	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	A design for testability technique for RTL circuits using control/data flow extraction.	ICCAD	1996	DBLP DOI BibTeX RDF
29	Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal	Improving Circuit Testability by Clock Control.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
29	Shaahin Hessabi, Mohamed Y. Osman, Mohamed I. Elmasry	Differential BiCMOS logic circuits: fault characterization and design-for-testability.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
29	Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel	Sequential circuit testability enhancement using a nonscan approach.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
29	Miquel Roca 0001, Antonio Rubio 0001	Current testability analysis of feedback bridging faults in CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
29	Vincenzo Piuri, Mariagiovanna Sami, Donatella Sciuto	Testability of artificial neural networks: A behavioral approach.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	behavioral testing, neural error models, controllability, observability, feed-forward neural networks
29	Sujit Dey, Vijay Gangaram, Miodrag Potkonjak	A controller-based design-for-testability technique for controller-data path circuits.	ICCAD	1995	DBLP DOI BibTeX RDF
29	Vivek Chickermane, Jaushin Lee, Janak H. Patel	Addressing design for testability at the architectural level.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
29	Sujit Dey, Miodrag Potkonjak	Non-scan design-for-testability of RT-level data paths.	ICCAD	1994	DBLP DOI BibTeX RDF
29	Kaushik De, Prithviraj Banerjee	PREST: a system for logic partitioning and resynthesis for testability.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
29	Irith Pomeranz, Zvi Kohavi	A limited exponential complexity algorithm for increasing the testability of digital circuits by testing-module insertion.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
29	William R. Simpson, John W. Sheppard	System Testability Assessment for Integrated Diagnostics.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
29	Joachim Hartmann	The Random Testability of the n-Input AND Gate.	STACS	1991	DBLP DOI BibTeX RDF
29	Noriyuki Ito	Automatic Incorporation of On-Chip Testability Circuits.	DAC	1990	DBLP DOI BibTeX RDF
29	T. Ghewala	CrossCheck: A Cell Based VLSI Testability Solution.	DAC	1989	DBLP DOI BibTeX RDF
29	Larry Carter, Leendert M. Huisman, Tom W. Williams	TRIM: testability range by ignoring the memory.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
29	Hans-Joachim Wunderlich	PROTEST: a tool for probabilistic testability analysis.	DAC	1985	DBLP DOI BibTeX RDF
27	Tianmei Li 0001, Xiaosheng Si, Zonghao Yang, Hong Pei, Yuzhe Ma	NHPP Testability Growth Model Considering Testability Growth Effort, Rectifying Delay, and Imperfect Correction.	IEEE Access	2020	DBLP DOI BibTeX RDF
27	Chia Yee Ooi, Hideo Fujiwara	A New Design-for-Testability Method Based on Thru-Testability.	J. Electron. Test.	2011	DBLP DOI BibTeX RDF
27	Dong Xiang, Yi Xu	Cost-Effective Non-Scan Design for Testability for Actual Testability Improvement.	ICCD	2001	DBLP DOI BibTeX RDF
27	Rachida Dssouli, Kamel Karoui, Kassem Saleh, Omar Cherkaoui	Communications software design for testability: specification transformations and testability measures.	Inf. Softw. Technol.	1999	DBLP DOI BibTeX RDF
27	Sandhya Seshadri, Michael S. Hsiao	An integrated approach to behavioral-level design-for-testability using value-range and variable testability techniques.	ITC	1999	DBLP DOI BibTeX RDF
27	Mohamed Jamoussi, Bozena Kaminska	M-Testability: An Approach for Data-Path Testability Evaluation.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
27	Mohamed Jamoussi, Bozena Kaminska	Data Path Testability Evaluation via Functional Testability Measures.	VLSI Design	1994	DBLP DOI BibTeX RDF
27	Mohamed Jamoussi, Bozena Kaminska	A Functional-level Testability Evaluation Using a New M-Testability.	ISCAS	1993	DBLP BibTeX RDF
27	M. Jamoussi, B. Kaminaka, D. Mukhedkar	A New Variable Testability Measure: a Concept for Data-Flow Testability Evaluation.	VLSI Design	1992	DBLP DOI BibTeX RDF
27	Colin Maunder	Bargain for testability researchers: Tsui, F FLSI/VLSI testability design McGrawHill, New York, NY, USA (1987) £49.95 pp 702.	Microprocess. Microsystems	1987	DBLP DOI BibTeX RDF
27	Ting-Hua Chen, Melvin A. Breuer	Automatic Design for Testability Via Testability Measures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1985	DBLP DOI BibTeX RDF
26	V. Loukusa	Embedded System Level Self-Test for Mixed-Signal IO Verification.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	IO connectivity, DFT, histogram, testability, self-test, mixed-signal, system level
26	Shiy Xu, E. Edirisuriya	A New Way of Detecting Reconvergent Fanout Branch Pairs in Logic Circuits.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF	Fanout branch, Reconvergence, Testability, Testable Design, Fanout
26	José M. Sempere, Pedro García 0001	Learning Locally Testable Even Linear Languages from Positive Data.	ICGI	2002	DBLP DOI BibTeX RDF	Learning from positive data, local testability, even linear languages
26	Shiyi Xu, Wei Cen	Forecasting the efficiency of test generation algorithms for digital circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms
26	Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu	Design of C-Testable Multipliers Based on the Modified Booth Algorithm.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	modified Booth Algorithm, c-testable design, design for testability, multiplier, exhaustive testing, cell fault model
26	Wei Liang Huang, Fred J. Meyer, Fabrizio Lombardi	Multiple fault detection in logic resources of FPGAs.	DFT	1997	DBLP DOI BibTeX RDF	logic resources, AND tree, OR tree, CLB test generation, field programmable gate arrays, fault model, configurability, testability, programmability, multiple fault detection, SRAM-based FPGA
26	Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri	On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers.	VLSI Design	1997	DBLP DOI BibTeX RDF	fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model
26	Harry Hengster, Rolf Drechsler, Bernd Becker 0001, Stefan Eckrich, Tonja Pfeiffer	AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	EXOR based synthesis, synthesis for testability, delay optimization
26	Mou Hu	Design of One-Vector Testable Binary Systems Based on Ternary Logic.	ISMVL	1996	DBLP DOI BibTeX RDF	ternary circuits, MOS circuit, logic testing, built-in self-test, design for testability, multiple-valued logic
26	Arun Balakrishnan, Srimat T. Chakradhar	Retiming with logic duplication transformation: theory and an application to partial scan.	VLSI Design	1996	DBLP DOI BibTeX RDF	logic duplication transformation, partial scan application, RLD configurations, RLD transformation, testability metrics, scan flip-flops, sequential circuit design, linear programming, timing, integer programming, logic design, sequential circuits, logic CAD, polynomial time algorithm, integer linear program, flip-flops, retiming, integrated circuit design, circuit CAD, integrated logic circuits, objective function
26	Tong Liu 0007, Wei-Kang Huang, Fabrizio Lombardi	Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays.	FPGA	1995	DBLP DOI BibTeX RDF	constant testability, FPGA, testing, manufacturing
26	Debesh K. Das, Bhargab B. Bhattacharya	Testable design of non-scan sequential circuits using extra logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	nonscan sequential circuits, sequentially redundant faults, multiple stuck-at-fault model, augmented logic, performance evaluation, logic testing, redundancy, test generation, design for testability, logic design, sequential circuits, logic synthesis, synchronous sequential circuits, benchmark circuits, testable design
26	Bulent I. Dervisoglu	Features of a Scan and Clock Resource chip for providing access to board-level test functions.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	diagnostics bus, design-for-testability, scan, boundary scan, pseudorandom testing
26	Arno Kunzmann, Hans-Joachim Wunderlich	An analytical approach to the partial scan problem.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	partial scan path, sequential test generation, design for testability
24	Janusz Sosnowski, Lukasz Tupaj	CPU Testability in Embedded Systems.	DELTA	2010	DBLP DOI BibTeX RDF	CPU testing, embedded systems, testability, software-based-self-test
24	Alberto González-Sanchez 0002, Éric Piel, Hans-Gerhard Groß	RiTMO: A Method for Runtime Testability Measurement and Optimisation.	QSIC	2009	DBLP DOI BibTeX RDF	runtime testability, cig, runtime testing, optimization
24	Roberta Coelho, Uirá Kulesza, Arndt von Staa	Improving architecture testability with patterns.	OOPSLA Companion	2005	DBLP DOI BibTeX RDF	testability, architectural patterns, test patterns
24	Rolf Drechsler, Junhao Shi, Görschwin Fey	MuTaTe: an efficient design for testability technique for multiplexor based circuits.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	multiplexor based circuits, design for testability, logic synthesis, BDDs, decision diagrams
24	Robert M. Hierons, T.-H. Kim, Hasan Ural	Expanding an Extended Finite State Machine to aid Testability.	COMPSAC	2002	DBLP DOI BibTeX RDF	testability, extended finite state machine, infeasible paths
24	Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja, Hideo Fujiwara	Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency.	VLSI Design	2000	DBLP DOI BibTeX RDF	Complete fault efficiency, Design for testability, Data path, Hierarchical test
24	Franco Fummi, Donatella Sciuto, Micaela Serra	Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	sequential circuits, functional testing, Synthesis for testability, logic minimization, redundant faults, redundancies removal
24	Yves Le Traon, Daniel Deveaux, Jean-Marc Jézéquel	Self-Testable Components: From Pragmatic Tests to Design-for-Testability Methodology.	TOOLS (29)	1999	DBLP DOI BibTeX RDF	testing, design-for-testability, self-test, design by contract, reusable components
24	Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò	Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	CMOS, testability, Bridging fault, self-checking circuits, checker
24	Wuudiann Ke, Premachandran R. Menon	Multifault and delay-fault testability of multilevel circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	testing, testability, delay-faults, multiple stuck-at faults
24	Víctor H. Champac, Joan Figueras	Testability of floating gate defects in sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	floating gate defect testability, logic detectability conditions, defective transistors, logically untestable branches, scan path cell, CMOS latch cell, scan path flip-flops, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, simulated results, flip-flops, CMOS logic circuits, integrated circuit modelling, I/sub DDQ/ testing
24	Gueesang Lee, Mary Jane Irwin, Robert Michael Owens	Polynomial Time Testability of Circuits Generated by Input Decomposition.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	input decomposition, logic synthesis tool, fault detection problem, complexity, logic testing, test generation, combinational circuits, logic CAD, testability, stuck-at fault, polynomial time, combinatorial circuits
24	Bernhard Eschermann	Enhancing on-line testability during synthesis.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	BIST, synthesis for testability, control flow checking, controller synthesis
24	Sam M. Kim, Robert McNaughton, Robert McCloskey	A Polynomial Time Algorithm for the Local Testability Problem of Deterministic Finite Automata.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	local testability, locally testable language, nonnegative integer, prefix, suffix, computational complexity, polynomial time algorithm, formal languages, finite automata, word, deterministic finite automata, deterministic automata, substrings
24	Irith Pomeranz, Zvi Kohavi	Polynomial Complexity Algorithms for Increasing the Testability of Digital Circuits by Testing Module Insertion.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	polynomial complexity algorithms, testing-module insertion, test set merging, fanout free circuits, computational complexity, logic testing, partitioning, combinational circuits, logic CAD, testability, digital circuits, combinatorial circuits, single stuck-at faults, test generation algorithm, placement algorithm
24	Bjørg Reppen, Einar J. Aas	Combined probabilistic testability calculation and compact test generation for PLAs.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	probabilistic testability, Fault coverage, test pattern generation, programmable logic arrays
24	Abhijit Chatterjee, Jacob A. Abraham	The Testability of Generalized Counters Under Multiple Faulty Cells.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	generalized counters, multiple faulty cells, counting circuits, logic testing, fault model, testability, adders, full adders
24	Jacob Savir, William H. McAnney	Random Pattern Testability of Delay Faults.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	combinational logic networks, logic testing, delay faults, combinatorial circuits, latches, random pattern testability, system clocks
24	Saied Bozorgui-Nesbat, Edward J. McCluskey	Lower Overhead Design for Testability of Programmable Logic Arrays.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	test generation for PLA's, PLA testing, Design for testability, programmable logic arrays (PLA)
24	Jacob Savir	Good Controllability and Observability Do Not Guarantee Good Testability.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	Controllability, observability, random testing, testability, deterministic testing
24	Robert W. Priester, James B. Clary	New Measures of Testability and Test Complexity for Linear Analog Failure Analysis.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	test point allocation, fault diagnosis experiment design, test complexity measure, testability measure, Automatic test program generation
24	George Markowsky	Syndrome-Testability Can be Achieved by Circuit Modification.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	syndrome testability, Circuit modification, stuck-at-faults
24	Chantal Robach, Gabriele Saucier, J. Lebrun	Processor Testability and Design Consequences.	IEEE Trans. Computers	1976	DBLP DOI BibTeX RDF	Hardcore, microdiagnosis, test microprograms, testability, processor design
23	Tali Kaufman, Madhu Sudan 0001	Algebraic property testing: the role of invariance.	STOC	2008	DBLP DOI BibTeX RDF	error-correcting codes, locally testable codes, sublinear time algorithms
23	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001	Low-Power and testable circuit synthesis using Shannon decomposition.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Shannon expansion, dynamic supply gating, test coverage, Design-for-test, IDDQ, noise immunity, test power
23	Görschwin Fey, Anna Bernasconi 0001, Valentina Ciriani, Rolf Drechsler	On the Construction of Small Fully Testable Circuits with Low Depth.	DSD	2007	DBLP DOI BibTeX RDF
23	Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz	Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs.	DSD	2005	DBLP DOI BibTeX RDF
23	Varun Arora, Indranil Sengupta 0001	A Unified Approach to Partial Scan Design using Genetic Algorithm.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
23	Julian P. Murphy, Alexandre V. Bystrov, Alexandre Yakovlev	Power-Balanced Self Checking Circuits for Cryptographic Chips.	IOLTS	2005	DBLP DOI BibTeX RDF
23	George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Test Generation Methodology for High-Speed Floating Point Adders.	IOLTS	2005	DBLP DOI BibTeX RDF
23	Abdil Rashid Mohamed, Zebo Peng, Petru Eles	A Heuristic for Wiring-Aware Built-In Self-Test Synthesis.	DSD	2004	DBLP DOI BibTeX RDF	BIST insertion, wiring area, test synthesis
23	Laurence Tianruo Yang, Jon C. Muzio	Testing Methodologies for Embedded Systems and Systems-on-Chip.	ICESS	2004	DBLP DOI BibTeX RDF
23	Sunwoong Yang, MoonJoon Kim, JaeHeung Park, Hoon Chang	A Study on Methodology for Enhancing Reliability of Datapath.	ICCSA (1)	2004	DBLP DOI BibTeX RDF
23	Matthew L. King, Kewal K. Saluja	Testing Micropipelined Asynchronous Circuits.	ITC	2004	DBLP DOI BibTeX RDF
23	Haibo Wang 0005, Suchitra Kulkarni, Spyros Tragoudas	On-line Testing Field Programmable Analog Array Circuits.	ITC	2004	DBLP DOI BibTeX RDF
23	Eli Ben-Sasson, Madhu Sudan 0001	Robust Locally Testable Codes and Products of Codes.	APPROX-RANDOM	2004	DBLP DOI BibTeX RDF
23	Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada	Practical Fault Coverage of Supply Current Tests for Bipolar ICs.	DELTA	2004	DBLP DOI BibTeX RDF
23	Jin-Fu Li 0001, Cheng-Wen Wu	Efficient FFT network testing and diagnosis schemes.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
23	M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor	Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume.	ITC	2002	DBLP DOI BibTeX RDF	compact test sets, ATPG, fault coverage, stuck-at faults, test length, Test point insertion, gate-delay faults
23	Xiaowei Li 0001, Paul Y. S. Cheung	Data Path Synthesis for BIST with Low Area Overhead.	ASP-DAC	1999	DBLP DOI BibTeX RDF
23	Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell	A Complete Characterization of Path Delay Faults through Stuck-at Faults.	VLSI Design	1999	DBLP DOI BibTeX RDF
23	Alex Orailoglu	Microarchitectural synthesis for rapid BIST testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
23	Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik	A Hybrid Algorithm for Test Point Selection for Scan-Based BIST.	DAC	1997	DBLP DOI BibTeX RDF
23	William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Delay fault coverage, test set size, and performance trade-offs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
23	Nai-Chi Lee	A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF
23	Srinivas Devadas, Kurt Keutzer	Synthesis of robust delay-fault-testable circuits: theory.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
23	Frans P. M. Beenker, Barry J. Dekker, Richard Stans, Max van der Star	Implementing Macro Test in Silicon Compiler Design.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
23	Kurt Keutzer, Sharad Malik, Alexander Saldanha	Is Redundancy Necessary to Reduce Delay.	DAC	1990	DBLP DOI BibTeX RDF
23	Srinivas Devadas, Kurt Keutzer	Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits.	DAC	1990	DBLP DOI BibTeX RDF
23	Micaela Serra, Jon C. Muzio	Space compaction for multiple-output circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
23	Wei-Kang Huang, Fabrizio Lombardi	On an improved design approach for C-testable orthogonal iterative arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
22	Muhammad Nummer, Manoj Sachdev	DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers.	DATE	2003	DBLP DOI BibTeX RDF	high-performance testing, design for testability, Delay-fault testing, design for delay testability
22	Tomokazu Yoneda, Hideo Fujiwara	Design for Consecutive Transparency of Cores in System-on-a-Chip.	VTS	2003	DBLP DOI BibTeX RDF	consecutive transparency, design for testability, system-on a chip, register transfer level, test access mechanism, consecutive testability
22	Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi	False-Path Removal Using Delay Fault Simulation.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	design for testability, fault simulation, Delay testing, path delay faults, synthesis for testability, redundancy removal