Search results for "transistor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Kwan-Do Kim, Young-Kwan Park, Jun-Ha Lee, Jeong-Taek Kong, Hee-Sung Kang, Young-Wug Kim, Seok-Jin Kim	Three Dimensional Analysis of Thermal Degradation Effects in FDSOI MOSFET's.	ISQED	2000	DBLP DOI BibTeX RDF	FDSOI, self-heating, finger type, bar type
18	Valery Axelrad, Nicolas B. Cobb, M. O'Brien, Thuy Do, Tom Donnelly, Yuri Granik, Emile Y. Sahouria, Victor Boksha, Artur Balasinski	Efficient Full-Chip Yield Analysis Methodology for OPC-Corrected VLSI Designs.	ISQED	2000	DBLP DOI BibTeX RDF
18	R. Shalem, Lizy Kurian John, Eugene John	A Novel Low Power Energy Recovery Full Adder Cell.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
18	Muhammad M. Khellah, Mohamed I. Elmasry	Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	low-power design, power estimation, high-level design
18	James T. Kao, Siva G. Narendra, Anantha P. Chandrakasan	MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
18	Daniel G. Saab, Youssef Saab, Jacob A. Abraham	Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
18	Uming Ko, T. Balsara, Wai Lee	Low-power design techniques for high-performance CMOS adders.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
18	Brian S. Cherkauer, Eby G. Friedman	Channel width tapering of serially connected MOSFET's with emphasis on power dissipation.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
18	Raffaele Costa, Francesco Curatelli, Daniele D. Caviglia, Giacomo M. Bisio	Symbolic generation of constrained random logic cells.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
18	H. Y. Chen, Sung-Mo Kang	A new circuit optimization technique for high performance CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
18	Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu	LiB: a CMOS cell compiler.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
18	Kye S. Hedlund	Electrical optimization of PLAs.	DAC	1985	DBLP DOI BibTeX RDF
18	Mahsa Tahermaram, Mahdi Vadizadeh, A. Eslamzadeh, Morteza Fathipour	Employing work function enginnering and asymmetric gate oxide in nano-scale source-heterojunction-MOS-transistor.	EIT	2009	DBLP DOI BibTeX RDF
18	He Peng, Chung-Kuan Cheng	Parallel transistor level circuit simulation using domain decomposition methods.	ASP-DAC	2009	DBLP DOI BibTeX RDF
18	Bao Liu 0001	Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture.	ASP-DAC	2009	DBLP DOI BibTeX RDF
18	Tamkeen M. Bhatti, F. A. Bhatti	Charged based MOS transistor modeling in weak inversion.	EIT	2008	DBLP DOI BibTeX RDF
18	Brian Cline, Kaviraj Chopra, David T. Blaauw, Andres Torres, Savithri Sundareswaran	Transistor-Specific Delay Modeling for SSTA.	DATE	2008	DBLP DOI BibTeX RDF
18	Petru Bogdan Bacinschi, Tudor Murgan, Klaus Koch, Manfred Glesner	An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs.	DATE	2008	DBLP DOI BibTeX RDF
18	Nikil D. Dutt	Quo vadis, BTSoC (Billion Transistor SoC)?	ASP-DAC	2008	DBLP DOI BibTeX RDF
18	Weiqing Guo, Yu Zhong, Tom Burd	Context-sensitive static transistor-level IR analysis.	ICCAD	2008	DBLP DOI BibTeX RDF
18	Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim	Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
18	Zeljko Ignjatovic, Yang Zhang, Mark F. Bocko	CMOS image sensor readout employing in-pixel transistor current sensing.	ISCAS	2008	DBLP DOI BibTeX RDF
18	Jordan D. Gray, Srinivasan Venkatesh 0003, Ryan W. Robucci, Paul E. Hasler	A floating-gate transistor based continuous-time analog adaptive filter.	ISCAS	2008	DBLP DOI BibTeX RDF
18	Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen	Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction.	ISCAS	2008	DBLP DOI BibTeX RDF
18	Saurabh Sinha, Asha Balijepalli, Yu Cao	A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design.	ISQED	2008	DBLP DOI BibTeX RDF	Schottky barrier, analog design metrics, modeling, CNT
18	Biswajit Ray, Santanu Mahapatra	A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor.	VLSI Design	2008	DBLP DOI BibTeX RDF
18	S. Raja 0002, F. Varadi, Murat R. Becer, Joao Geada	Transistor level gate modeling for accurate and fast timing, noise, and power analysis.	DAC	2008	DBLP DOI BibTeX RDF	gate modeling, timing, statistical, crosstalk, multi threaded
18	Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas	Modeling Subthreshold Leakage Current in General Transistor Networks.	ISVLSI	2007	DBLP DOI BibTeX RDF
18	Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt	A low-power CAM using a 12-transistor design cell.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
18	Yiming Li 0005, Chih-Hong Hwang, Shao-Ming Yu	Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors.	International Conference on Computational Science (4)	2007	DBLP DOI BibTeX RDF	computational statistics, SRAM, modeling and simulation, FinFET
18	Asha Balijepalli, Saurabh Sinha, Yu Cao	Compact modeling of carbon nanotube transistor for early stage process-design exploration.	ISLPED	2007	DBLP DOI BibTeX RDF	optimum delay, schottky-barrier, surface potential, modeling, process variability, CNT
18	Martin Saint-Laurent, Baker Mohammad, Paul Bassett	A 65-nm pulsed latch with a single clocked transistor.	ISLPED	2007	DBLP DOI BibTeX RDF	low voltage swing, minimum clock power, pulsed latch, virtual-ground clocking
18	Paul E. Hasler, Scott Koziol, Ethan Farquhar, Arindam Basu	Transistor Channel Dendrites implementing HMM classifiers.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Afshin Nourivand, Chunyan Wang 0004, M. Omair Ahmad	An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri	A Structured ASIC Design Approach Using Pass Transistor Logic.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Chanseok Hwang, Peng Rong, Massoud Pedram	Sleep transistor distribution in row-based MTCMOS designs.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	leakage minimization, placement, MTCMOS
18	Takashi Sato, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu	A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation.	ISQED	2007	DBLP DOI BibTeX RDF
18	Benoit Dubois, Jean-Baptiste Kammerer, Luc Hébrard, Francis Braun	Analytical Modeling of Hot-Carrier Induced Degradation of MOS Transistor for Analog Design for Reliability.	ISQED	2007	DBLP DOI BibTeX RDF
18	Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz	A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults.	ETS	2006	DBLP DOI BibTeX RDF
18	Yu Wang 0002, Yongpan Liu, Rong Luo, Huazhong Yang	Genetic Algorithm Based Fine-Grain Sleep Transistor Insertion Technique for Leakage Optimization.	ICNC (1)	2006	DBLP DOI BibTeX RDF
18	Martin Trefzer, Jörg Langeheine, Karlheinz Meier, Johannes Schemmel	A Modular Framework for the Evolution of Circuits on Configurable Transistor Array Architectures.	AHS	2006	DBLP DOI BibTeX RDF
18	Maryam Etezad, Mojtaba Kahrizi	Schottky Barrier Carbon Nanotube Field Effect Transistor: Electronic Characterizations.	CCECE	2006	DBLP DOI BibTeX RDF
18	P. W. Chandana Prasad, Bruce Mills, Ali Assi 0001, S. M. N. Arosha Senanayake, V. C. Prasad	Evaluation time Estimation for Pass Transistor Logic circuits.	DELTA	2006	DBLP DOI BibTeX RDF
18	M. Emadi, Amir Jafargholi, M. H. Sargazi Moghadam, Mohammad Mahdi Nayebi	Optimum Supply and Threshold Voltages and Transistor Sizing Effects on Low Power SOI Circuit Design.	APCCAS	2006	DBLP DOI BibTeX RDF
18	Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen	Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits.	APCCAS	2006	DBLP DOI BibTeX RDF
18	Yu Wang 0002, Hui Wang 0004, Huazhong Yang	Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate.	APCCAS	2006	DBLP DOI BibTeX RDF
18	Shekhar Borkar	Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Hardware Computer System Organization
18	Rupesh S. Shelar, Sachin S. Sapatnekar	BDD decomposition for delay oriented pass transistor logic synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
18	Rob Roy, Debashis Bhattacharya, Vamsi Boppana	Transistor-Level Optimization of Digital Designs with Flex Cells.	Computer	2005	DBLP DOI BibTeX RDF	ASIC design methodology, integrated circuit design, power optimization, design and test, high-performance design
18	Adrian Stoica, Ricardo Salem Zebulum, Didier Keymeulen, Taher Daud	Transistor-Level Circuit Experiments Using Evolvable Hardware.	IWINAC (2)	2005	DBLP DOI BibTeX RDF
18	Yiming Li 0005	Application of Parallel Adaptive Computing Technique to Polysilicon Thin-Film Transistor Simulation.	HPCC	2005	DBLP DOI BibTeX RDF
18	Junichi Hirase, Tatsuya Furukawa	Chip Identification using the Characteristic Dispersion of Transistor.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
18	Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Gilles Sassatelli, Gaston Cambon, Michel Robert, Fernando Moraes 0001	Current mask generation: a transistor level security against DPA attacks.	SBCCI	2005	DBLP DOI BibTeX RDF	cryptography, side channel attacks, DPA, countermeasures
18	Heng-Ming Hsu, Tai-Hsing Lee	Optimum quiescent point of integrated power CMOS transistor for wireless portable applications.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
18	Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen	An efficient pass-transistor-logic synthesizer using multiplexers and inverters only.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
18	Phil Corbishley, David G. Haigh	Rules for systematic synthesis of all-transistor analogue circuits by admittance matrix expansion.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
18	Ananth Somayaji Goda, Gautam Kapila	Design For Degradation : CAD Tools for Managing Transistor Degradation Mechanisms.	ISQED	2005	DBLP DOI BibTeX RDF
18	Stefan Dilhaire, Stéphane Grauby, Sébastien Jorez, Wilfrid Claeys	Strain energy imaging of a power MOS transistor using speckle interferometry.	IEEE Trans. Reliab.	2004	DBLP DOI BibTeX RDF
18	Fabricio B. Bastian, Cristiano Lazzari, José Luís Almada Güntzel, Ricardo Reis 0001	A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool.	PATMOS	2004	DBLP DOI BibTeX RDF
18	Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao	64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi.	ISVLSI	2004	DBLP DOI BibTeX RDF	CPL, conditional sum adder, low-threshold voltage, differential-end, VLSI design, low-voltage
18	Hafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Mazder Rahman, Md. Rafiqul Islam 0001	Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic.	DSD	2004	DBLP DOI BibTeX RDF
18	Hamilton Klimach, Alfredo Arnaud, Márcio C. Schneider, Carlos Galup-Montoro	Characterization of MOS transistor current mismatch.	SBCCI	2004	DBLP DOI BibTeX RDF	matching, analog design, MOSFET, mismatch, compact models
18	Soo Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, Heung Soo Kim	Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit.	ISMVL	2004	DBLP DOI BibTeX RDF
18	Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi 0001, Hiroshi Inokawa, Yasuo Takahashi	A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic.	ISMVL	2004	DBLP DOI BibTeX RDF
18	Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi 0001	A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions.	ISMVL	2004	DBLP DOI BibTeX RDF
18	Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar	Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits.	ICCD	2004	DBLP DOI BibTeX RDF
18	Paul D. Smith, David W. Graham, Ravi Chawla, Paul E. Hasler	A five-transistor bandpass filter element.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
18	Eren Kursun, Soheil Ghiasi, Majid Sarrafzadeh	Transistor Level Budgeting for Power Optimization.	ISQED	2004	DBLP DOI BibTeX RDF
18	Arturo Hernández Aguirre, Ricardo Salem Zebulum, Carlos A. Coello Coello	Evolutionary Multiobjective Design targeting a Field Programmable Transistor Array.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
18	David M. Binkley, C. E. Hopper, Steve D. Tucker, Brian C. Moss, James M. Rochelle, Daniel Foty	A CAD methodology for optimizing transistor current and sizing in analog CMOS design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
18	Md. Rafiqul Islam 0001, Hafiz Md. Hasan Babu, Mohammad Abdur Rahim Mustafa, Md. Sumon Shahriar	A Heuristic Approach for Design of Easily Testable PLAs Using Pass Transistor Logic.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
18	G. Gautier, Samuel Crand, Olivier Bonnaud	Dynamic electrical characterization of CMOS-like Thin Film Transistor circuits.	MSE	2003	DBLP DOI BibTeX RDF
18	E. Kinvi-Boh, M. Aline, Olivier Sentieys, Edgar "Dan" Olson	MVL circuit design and characterization at the transistor level using SUS-LOC.	ISMVL	2003	DBLP DOI BibTeX RDF
18	Ali Abbasian, S. H. Rasouli, Ali Afzali-Kusha, Mehrdad Nourani	No-race charge recycling complementary pass transistor logic (NCRCPL) for low power applications.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
18	Mutlu Avci, Tülay Yildirim	A coding method for 123 decision diagram pass transistor logic circuit synthesis.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
18	Yi Zhao, Sujit Dey	Separate Dual-Transistor Registers - A Circuit Solution for On-line Testing of Transient Error in UDSM-IC.	IOLTS	2003	DBLP DOI BibTeX RDF
18	Geun Rae Cho, Tom Chen 0001	Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic.	ISQED	2003	DBLP DOI BibTeX RDF
18	Derek Wright, Manoj Sachdev	Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie.	ITC	2003	DBLP DOI BibTeX RDF
18	Alexis Landrault, Ludovic Pellier, Alexandre Richard, Christian Jay, Michel Robert, Daniel Auvergne	Transistor Level Synthesis Dedicated to Fast I.P. Prototyping.	PATMOS	2002	DBLP DOI BibTeX RDF
18	Mahesh Ketkar, Sachin S. Sapatnekar	Standby power optimization via transistor sizing and dual threshold voltage assignment.	ICCAD	2002	DBLP DOI BibTeX RDF
18	Mezyad M. Amourah, Randall L. Geiger	All digital transistor high gain operational amplifier using positive feedback technique.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
18	André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand	On the detectability of CMOS floating gate transistor faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
18	Masanori Hashimoto, Hidetoshi Onodera	Post-layout transistor sizing for power reduction in cell-based design.	ASP-DAC	2001	DBLP DOI BibTeX RDF
18	A. B. M. Harun-ur Rashid, Mazuhidul Karim, Syed Mahfuzul Aziz	Testing complementary pass-transistor logic circuits.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
18	Jonathan Scott	Reconciliation of methods for bipolar transistor thermal resistance extraction.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
18	Janusz Zarebski	A new electrothermal dynamic macromodel of the power Darlington transistor for SPICE.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
18	Saeid Nooshabadi	Modelling of effects of temperature profile in the MOS transistor characteristics.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
18	Mayukh Bhattacharya, Pinaki Mazumder, Ronald J. Lomax	Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic Gates.	VLSI Design	2001	DBLP DOI BibTeX RDF
18	Kishore Kasamsetty, Mahesh Ketkar, Sachin S. Sapatnekar	A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
18	Christoph Scholl 0001, Bernd Becker 0001	On the Generation of Multiplexer Circuits for Pass Transistor Logic.	DATE	2000	DBLP DOI BibTeX RDF
18	Jörg Langeheine, Simon Fölling, Karlheinz Meier, Johannes Schemmel	Towards a Silicon Primordial Soup: A Fast Approach to Hardware Evolution with a VLSI Transistor Array.	ICES	2000	DBLP DOI BibTeX RDF
18	Tudor Vinereanu, Sverre Lidholm	An improved pass transistor synthesis method for low power, high speed CMOS circuits.	ISLPED	2000	DBLP DOI BibTeX RDF
18	Michael S. Shur, Tor A. Fjeldly, Trond Ytterdal	Transistor Modeling for the VDSM Era.	ISQED	2000	DBLP DOI BibTeX RDF	field effect transistors, parameter extraction, SPICE, device modeling
18	Adrian Stoica, Didier Keymeulen, Ricardo Salem Zebulum, Anilkumar P. Thakoor, Taher Daud, Gerhard Klimeck, Y. Jin, Raoul Tawel, Vu Duong	Evolution of Analog Circuits on Field Programmable Transistor Arrays.	Evolvable Hardware	2000	DBLP DOI BibTeX RDF
18	Ranjit K. Dash, T. Pramod, Vinita Vasudevan, M. Ramakrishna 0001	A Transistor Level Placement Tool for Custom Cell Generation.	VLSI Design	2000	DBLP DOI BibTeX RDF	simulated annealing, placement
18	Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi	MINFLOTRANSIT: min-cost flow based transistor sizing tool.	DAC	2000	DBLP DOI BibTeX RDF
18	Manish Pandey, Randal E. Bryant	Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
18	S. Deuty, C. S. Mitter	Transistor paradigm shift required to meet the power demands for microprocessors.	IPCCC	1999	DBLP DOI BibTeX RDF
18	Leonid B. Goldgeisser, Michael M. Green	Some two-transistor circuits possess more than three operating points.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
18	Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos	An analytical, transistor-level energy model for SRAM-based caches.	ISCAS (6)	1999	DBLP DOI BibTeX RDF