Search results for "faults"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
23	Irith Pomeranz, Sudhakar M. Reddy	Static compaction for two-pattern test sets.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	two-pattern test sets, static compaction procedure, test set size reduction, redundant tests removal, redundant patterns removal, CMOS stuck open faults, reordering of tests, digital logic circuits, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, combinational circuits, combinational circuits, automatic testing, fault coverage, CMOS logic circuits, delay faults
23	O. A. Petlin, Stephen B. Furber	Scan testing of asynchronous sequential circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits
23	O. A. Petlin, Stephen B. Furber	Scan testing of micropipelines.	VTS	1995	DBLP DOI BibTeX RDF	asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines
22	Michael Crocker, Xiaobo Sharon Hu, Michael T. Niemier	Defects and faults in QCA-based PLAs.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	logic mapping, Nanotechnology, faults, defects, quantum-dot cellular automata
22	Bogdan Tomoyuki Nassu, Takashi Nanya	Interaction Faults Caused by Third-Party External Systems - A Case Study and Challenges.	ISAS	2008	DBLP DOI BibTeX RDF	Interaction Faults, Error Detection, Fault Model, Communication Protocols, Case Study
22	Stephan Eggersglüß, Rolf Drechsler	On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults.	ISMVL	2008	DBLP DOI BibTeX RDF	Boolean Encodings, ATPG, SAT, Path Delay Faults
22	Kyriakos Christou, Maria K. Michael, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez 0001, Matteo Sonza Reorda	A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions.	VTS	2008	DBLP DOI BibTeX RDF	SBST, path-delay faults, microprocessor test
22	Hafizur Rahaman 0001, Dipak Kumar Kole, Debesh Kumar Das, Bhargab B. Bhattacharya	On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set.	VLSI Design	2008	DBLP DOI BibTeX RDF	Missing-gate faults, quantum computing, reversible logic, testable design, universal test set
22	Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra	Latch Susceptibility to Transient Faults and New Hardening Approach.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Static Latch, Hardened Latch, Soft Errors, Transient Faults, Robust Design
22	Lorenzo Petroli, Carlos Arthur Lang Lisbôa, Fernanda Lima Kastensmidt, Luigi Carro	Using majority logic to cope with long duration transient faults.	SBCCI	2007	DBLP DOI BibTeX RDF	long duration transient faults, majority logic
22	Jong-Hoon Youn, Bella Bose, Seungjin Park	Fault-Tolerant Routing Algorithm in Meshes with Solid Faults.	J. Supercomput.	2006	DBLP DOI BibTeX RDF	solid faults, fault-tolerant, wormhole routing, mesh networks
22	Feng Shi 0010, Yiorgos Makris	Testing delay faults in asynchronous handshake circuits.	ICCAD	2006	DBLP DOI BibTeX RDF	test generation, asynchronous circuits, delay faults, handshake circuits
22	Colin Cooper, Ralf Klasing, Tomasz Radzik	Searching for Black-Hole Faults in a Network Using Multiple Agents.	OPODIS	2006	DBLP DOI BibTeX RDF	black hole faults, mobile agent, Graph exploration
22	Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas	Low power test generation for path delay faults using stability functions.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	low power, ATPG, path delay faults
22	Mahilchi Milir Vaseekar Kumar, Saravanan Padmanaban, Spyros Tragoudas	Low power ATPG for path delay faults.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	low power, ATPG, path delay faults, PODEM
22	Ad J. van de Goor, Said Hamdioui, Rob Wadsworth	Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests.	ITC	2004	DBLP DOI BibTeX RDF	address directions, peripheral circuit faults, fault coverage, March tests, data-backgrounds
22	S. Amitanand, I. Sanketh, K. Srinathan, Vinod Vaikuntanathan, C. Pandu Rangan	Distributed consensus in the presence of sectional faults.	PODC	2003	DBLP DOI BibTeX RDF	sectional faults, distributed consensus
22	Zhen Guo	Coefficient-based parametric faults detection in analog circuits.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	fault detection, Monte-Carlo simulation, system identification, parametric faults
22	Michele Favalli, Cecilia Metra	Bridging Faults in Pipelined Circuits.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	fault modeling, bridging faults, CMOS circuits, pipelined circuits
22	Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults.	IOLTW	2000	DBLP DOI BibTeX RDF	BIST, Random Testing, Delay Testing, Bridging Faults
22	Claude Thibeault	Efficient Diagnosis of Single/Double Bridging Faults with Delta Iddq Probabilistic Signatures and Viterbi Algorithm.	VTS	2000	DBLP DOI BibTeX RDF	probabilistic signatures, double faults, Diagnosis, Viterbi algorithm, Delta Iddq
22	Koji Yamazaki, Teruhiko Yamada	An approach to diagnose logical faults in partially observable sequential circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	logical faults, partially observable sequential circuits, internal nets, error sources, error propagation traceback, failing primary outputs, ISCAS'89 benchmark circuits, fault diagnosis, simulation results, probing, diagnostic resolution
22	Nihal J. Godambe, C.-J. Richard Shi	Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS.	VTS	1997	DBLP DOI BibTeX RDF	behavioral level noise modeling, jitter simulation, mixed-signal hardware description language, phase-locked loops, voltage-controlled oscillator, power supply noise, phase noise, VHDL-AMS, catastrophic faults, top down design, integrated circuit noise
22	Mark G. Karpovsky, Vyacheslav N. Yarmolik	Transparent random access memory testing for pattern sensitive faults.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	transparent memory testing, pseudoexhaustive memory testing, built-in self-test, memory testing, signature analysis, random access memory, pattern sensitive faults
22	Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal	Segment delay faults: a new fault model.	VTS	1996	DBLP DOI BibTeX RDF	segment delay faults, delay defect, distributed defect, rising transitions, falling transitions, transition tests, nonrobust tests, VLSI, fault diagnosis, logic testing, delays, integrated circuit testing, fault model, automatic testing, circuit analysis computing, robust tests, integrated circuit modelling, production testing, spot defect, manufacturing defects
22	Anastasios Vergis, Carlos Tobon 0002	Testing trees for multiple faults.	VTS	1996	DBLP DOI BibTeX RDF	testing trees, combinational logic cells, tree-structured circuits, VLSI, logic testing, integrated circuit testing, design for testability, logic design, combinational circuits, integrated logic circuits, multiple faults, test set size
22	Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel	Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.	VTS	1996	DBLP DOI BibTeX RDF	GA-based test generators, CMOS VLSI circuits, I/sub DDQ/ current testing, CMOS digital circuits, two-line bridging fault set, compact test set generation, genetic algorithms, VLSI, logic testing, integrated circuit testing, ATPG, automatic test pattern generator, automatic testing, fault location, bridging faults, CMOS digital integrated circuits, adaptive genetic algorithm
22	Fei Wang, Yu Hu 0001, Huawei Li 0001, Xiaowei Li 0001	A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults.	ASP-DAC	2008	DBLP DOI BibTeX RDF
22	Jin-Fu Li 0001	Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
21	Cristiana Bolchini, Antonio Miele, Fabio Rebaudengo, Fabio Salice, Donatella Sciuto, Luca Sterpone, Massimo Violante	Software and Hardware Techniques for SEU Detection in IP Processors.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Hardware/software techniques, Single-event upset faults, Reliability, Fault injection
21	Simon Ogg, Bashir M. Al-Hashimi, Alexandre Yakovlev	Asynchronous transient resilient links for NoC.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	point to point link, reliability, network-on-chip, asynchronous, transient faults
21	Ronen Gradwohl, Omer Reingold	Fault tolerance in large games.	EC	2008	DBLP DOI BibTeX RDF	large games, nash equilibrium, byzantine faults
21	Ranjith Purushothaman, Dewayne E. Perry	Toward Understanding the Rhetoric of Small Source Code Changes.	IEEE Trans. Software Eng.	2005	DBLP DOI BibTeX RDF	Source code changes, one-line changes, fault probabilities, software faults
21	Raquel Vigolvino Lopes, Walfredo Cirne, Francisco Vilar Brasileiro	Using Process Restarts to Improve Dynamic Provisioning.	DSOM	2004	DBLP DOI BibTeX RDF	software faults, restart, dynamic provisioning, n-tier applications
21	Dahlia Malkhi, Michael Merritt, Michael K. Reiter, Gadi Taubenfeld	Objects shared by Byzantine processes.	Distributed Comput.	2003	DBLP DOI BibTeX RDF	shared memory, consensus, emulation, Byzantine faults
21	Derek Lawson, Gerry Coleman	Investigating software measures to improve product reliability.	SAC	2002	DBLP DOI BibTeX RDF	metrics, software, quality, process improvement, failures, faults
21	Zhen Jiang, Jie Wu 0001	A Limited-Global Fault Information Model for Dynamic Routing in 2-D Meshes.	IPDPS	2002	DBLP DOI BibTeX RDF	2-D meshes, safety levels, fault tolerance, routing, Dynamic faults
21	Matthias Klaus, Ad J. van de Goor	Tests for Resistive and Capacitive Defects in Address Decoders.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	address decoders, test conditions, Defects, opens, dynamic faults, capacitive coupling
21	Naotake Kamiura, Masashi Tomita, Teijiro Isokawa, Nobuyuki Matsui	On Variable-Shift-Based Fault Compensation of Fuzzy Controllers.	DFT	2001	DBLP DOI BibTeX RDF	fault compensation, fault tolerance, fuzzy control, stuck-at faults, on-line testing
21	Charles E. Stroud, James R. Bailey, Johan R. Emmert	A New Method for Testing Re-Programmable PLAs.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	electrically erasable programmable logic array testing, manufacturing test development, bridging faults
21	Matthew Worsman, Mike W. T. Wong, Yim-Shu Lee	A Pre-Simulation Measure of D.C. Design-for-Testability Fault Diagnosis Quality.	ISQED	2000	DBLP DOI BibTeX RDF	Equivalent faults, One-port circuits, Fault diagnosis, Design for testability, Fault collapsing
21	M. A. El-Gamal, Mohamed Fathy Abu El-Yazeed	A Combined Clustering and Neural Network Approach for Analog Multiple Hard Fault Classification.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	multiple hard faults, fault clustering, learning vector quantization neural networks, feature selection, analog circuits, fault classification
21	Ad J. van de Goor, J. E. Simonse	Defining SRAM Resistive Defects and Their Simulation Stimuli.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Resistive defects, simulation stimuli, SRAM functional faults, SPICE simulation
21	Parag K. Lala, Anup Singh, Alvernon Walker	A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs.	DFT	1999	DBLP DOI BibTeX RDF	DCVSL, Stuck-ON/OFF, Stuck-at Faults, Self-testing
21	Antonis M. Paschalis, Dimitris Gizopoulos, Nikolaos Gaitanis	Concurrent Delay Testing in Totally Self-Checking Systems.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	concurrent on-line detection, duplication systems, path delay faults, totally self-checking circuits, error indicators
21	Vijay R. Sar-Dessai, D. M. H. Walker	Accurate Fault Modeling and Fault Simulation of Resistive Bridges.	DFT	1998	DBLP DOI BibTeX RDF	realistic bridges, zero-ohm bridges, Resistive bridging faults, low-voltage testing
21	Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal	Path Delay Testing: Variable-Clock Versus Rated-Clock.	VLSI Design	1998	DBLP DOI BibTeX RDF	rated-clock testing, slow-clock testing, Delay testing, path delay faults, sequential circuit test
21	Walter W. Weber, Adit D. Singh	Incorporating IDDQ Testing with BIST for Improved Coverage: An Experimental Study.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	open faults, BIST, fault coverage, built in current sensor, BICS, I DDQ
21	Lech Józwiak	On the use of term trees for effective and efficient test pattern generation.	EUROMICRO	1997	DBLP DOI BibTeX RDF	term trees, structural automatic test pattern generation, fault discovery, structural fault model, term tree based ATPG algorithm, nonredundant faults, minimal test set, circuit redundancy, logic design, fault model, data representation, automatic test software
21	Richard A. DeMillo, Hsin Pan, Eugene H. Spafford	Critical Slicing for Software Fault Localization.	ISSTA	1996	DBLP DOI BibTeX RDF	critical slicing, static program slicing, testing, debugging, failures, faults, fault localization, mutation analysis, dynamic program slicing
21	Nikolaos Gaitanis, Dimitris Gizopoulos, Antonis M. Paschalis, Panagiotis Kostarakis	An asynchronous totally self-checking two-rail code error indicator.	VTS	1996	DBLP DOI BibTeX RDF	asynchronous TSC error indicator, totally self-checking error indicator, concurrent detection, two-rail code error indicator, CMOS implementation, VLSI, logic testing, delays, integrated circuit testing, error detection, automatic testing, asynchronous circuits, CMOS logic circuits, delay faults
21	Jwu E. Chen, Chung-Len Lee 0001, Wen-Zen Shen, Beyin Chen	Fanout fault analysis for digital logic circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	fanout fault analysis, digital logic circuits, combinational benchmark circuits, sequential benchmark circuits, target faults, fault diagnosis, logic testing, test generation, sequential circuits, combinational circuits, fault simulation, fault collapsing
21	Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita	Transistor leakage fault location with ZDDQ measurement.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	field effect transistor circuits, transistor leakage fault location, I/sub DDQ/ measurement, equivalence fault collapsing, diagnosed faults, gate-array circuit, fault diagnosis, logic testing, random tests, fault location, CMOS logic circuits, leakage currents, logic arrays, CMOS circuit, deterministic tests, electric current measurement, diagnostic resolution
21	Alessandro Bogliolo, Maurizio Damiani, Piero Olivo, Bruno Riccò	Reliability evaluation of combinational logic circuits by symbolic simulation.	VTS	1995	DBLP DOI BibTeX RDF	mcnc benchmark circuits, fault-tolerant combinational logic circuits, circuit functionality, fault indicators, control variables, BDD-based symbolic simulation, undetectable multiple faults, VLSI, VLSI, combinational circuits, logic CAD, digital simulation, circuit analysis computing, reliability evaluation, integrated circuit reliability
21	Noé Lopez-Benitez	Dependability Modeling and Analysis of Distributed Programs.	IEEE Trans. Software Eng.	1994	DBLP DOI BibTeX RDF	program reliability, program availability, distributed computing system environment, repair actions, global repair mode, centralized repair team, system status restoration, failure state, local repair model, program interruption, Petri nets, distributed algorithms, software reliability, distributed programs, stochastic processes, programming theory, dependability analysis, system recovery, stochastic Petri nets, program diagnostics, hardware support, multiprocessing programs, program execution, file distribution, dependability modeling, hardware faults
21	Rajendra V. Boppana, Suresh Chalasani	Fault-tolerant routing with non-adaptive wormhole algorithms in mesh networks.	SC	1994	DBLP DOI BibTeX RDF	block faults, nonadaptive routing, deadlocks, wormhole routing, mesh networks, fault-tolerant routing, multicomputer networks
21	Michael Nicolaidis	Shorts in self-checking circuits.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	strongly fault-secure circuits, transistor faults, error detecting codes, self-checking circuits, totally self-checking circuits
21	Michael H. Woodbury, Kang G. Shin	Measurement and Analysis of Workload Effects on Fault Latency in Real-Time Systems.	IEEE Trans. Software Eng.	1990	DBLP DOI BibTeX RDF	workload effects, fault latency, control computer systems, multiple latent faults, coverage failure, synthetic work generator, hardware fault injector, NASA Airlab, software engineering, real-time systems, real-time systems, fault tolerant computing, multiprocessing systems, program testing, system recovery, control systems, recovery mechanisms, fault-tolerant multiprocessor
21	Chris Lewis 0002, Jim Whitehead	Runtime repair of software faults using event-driven monitoring.	ICSE (2)	2010	DBLP DOI BibTeX RDF	message broker, runtime software-fault monitoring, temporal invariants, specifications, video games, rule engine, event-driven systems
21	Bernadette Charron-Bost, André Schiper	The Heard-Of model: computing in distributed systems with benign faults.	Distributed Comput.	2009	DBLP DOI BibTeX RDF	Benign fault, HO (Heard-Of) model, Transmission fault, Consensus, Computational model
21	Qiang Xu 0001, Yubin Zhang, Krishnendu Chakrabarty	SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Core-based system-on-chip, test scheduling, test-access mechanism (TAM), interconnect testing
21	Ian J. Hayes	Dynamically Detecting Faults via Integrity Constraints.	Methods, Models and Tools for Fault Tolerance	2009	DBLP DOI BibTeX RDF	fault detection, Integrity constraint, action system, real-time programming
21	Masahiro Tsunoyama, Hirokazu Jinno, Masayuki Ogawa, Tatsuo Sato	An Application of Fuzzy Measure and Integral for Diagnosing Faults in Rotating Machines.	Tools and Applications with Artificial Intelligence	2009	DBLP DOI BibTeX RDF
21	Peter Tummeltshammer, Andreas Steininger	On the role of the power supply as an entry for common cause faults - An experimental analysis.	DDECS	2009	DBLP DOI BibTeX RDF
21	Jiadong Ren, Changzhen Hu, Kunsheng Wang, Di Wu 0033	A Method for Analyzing Software Faults Based on Mining Outliers' Feature Attribute Sets.	AMT	2009	DBLP DOI BibTeX RDF
21	Ahmed E. Hassan	Predicting faults using the complexity of code changes.	ICSE	2009	DBLP DOI BibTeX RDF
21	Safeeullah Soomro, Franz Wotawa	Detect and Localize Faults in Alias-Free Programs Using Specification Knowledge.	IEA/AIE	2009	DBLP DOI BibTeX RDF
21	Irith Pomeranz, Sudhakar M. Reddy	Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
21	M. Ümit Uyar, Samrat S. Batth, Yu Wang 0012, Mariusz A. Fecko	Algorithms for Modeling a Class of Single Timing Faults in Communication Protocols.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Finite State Machine (FSM), Extended Finite State Machine (EFSM), Timed EFSM, Fault Modeling, Conformance Testing, Timers
21	Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy	On Complete Functional Broadside Tests for Transition Faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
21	Piotr Jantos, Damian Grzechca, Tomasz Golonek, Jerzy Rutkowski	The Influence of Global Parametric Faults on Analogue Electronic Circuits Time Domain Response Features.	DDECS	2008	DBLP DOI BibTeX RDF
21	Lingfu Xie, Du Xu, Qing Yao, Lei Song	A New Fault-Tolerant Wormhole Routing Scheme in Tori with Convex Faults.	HASE	2008	DBLP DOI BibTeX RDF
21	Miao Jiang 0002, Mohammad Ahmad Munawar, Thomas Reidemeister, Paul A. S. Ward	Detection and Diagnosis of Recurrent Faults in Software Systems by Invariant Analysis.	HASE	2008	DBLP DOI BibTeX RDF
21	Jaymie Strecker, Atif M. Memon	Relationships between Test Suites, Faults, and Fault Detection in GUI Testing.	ICST	2008	DBLP DOI BibTeX RDF
21	Ing-Xiang Chen, Cheng-Zen Yang, Ting-Kun Lu, Hojun Jaygarl	Implicit Social Network Model for Predicting and Tracking the Location of Faults.	COMPSAC	2008	DBLP DOI BibTeX RDF	bug report managing system (BRMS), implicit social network analysis, PageRank, bug prediction
21	Jon Stearley, Adam J. Oliner	Bad Words: Finding Faults in Spirit's Syslogs.	CCGRID	2008	DBLP DOI BibTeX RDF
21	Claudomir Cardoso, Yomara Pires, Jefferson Morais, Aldebaro Klautau	Hierarchical Agglomerative Clustering of Short-Circuit Faults in Transmission Lines.	SBRN	2008	DBLP DOI BibTeX RDF
21	Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal	Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults.	VTS	2008	DBLP DOI BibTeX RDF	Diagnosis, ATPG, Fault Model, Fault Collapsing, Implication Graph
21	Xiangyu Zhang 0001, Neelam Gupta, Rajiv Gupta 0001	A study of effectiveness of dynamic slicing in locating real faults.	Empir. Softw. Eng.	2007	DBLP DOI BibTeX RDF	Full slicing, Exploring slices, Fault location, Dynamic program slicing, Data slicing
21	Crineu Tres, Leandro Buss Becker, Edgar Nett	Real-Time Tasks Scheduling with Value Control to Predict Timing Faults During Overload.	ISORC	2007	DBLP DOI BibTeX RDF
21	Marta Capiluppi, Manfred Morari	Networks of Hybrid Systems: Connections Faults Modelling and Detection.	HSCC	2007	DBLP DOI BibTeX RDF
21	Shuhua Xu, Benxiong Huang, Yuchun Huang	Classification and Diagnosis of Mechanical Faults Using the RBF Network Based on the Local Bispectra.	ISNN (3)	2007	DBLP DOI BibTeX RDF
21	Ching-Wen Chen	Design schemes of dynamic rerouting networks with destination tag routing for tolerating faults and preventing collisions.	J. Supercomput.	2006	DBLP DOI BibTeX RDF	Destination tag routing, Fault tolerance, Performance, Parallel computing, Multistage interconnection network (MIN), Collision, Dynamic rerouting
21	Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee 0001, Jwu E. Chen	IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
21	Kalpesh Kapoor	Formal Analysis of Coupling Hypothesis for Logical Faults.	Innov. Syst. Softw. Eng.	2006	DBLP DOI BibTeX RDF	Logical fault, Software testing, Mutation testing, Fault-based testing, Boolean specification
21	Nektarios Kranitis, Andreas Merentitis, Nikolaos Laoutaris, George Theodorou, Antonis M. Paschalis, Dimitris Gizopoulos, Constantin Halatsis	Optimal periodic testing of intermittent faults in embedded pipelined processor applications.	DATE	2006	DBLP DOI BibTeX RDF
21	Yoshihiro Nakaminami, Hirotsugu Kakugawa, Toshimitsu Masuzawa	An advanced performance analysis of self-stabilizing protocols: stabilization time with transient faults during convergence.	IPDPS	2006	DBLP DOI BibTeX RDF
21	Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato	Effective Post-BIST Fault Diagnosis for Multiple Faults.	DFT	2006	DBLP DOI BibTeX RDF
21	Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian	Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories.	VTS	2006	DBLP DOI BibTeX RDF
21	Jais Abraham, Uday Goel, Arun Kumar	Multi-Cycle Sensitizable Transition Delay Faults.	VTS	2006	DBLP DOI BibTeX RDF
21	Stefan Dobrev, Rastislav Kralovic, Richard Královic, Nicola Santoro	On Fractional Dynamic Faults with Threshold.	SIROCCO	2006	DBLP DOI BibTeX RDF
21	Mikhail Nesterenko, Sébastien Tixeuil	Discovering Network Topology in the Presence of Byzantine Faults.	SIROCCO	2006	DBLP DOI BibTeX RDF
21	Philipp Peti, Roman Obermaisser, Harald Paulitsch	Investigating Connector Faults in the Time-Triggered Architecture.	ETFA	2006	DBLP DOI BibTeX RDF
21	Bartosz Sokol, S. V. Yarmolik	Address Sequences for March Tests to Detect Pattern Sensitive Faults.	DELTA	2006	DBLP DOI BibTeX RDF
21	Bogdan Tomoyuki Nassu, Takashi Nanya	A Scenario of Tolerating Interaction Faults Between Otherwise Correct Systems.	PRDC	2006	DBLP DOI BibTeX RDF
21	Huawei Li 0001, Xiaowei Li 0001	Selection of Crosstalk-Induced Faults in Enhanced Delay Test.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	automatic test pattern generation (ATPG), crosstalk, delay test, critical paths
21	Viraj Kumar, Mahesh Viswanathan 0001	Conformance testing in the presence of multiple faults.	SODA	2005	DBLP BibTeX RDF
21	Assaf Harel, Eliezer Kantorowitz	Estimating the Number of Faults Remaining in Software Code Documents Inspected with Iterative Code Reviews.	SwSTE	2005	DBLP DOI BibTeX RDF
21	Gabriela Jacques-Silva, Roberto Jung Drebes, Taisy Silva Weber, Eliane Martins	Injecting Communication Faults to Experimentally Validate Java Distributed Applications.	ISSADS	2005	DBLP DOI BibTeX RDF
21	Gerald Steinbauer, Martin Mörth, Franz Wotawa	Real-Time Diagnosis and Repair of Faults of Robot Control Software.	RoboCup	2005	DBLP DOI BibTeX RDF