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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 10002 occurrences of 3019 keywords
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Results
Found 11893 publication records. Showing 11893 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
23 | Irith Pomeranz, Sudhakar M. Reddy |
Static compaction for two-pattern test sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 222-228, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
two-pattern test sets, static compaction procedure, test set size reduction, redundant tests removal, redundant patterns removal, CMOS stuck open faults, reordering of tests, digital logic circuits, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, combinational circuits, combinational circuits, automatic testing, fault coverage, CMOS logic circuits, delay faults |
23 | O. A. Petlin, Stephen B. Furber |
Scan testing of asynchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 224-229, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits |
23 | O. A. Petlin, Stephen B. Furber |
Scan testing of micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 296-303, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines |
22 | Michael Crocker, Xiaobo Sharon Hu, Michael T. Niemier |
Defects and faults in QCA-based PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 5(2), pp. 8:1-8:27, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
logic mapping, Nanotechnology, faults, defects, quantum-dot cellular automata |
22 | Bogdan Tomoyuki Nassu, Takashi Nanya |
Interaction Faults Caused by Third-Party External Systems - A Case Study and Challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISAS ![In: Service Availability, 5th International Service Availability Symposium, ISAS 2008, Tokyo, Japan, May 19-21, 2008, Proceedings, pp. 59-74, 2008, Springer, 978-3-540-68128-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Interaction Faults, Error Detection, Fault Model, Communication Protocols, Case Study |
22 | Stephan Eggersglüß, Rolf Drechsler |
On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 94-99, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Boolean Encodings, ATPG, SAT, Path Delay Faults |
22 | Kyriakos Christou, Maria K. Michael, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez 0001, Matteo Sonza Reorda |
A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 389-394, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SBST, path-delay faults, microprocessor test |
22 | Hafizur Rahaman 0001, Dipak Kumar Kole, Debesh Kumar Das, Bhargab B. Bhattacharya |
On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 163-168, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Missing-gate faults, quantum computing, reversible logic, testable design, universal test set |
22 | Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra |
Latch Susceptibility to Transient Faults and New Hardening Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(9), pp. 1255-1268, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Static Latch, Hardened Latch, Soft Errors, Transient Faults, Robust Design |
22 | Lorenzo Petroli, Carlos Arthur Lang Lisbôa, Fernanda Lima Kastensmidt, Luigi Carro |
Using majority logic to cope with long duration transient faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 354-359, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
long duration transient faults, majority logic |
22 | Jong-Hoon Youn, Bella Bose, Seungjin Park |
Fault-Tolerant Routing Algorithm in Meshes with Solid Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 37(2), pp. 161-177, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
solid faults, fault-tolerant, wormhole routing, mesh networks |
22 | Feng Shi 0010, Yiorgos Makris |
Testing delay faults in asynchronous handshake circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 193-197, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
test generation, asynchronous circuits, delay faults, handshake circuits |
22 | Colin Cooper, Ralf Klasing, Tomasz Radzik |
Searching for Black-Hole Faults in a Network Using Multiple Agents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OPODIS ![In: Principles of Distributed Systems, 10th International Conference, OPODIS 2006, Bordeaux, France, December 12-15, 2006, Proceedings, pp. 320-332, 2006, Springer, 3-540-49990-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
black hole faults, mobile agent, Graph exploration |
22 | Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas |
Low power test generation for path delay faults using stability functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 8-12, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low power, ATPG, path delay faults |
22 | Mahilchi Milir Vaseekar Kumar, Saravanan Padmanaban, Spyros Tragoudas |
Low power ATPG for path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 389-392, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
low power, ATPG, path delay faults, PODEM |
22 | Ad J. van de Goor, Said Hamdioui, Rob Wadsworth |
Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 114-123, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
address directions, peripheral circuit faults, fault coverage, March tests, data-backgrounds |
22 | S. Amitanand, I. Sanketh, K. Srinathan, Vinod Vaikuntanathan, C. Pandu Rangan |
Distributed consensus in the presence of sectional faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODC ![In: Proceedings of the Twenty-Second ACM Symposium on Principles of Distributed Computing, PODC 2003, Boston, Massachusetts, USA, July 13-16, 2003, pp. 202-210, 2003, ACM, 1-58113-708-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
sectional faults, distributed consensus |
22 | Zhen Guo |
Coefficient-based parametric faults detection in analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 299-302, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
fault detection, Monte-Carlo simulation, system identification, parametric faults |
22 | Michele Favalli, Cecilia Metra |
Bridging Faults in Pipelined Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(6), pp. 617-629, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fault modeling, bridging faults, CMOS circuits, pipelined circuits |
22 | Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel |
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 121-126, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
BIST, Random Testing, Delay Testing, Bridging Faults |
22 | Claude Thibeault |
Efficient Diagnosis of Single/Double Bridging Faults with Delta Iddq Probabilistic Signatures and Viterbi Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 431-438, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
probabilistic signatures, double faults, Diagnosis, Viterbi algorithm, Delta Iddq |
22 | Koji Yamazaki, Teruhiko Yamada |
An approach to diagnose logical faults in partially observable sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 168-173, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
logical faults, partially observable sequential circuits, internal nets, error sources, error propagation traceback, failing primary outputs, ISCAS'89 benchmark circuits, fault diagnosis, simulation results, probing, diagnostic resolution |
22 | Nihal J. Godambe, C.-J. Richard Shi |
Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 177-183, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
behavioral level noise modeling, jitter simulation, mixed-signal hardware description language, phase-locked loops, voltage-controlled oscillator, power supply noise, phase noise, VHDL-AMS, catastrophic faults, top down design, integrated circuit noise |
22 | Mark G. Karpovsky, Vyacheslav N. Yarmolik |
Transparent random access memory testing for pattern sensitive faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 9(3), pp. 251-266, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
transparent memory testing, pseudoexhaustive memory testing, built-in self-test, memory testing, signature analysis, random access memory, pattern sensitive faults |
22 | Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal |
Segment delay faults: a new fault model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 32-41, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
segment delay faults, delay defect, distributed defect, rising transitions, falling transitions, transition tests, nonrobust tests, VLSI, fault diagnosis, logic testing, delays, integrated circuit testing, fault model, automatic testing, circuit analysis computing, robust tests, integrated circuit modelling, production testing, spot defect, manufacturing defects |
22 | Anastasios Vergis, Carlos Tobon 0002 |
Testing trees for multiple faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 444-449, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
testing trees, combinational logic cells, tree-structured circuits, VLSI, logic testing, integrated circuit testing, design for testability, logic design, combinational circuits, integrated logic circuits, multiple faults, test set size |
22 | Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel |
Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 456-462, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
GA-based test generators, CMOS VLSI circuits, I/sub DDQ/ current testing, CMOS digital circuits, two-line bridging fault set, compact test set generation, genetic algorithms, VLSI, logic testing, integrated circuit testing, ATPG, automatic test pattern generator, automatic testing, fault location, bridging faults, CMOS digital integrated circuits, adaptive genetic algorithm |
22 | Fei Wang, Yu Hu 0001, Huawei Li 0001, Xiaowei Li 0001 |
A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 571-576, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Jin-Fu Li 0001 |
Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 65-70, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Cristiana Bolchini, Antonio Miele, Fabio Rebaudengo, Fabio Salice, Donatella Sciuto, Luca Sterpone, Massimo Violante |
Software and Hardware Techniques for SEU Detection in IP Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 35-44, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Hardware/software techniques, Single-event upset faults, Reliability, Fault injection |
21 | Simon Ogg, Bashir M. Al-Hashimi, Alexandre Yakovlev |
Asynchronous transient resilient links for NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 209-214, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
point to point link, reliability, network-on-chip, asynchronous, transient faults |
21 | Ronen Gradwohl, Omer Reingold |
Fault tolerance in large games. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EC ![In: Proceedings 9th ACM Conference on Electronic Commerce (EC-2008), Chicago, IL, USA, June 8-12, 2008, pp. 274-283, 2008, ACM, 978-1-60558-169-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
large games, nash equilibrium, byzantine faults |
21 | Ranjith Purushothaman, Dewayne E. Perry |
Toward Understanding the Rhetoric of Small Source Code Changes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 31(6), pp. 511-526, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Source code changes, one-line changes, fault probabilities, software faults |
21 | Raquel Vigolvino Lopes, Walfredo Cirne, Francisco Vilar Brasileiro |
Using Process Restarts to Improve Dynamic Provisioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSOM ![In: Utility Computing: 15th IFIP/IEEE International Workshop on Distributed Systems: Operations and Management, DSOM 2004, Davis, CA, USA, November 15-17, 2004.Proceedings, pp. 220-231, 2004, Springer, 3-540-23631-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
software faults, restart, dynamic provisioning, n-tier applications |
21 | Dahlia Malkhi, Michael Merritt, Michael K. Reiter, Gadi Taubenfeld |
Objects shared by Byzantine processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 16(1), pp. 37-48, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
shared memory, consensus, emulation, Byzantine faults |
21 | Derek Lawson, Gerry Coleman |
Investigating software measures to improve product reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2002 ACM Symposium on Applied Computing (SAC), March 10-14, 2002, Madrid, Spain, pp. 1031-1035, 2002, ACM, 1-58113-445-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
metrics, software, quality, process improvement, failures, faults |
21 | Zhen Jiang, Jie Wu 0001 |
A Limited-Global Fault Information Model for Dynamic Routing in 2-D Meshes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
2-D meshes, safety levels, fault tolerance, routing, Dynamic faults |
21 | Matthias Klaus, Ad J. van de Goor |
Tests for Resistive and Capacitive Defects in Address Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 31-36, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
address decoders, test conditions, Defects, opens, dynamic faults, capacitive coupling |
21 | Naotake Kamiura, Masashi Tomita, Teijiro Isokawa, Nobuyuki Matsui |
On Variable-Shift-Based Fault Compensation of Fuzzy Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 436-444, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
fault compensation, fault tolerance, fuzzy control, stuck-at faults, on-line testing |
21 | Charles E. Stroud, James R. Bailey, Johan R. Emmert |
A New Method for Testing Re-Programmable PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(6), pp. 635-640, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
electrically erasable programmable logic array testing, manufacturing test development, bridging faults |
21 | Matthew Worsman, Mike W. T. Wong, Yim-Shu Lee |
A Pre-Simulation Measure of D.C. Design-for-Testability Fault Diagnosis Quality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 361-368, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Equivalent faults, One-port circuits, Fault diagnosis, Design for testability, Fault collapsing |
21 | M. A. El-Gamal, Mohamed Fathy Abu El-Yazeed |
A Combined Clustering and Neural Network Approach for Analog Multiple Hard Fault Classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(3), pp. 207-217, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
multiple hard faults, fault clustering, learning vector quantization neural networks, feature selection, analog circuits, fault classification |
21 | Ad J. van de Goor, J. E. Simonse |
Defining SRAM Resistive Defects and Their Simulation Stimuli. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 33-40, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Resistive defects, simulation stimuli, SRAM functional faults, SPICE simulation |
21 | Parag K. Lala, Anup Singh, Alvernon Walker |
A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 238-246, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
DCVSL, Stuck-ON/OFF, Stuck-at Faults, Self-testing |
21 | Antonis M. Paschalis, Dimitris Gizopoulos, Nikolaos Gaitanis |
Concurrent Delay Testing in Totally Self-Checking Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(1-2), pp. 55-61, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
concurrent on-line detection, duplication systems, path delay faults, totally self-checking circuits, error indicators |
21 | Vijay R. Sar-Dessai, D. M. H. Walker |
Accurate Fault Modeling and Fault Simulation of Resistive Bridges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 102-107, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
realistic bridges, zero-ohm bridges, Resistive bridging faults, low-voltage testing |
21 | Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal |
Path Delay Testing: Variable-Clock Versus Rated-Clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 470-475, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
rated-clock testing, slow-clock testing, Delay testing, path delay faults, sequential circuit test |
21 | Walter W. Weber, Adit D. Singh |
Incorporating IDDQ Testing with BIST for Improved Coverage: An Experimental Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(2), pp. 147-156, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
open faults, BIST, fault coverage, built in current sensor, BICS, I DDQ |
21 | Lech Józwiak |
On the use of term trees for effective and efficient test pattern generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 87-95, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
term trees, structural automatic test pattern generation, fault discovery, structural fault model, term tree based ATPG algorithm, nonredundant faults, minimal test set, circuit redundancy, logic design, fault model, data representation, automatic test software |
21 | Richard A. DeMillo, Hsin Pan, Eugene H. Spafford |
Critical Slicing for Software Fault Localization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSTA ![In: Proceedings of the 1996 International Symposium on Software Testing and Analysis, ISSTA 1996, San Diego, CA, USA, January 8-10, 1996, pp. 121-134, 1996, ACM, 0-89791-787-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
critical slicing, static program slicing, testing, debugging, failures, faults, fault localization, mutation analysis, dynamic program slicing |
21 | Nikolaos Gaitanis, Dimitris Gizopoulos, Antonis M. Paschalis, Panagiotis Kostarakis |
An asynchronous totally self-checking two-rail code error indicator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 151-156, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
asynchronous TSC error indicator, totally self-checking error indicator, concurrent detection, two-rail code error indicator, CMOS implementation, VLSI, logic testing, delays, integrated circuit testing, error detection, automatic testing, asynchronous circuits, CMOS logic circuits, delay faults |
21 | Jwu E. Chen, Chung-Len Lee 0001, Wen-Zen Shen, Beyin Chen |
Fanout fault analysis for digital logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 33-39, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
fanout fault analysis, digital logic circuits, combinational benchmark circuits, sequential benchmark circuits, target faults, fault diagnosis, logic testing, test generation, sequential circuits, combinational circuits, fault simulation, fault collapsing |
21 | Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita |
Transistor leakage fault location with ZDDQ measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 51-57, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
field effect transistor circuits, transistor leakage fault location, I/sub DDQ/ measurement, equivalence fault collapsing, diagnosed faults, gate-array circuit, fault diagnosis, logic testing, random tests, fault location, CMOS logic circuits, leakage currents, logic arrays, CMOS circuit, deterministic tests, electric current measurement, diagnostic resolution |
21 | Alessandro Bogliolo, Maurizio Damiani, Piero Olivo, Bruno Riccò |
Reliability evaluation of combinational logic circuits by symbolic simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 235-243, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
mcnc benchmark circuits, fault-tolerant combinational logic circuits, circuit functionality, fault indicators, control variables, BDD-based symbolic simulation, undetectable multiple faults, VLSI, VLSI, combinational circuits, logic CAD, digital simulation, circuit analysis computing, reliability evaluation, integrated circuit reliability |
21 | Noé Lopez-Benitez |
Dependability Modeling and Analysis of Distributed Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 20(5), pp. 345-352, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
program reliability, program availability, distributed computing system environment, repair actions, global repair mode, centralized repair team, system status restoration, failure state, local repair model, program interruption, Petri nets, distributed algorithms, software reliability, distributed programs, stochastic processes, programming theory, dependability analysis, system recovery, stochastic Petri nets, program diagnostics, hardware support, multiprocessing programs, program execution, file distribution, dependability modeling, hardware faults |
21 | Rajendra V. Boppana, Suresh Chalasani |
Fault-tolerant routing with non-adaptive wormhole algorithms in mesh networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings Supercomputing '94, Washington, DC, USA, November 14-18, 1994, pp. 693-702, 1994, IEEE Computer Society, 0-8186-6605-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
block faults, nonadaptive routing, deadlocks, wormhole routing, mesh networks, fault-tolerant routing, multicomputer networks |
21 | Michael Nicolaidis |
Shorts in self-checking circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 1(4), pp. 257-273, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
strongly fault-secure circuits, transistor faults, error detecting codes, self-checking circuits, totally self-checking circuits |
21 | Michael H. Woodbury, Kang G. Shin |
Measurement and Analysis of Workload Effects on Fault Latency in Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 16(2), pp. 212-216, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
workload effects, fault latency, control computer systems, multiple latent faults, coverage failure, synthetic work generator, hardware fault injector, NASA Airlab, software engineering, real-time systems, real-time systems, fault tolerant computing, multiprocessing systems, program testing, system recovery, control systems, recovery mechanisms, fault-tolerant multiprocessor |
21 | Chris Lewis 0002, Jim Whitehead |
Runtime repair of software faults using event-driven monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSE (2) ![In: Proceedings of the 32nd ACM/IEEE International Conference on Software Engineering - Volume 2, ICSE 2010, Cape Town, South Africa, 1-8 May 2010, pp. 275-280, 2010, ACM. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
message broker, runtime software-fault monitoring, temporal invariants, specifications, video games, rule engine, event-driven systems |
21 | Bernadette Charron-Bost, André Schiper |
The Heard-Of model: computing in distributed systems with benign faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 22(1), pp. 49-71, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Benign fault, HO (Heard-Of) model, Transmission fault, Consensus, Computational model |
21 | Qiang Xu 0001, Yubin Zhang, Krishnendu Chakrabarty |
SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(1), pp. 4:1-4:27, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Core-based system-on-chip, test scheduling, test-access mechanism (TAM), interconnect testing |
21 | Ian J. Hayes |
Dynamically Detecting Faults via Integrity Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Methods, Models and Tools for Fault Tolerance ![In: Methods, Models and Tools for Fault Tolerance, pp. 85-103, 2009, Springer, 978-3-642-00866-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fault detection, Integrity constraint, action system, real-time programming |
21 | Masahiro Tsunoyama, Hirokazu Jinno, Masayuki Ogawa, Tatsuo Sato |
An Application of Fuzzy Measure and Integral for Diagnosing Faults in Rotating Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Tools and Applications with Artificial Intelligence ![In: Tools and Applications with Artificial Intelligence, pp. 121-133, 2009, Springer, 978-3-540-88068-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Peter Tummeltshammer, Andreas Steininger |
On the role of the power supply as an entry for common cause faults - An experimental analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 152-157, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Jiadong Ren, Changzhen Hu, Kunsheng Wang, Di Wu 0033 |
A Method for Analyzing Software Faults Based on Mining Outliers' Feature Attribute Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AMT ![In: Active Media Technology, 5th International Conference, AMT 2009, Beijing, China, October 22-24, 2009. Proceedings, pp. 409-417, 2009, Springer, 978-3-642-04874-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Ahmed E. Hassan |
Predicting faults using the complexity of code changes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSE ![In: 31st International Conference on Software Engineering, ICSE 2009, May 16-24, 2009, Vancouver, Canada, Proceedings, pp. 78-88, 2009, IEEE, 978-1-4244-3452-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Safeeullah Soomro, Franz Wotawa |
Detect and Localize Faults in Alias-Free Programs Using Specification Knowledge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEA/AIE ![In: Next-Generation Applied Intelligence, 22nd International Conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems, IEA/AIE 2009, Tainan, Taiwan, June 24-27, 2009. Proceedings, pp. 379-388, 2009, Springer, 978-3-642-02567-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Irith Pomeranz, Sudhakar M. Reddy |
Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(1), pp. 98-107, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | M. Ümit Uyar, Samrat S. Batth, Yu Wang 0012, Mariusz A. Fecko |
Algorithms for Modeling a Class of Single Timing Faults in Communication Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(2), pp. 274-288, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Finite State Machine (FSM), Extended Finite State Machine (EFSM), Timed EFSM, Fault Modeling, Conformance Testing, Timers |
21 | Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy |
On Complete Functional Broadside Tests for Transition Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3), pp. 583-587, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Piotr Jantos, Damian Grzechca, Tomasz Golonek, Jerzy Rutkowski |
The Influence of Global Parametric Faults on Analogue Electronic Circuits Time Domain Response Features. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, pp. 299-303, 2008, IEEE Computer Society, 978-1-4244-2276-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Lingfu Xie, Du Xu, Qing Yao, Lei Song |
A New Fault-Tolerant Wormhole Routing Scheme in Tori with Convex Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HASE ![In: 11th IEEE High Assurance Systems Engineering Symposium, HASE 2008, Nanjing, China, December 3 - 5, 2008, pp. 467-470, 2008, IEEE Computer Society, 978-0-7695-3482-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Miao Jiang 0002, Mohammad Ahmad Munawar, Thomas Reidemeister, Paul A. S. Ward |
Detection and Diagnosis of Recurrent Faults in Software Systems by Invariant Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HASE ![In: 11th IEEE High Assurance Systems Engineering Symposium, HASE 2008, Nanjing, China, December 3 - 5, 2008, pp. 323-332, 2008, IEEE Computer Society, 978-0-7695-3482-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Jaymie Strecker, Atif M. Memon |
Relationships between Test Suites, Faults, and Fault Detection in GUI Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICST ![In: First International Conference on Software Testing, Verification, and Validation, ICST 2008, Lillehammer, Norway, April 9-11, 2008, pp. 12-21, 2008, IEEE Computer Society, 978-0-7695-3127-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Ing-Xiang Chen, Cheng-Zen Yang, Ting-Kun Lu, Hojun Jaygarl |
Implicit Social Network Model for Predicting and Tracking the Location of Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPSAC ![In: Proceedings of the 32nd Annual IEEE International Computer Software and Applications Conference, COMPSAC 2008, 28 July - 1 August 2008, Turku, Finland, pp. 136-143, 2008, IEEE Computer Society, 978-0-7695-3262-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
bug report managing system (BRMS), implicit social network analysis, PageRank, bug prediction |
21 | Jon Stearley, Adam J. Oliner |
Bad Words: Finding Faults in Spirit's Syslogs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCGRID ![In: 8th IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2008), 19-22 May 2008, Lyon, France, pp. 765-770, 2008, IEEE Computer Society, 978-0-7695-3156-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Claudomir Cardoso, Yomara Pires, Jefferson Morais, Aldebaro Klautau |
Hierarchical Agglomerative Clustering of Short-Circuit Faults in Transmission Lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBRN ![In: 10th Brazilian Symposium on Neural Networks (SBRN 2008), Salvador, Bahia, Brazil, October 26-30, 2008, pp. 87-92, 2008, IEEE Computer Society, 978-0-7695-3361-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal |
Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 329-335, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Diagnosis, ATPG, Fault Model, Fault Collapsing, Implication Graph |
21 | Xiangyu Zhang 0001, Neelam Gupta, Rajiv Gupta 0001 |
A study of effectiveness of dynamic slicing in locating real faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Empir. Softw. Eng. ![In: Empir. Softw. Eng. 12(2), pp. 143-160, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Full slicing, Exploring slices, Fault location, Dynamic program slicing, Data slicing |
21 | Crineu Tres, Leandro Buss Becker, Edgar Nett |
Real-Time Tasks Scheduling with Value Control to Predict Timing Faults During Overload. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISORC ![In: Tenth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2007), 7-9 May 2007, Santorini Island, Greece, pp. 354-358, 2007, IEEE Computer Society, 0-7695-2765-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Marta Capiluppi, Manfred Morari |
Networks of Hybrid Systems: Connections Faults Modelling and Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HSCC ![In: Hybrid Systems: Computation and Control, 10th International Workshop, HSCC 2007, Pisa, Italy, April 3-5, 2007, Proceedings, pp. 660-663, 2007, Springer, 978-3-540-71492-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Shuhua Xu, Benxiong Huang, Yuchun Huang |
Classification and Diagnosis of Mechanical Faults Using the RBF Network Based on the Local Bispectra. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (3) ![In: Advances in Neural Networks - ISNN 2007, 4th International Symposium on Neural Networks, ISNN 2007, Nanjing, China, June 3-7, 2007, Proceedings, Part III, pp. 626-632, 2007, Springer, 978-3-540-72394-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Ching-Wen Chen |
Design schemes of dynamic rerouting networks with destination tag routing for tolerating faults and preventing collisions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 38(3), pp. 307-326, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Destination tag routing, Fault tolerance, Performance, Parallel computing, Multistage interconnection network (MIN), Collision, Dynamic rerouting |
21 | Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee 0001, Jwu E. Chen |
IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2513-2525, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Kalpesh Kapoor |
Formal Analysis of Coupling Hypothesis for Logical Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Innov. Syst. Softw. Eng. ![In: Innov. Syst. Softw. Eng. 2(2), pp. 80-87, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Logical fault, Software testing, Mutation testing, Fault-based testing, Boolean specification |
21 | Nektarios Kranitis, Andreas Merentitis, Nikolaos Laoutaris, George Theodorou, Antonis M. Paschalis, Dimitris Gizopoulos, Constantin Halatsis |
Optimal periodic testing of intermittent faults in embedded pipelined processor applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 65-70, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Yoshihiro Nakaminami, Hirotsugu Kakugawa, Toshimitsu Masuzawa |
An advanced performance analysis of self-stabilizing protocols: stabilization time with transient faults during convergence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato |
Effective Post-BIST Fault Diagnosis for Multiple Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 401-109, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian |
Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 120-127, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Jais Abraham, Uday Goel, Arun Kumar |
Multi-Cycle Sensitizable Transition Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 306-313, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Stefan Dobrev, Rastislav Kralovic, Richard Královic, Nicola Santoro |
On Fractional Dynamic Faults with Threshold. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIROCCO ![In: Structural Information and Communication Complexity, 13th International Colloquium, SIROCCO 2006, Chester, UK, July 2-5, 2006, Proceedings, pp. 197-211, 2006, Springer, 3-540-35474-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Mikhail Nesterenko, Sébastien Tixeuil |
Discovering Network Topology in the Presence of Byzantine Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIROCCO ![In: Structural Information and Communication Complexity, 13th International Colloquium, SIROCCO 2006, Chester, UK, July 2-5, 2006, Proceedings, pp. 212-226, 2006, Springer, 3-540-35474-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Philipp Peti, Roman Obermaisser, Harald Paulitsch |
Investigating Connector Faults in the Time-Triggered Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETFA ![In: Proceedings of 11th IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2006, September 20-22, 2006, Diplomat Hotel Prague, Czech Republic, pp. 887-896, 2006, IEEE, 0-7803-9758-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Bartosz Sokol, S. V. Yarmolik |
Address Sequences for March Tests to Detect Pattern Sensitive Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 354-360, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Bogdan Tomoyuki Nassu, Takashi Nanya |
A Scenario of Tolerating Interaction Faults Between Otherwise Correct Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 18-20 December, 2006, University of California, Riverside, USA, pp. 371-372, 2006, IEEE Computer Society, 0-7695-2724-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Huawei Li 0001, Xiaowei Li 0001 |
Selection of Crosstalk-Induced Faults in Enhanced Delay Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(2), pp. 181-195, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
automatic test pattern generation (ATPG), crosstalk, delay test, critical paths |
21 | Viraj Kumar, Mahesh Viswanathan 0001 |
Conformance testing in the presence of multiple faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SODA ![In: Proceedings of the Sixteenth Annual ACM-SIAM Symposium on Discrete Algorithms, SODA 2005, Vancouver, British Columbia, Canada, January 23-25, 2005, pp. 1136-1145, 2005, SIAM, 0-89871-585-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
21 | Assaf Harel, Eliezer Kantorowitz |
Estimating the Number of Faults Remaining in Software Code Documents Inspected with Iterative Code Reviews. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SwSTE ![In: 2005 IEEE International Conference on Software - Science, Technology and Engineering (SwSTE 2005), 22-23 February 2005, Herzelia, Israel, pp. 151-160, 2005, IEEE Computer Society, 0-7695-2335-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Gabriela Jacques-Silva, Roberto Jung Drebes, Taisy Silva Weber, Eliane Martins |
Injecting Communication Faults to Experimentally Validate Java Distributed Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSADS ![In: Advanced Distributed Systems: 5th International School and Symposium, ISSADS 2005, Guadalajara, Mexico, January 24-28, 2005, Revised Selected Papers, pp. 235-245, 2005, Springer, 3-540-28063-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Gerald Steinbauer, Martin Mörth, Franz Wotawa |
Real-Time Diagnosis and Repair of Faults of Robot Control Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RoboCup ![In: RoboCup 2005: Robot Soccer World Cup IX, pp. 13-23, 2005, Springer, 3-540-35437-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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