Search results for "BIST"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
22	Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Test Vector Inhibiting Technique for Low Energy BIST Design.	VTS	1999	DBLP DOI BibTeX RDF
22	Sassan Tabatabaei, André Ivanov	A Current Integrator for BIST of Mixed-Signal ICs.	VTS	1999	DBLP DOI BibTeX RDF
22	Piero Olivo, Marcello Dalpasso	A Bist Scheme for Non-Volatile Memories.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	off-line testing, built-in self-test, signature analysis, non-volatile memories
22	Vyacheslav N. Yarmolik, Sybille Hellebrand, Hans-Joachim Wunderlich	Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs.	DATE	1998	DBLP DOI BibTeX RDF
22	Cheng-Wen Wu	Testing Embedded Memories: Is BIST the Ultimate Solution?	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
22	C. P. Ravikumar, N. Satya Prasad	Evaluating BIST Architectures for Low Power.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
22	Christophe Fagot, Olivier Gascuel, Patrick Girard 0001, Christian Landrault	A Ring Architecture Strategy for BIST Test Pattern Generation.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
22	Vladimir Castro Alves, Felipe M. G. França, Edson do Prado Granja	A BIST Scheme for Asynchronous Logic.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
22	Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel	A BIST Structure to Test Delay Faults in a Scan Environment.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
22	Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian	A distributed BIST technique for diagnosis of MCM interconnections.	ITC	1998	DBLP DOI BibTeX RDF
22	Chauchin Su, Shung-Won Jeng, Yue-Tsang Chen	Boundary scan BIST methodology for reconfigurable systems.	ITC	1998	DBLP DOI BibTeX RDF
22	Mehrdad Nourani, Christos A. Papachristou	Structural BIST insertion using behavioral test analysis.	ED&TC	1997	DBLP DOI BibTeX RDF
22	Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik	A Hybrid Algorithm for Test Point Selection for Scan-Based BIST.	DAC	1997	DBLP DOI BibTeX RDF
22	Chih-Ang Chen, Sandeep K. Gupta	Design of efficient BIST test pattern generators for delay testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
22	Kowen Lai, Christos A. Papachristou	BIST Testability Enhancement of System Level Circuits : Experience with An Industrial Design.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
22	D. Lambidonis, André Ivanov, Vinod K. Agarwal	Fast signature computation for BIST linear compactors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
22	Jacob Savir	Shrinking wide compressors [BIST].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
22	Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan	ScanBist: A Multifrequency Scan-Based BIST Method.	IEEE Des. Test Comput.	1994	DBLP DOI BibTeX RDF
22	Dimitrios Kagaris, Spyros Tragoudas	Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
22	Sungju Park, Sheldon B. Akers	Parity bit calculation and test signal compaction for BIST applications.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	parity bit, test response compression, Built-in self-test, pseudo-exhaustive tests
22	Andrzej Krasniewski, Slawomir Pilarski	Circular self-test path: a low-cost BIST technique for VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
20	Brendan Mullane, Ciaran MacNamee, Vincent O'Brien, Thomas Fleischmann	An on-chip solution for static ADC test and measurement.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	ADC-BiST, code histogram, linearity measurements, test, system-on-chip, analog to digital converter
20	Scott Davidson 0001	The commonality of vector generation techniques.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	output compression, non-fault-directed test, semi-fault-directed test, ATPG, test compression, full scan, vector generation, logic BIST
20	Apurva Mishra, Mani Soma	A Time-Domain Method for Pseudo-Spectral Characterization.	VTS	2008	DBLP DOI BibTeX RDF	bist, analog test, mixed-signal test, fft
20	Rei-Fu Huang, Chao-Hsun Chen, Cheng-Wen Wu	Economic Aspects of Memory Built-in Self-Repair.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	BIRA, BIST, yield, overhead, economic models, BISR, redundancy analysis, built-in self-repair
20	Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor	Opens and Delay Faults in CMOS RAM Address Decoders.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	address decoder delay faults, addressing methods, BIST, DFT, Memory testing, open defects
20	Hani Rizk, Christos A. Papachristou, Francis G. Wolff	A Self Test Program Design Technique for Embedded DSP Cores.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	self test programs, pseudorandom BIST, LSFR, DSP, ATPG
20	Markus Seuring	Combining Scan Test and Built-in Self Test.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	MBIST, BIST, scan test, production test, stress test
20	Kentaroh Katoh, Hideo Ito	Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices.	ETS	2006	DBLP DOI BibTeX RDF	Coarse Grained Dynamically Reconfigurable Devices, DRP, BIST(Built-In Self Test), PE, DFT
20	Kang Yi, Kyeong-Hoon Jung, Shih-Yang Cheng, Young-Hwan Park, Fadi J. Kurdahi, Ahmed M. Eltawil	Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Low power image filter design, Memory yield enhancement, Memory-error resilient design, H.264 codec, BIST, Embedded memory, BISR
20	R. Sanahuja, Victor Barcons, Luz Balado, Joan Figueras	Testing Biquad Filters under Parametric Shifts Using X-Y Zoning.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	X-Y zoning, Lissajous curves, BIST, parametric testing
20	Libor Rufer, Salvador Mir, Emmanuel Simeu, C. Domingues	On-Chip Pseudorandom MEMS Testing.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	BIST, pseudorandom sequences, impulse response, MEMS testing
20	Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel	Implementing a Scheme for External Deterministic Self-Test.	VTS	2005	DBLP DOI BibTeX RDF	Deterministic self-test, external BIST, test data compression, test resource partitioning
20	Kanad Chakraborty	Testing and Reliability Techniques for High-Bandwidth Embedded RAMs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	multiport RAM, BIST (built-in self-test), BISR (built-in self-repair), column-multiplexed addressing, fault tolerance, reliability, bandwidth
20	Hao-Yung Lo, Hsiu-Feng Lin, Chichyang Chen, Jenshiuh Liu, Chia-Cheng Liu	Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	generator, BIST, computer arithmetic, polynomials, VLSI design, multiplication, division
20	Jin-Fu Li 0001, Ruey-Shing Tzeng, Cheng-Wen Wu	Testing and Diagnosis Methodologies for Embedded Content Addressable Memories.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	march test algorithm, memory diagnostics, BIST, memory testing, CAM
20	Martin John Burbidge, Jim Tijou, Andrew Richardson 0001	Techniques for Automatic On Chip Closed Loop Transfer Function Monitoring For Embedded Charge Pump Phase Locked Loops.	DATE	2003	DBLP DOI BibTeX RDF	CP-PLL, TEST, DfT, BIST, PLL
20	Shiyi Xu	Build-In-Self-Test for Software.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	Software Testing, Design for Testability, Build-In-Self-Test (BIST)
20	Mohammad A. Naal, Emmanuel Simeu, Salvador Mir	On-Line Testable Decimation Filter Design for AMS Systems.	IOLTS	2003	DBLP DOI BibTeX RDF	non-concurrent, semi-concurrent, SigmaDelta, decimation filters, analogue BIST, on-line testing
20	Jin-Fu Li 0001, Ruey-Shing Tzeng, Cheng-Wen Wu	Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	Hamming syndrome, memory diagnostics, data compression, built-in self-test (BIST), system-on-chip, memory testing, Huffman code, March test
20	Douglas Kay, Sung Chung, Samiha Mourad	Embedded test control schemes for compression in SOCs.	DAC	2002	DBLP DOI BibTeX RDF	test resource allocation, data compression, BIST
20	Arnaud Virazel, René David, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch	Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	non-robust test, BIST, random testing, delay testing, robust test
20	Anna Maria Brosa, Joan Figueras	Digital Signature Proposal for Mixed-Signal Circuits.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	BIST, analog test, mixed-signal test
20	Hans G. Kerkhoff, Han Speek, M. Shashani, Manoj Sachdev	Design for Delay Testability in High-Speed Digital ICs.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	BIST, delay-fault testing, design for delay testability, high-speed testing
20	Paulo F. Flores, Horácio C. Neto, João P. Marques Silva	An exact solution to the minimum size test pattern problem.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	propositional satisfiability (SAT), verification and test, built-in self-test (BIST), Automatic test pattern generation (ATPG), integer linear programming (ILP)
20	Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.	A New Approach to Design Reliable Real-Time Speech Recognition Systems.	IOLTW	2001	DBLP DOI BibTeX RDF	HW-SW Codesign, Digital Signal Processing - DSP, Speech-Recognition Systems, Fault-Tolerance Techniques, Transparent BIST, Performance Degradation, Area overhead
20	Kelly A. Ockunzzi, Christos A. Papachristou	Breaking Correlation to Improve Testability.	VTS	2001	DBLP DOI BibTeX RDF	BIST, DFT, Test Synthesis
20	Ugur Kalay, Douglas V. Hall, Marek A. Perkowski	A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	AND-EXOR realizations, Reed-Muller expressions, single stuck-at fault model, easily testable combinational networks, self-testable circuits, Built-in Self-Test (BIST), test pattern generation, Design for Testing (DFT), Universal test set
20	Sying-Jyan Wang, Chen-Jung Wei	Efficient built-in self-test algorithm for memory.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	built-in self-test algorithm, built-in self test, BIST, DRAM, test patterns, pseudorandom testing, coupling faults, DRAM chips
20	Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy	Fsimac: a fault simulator for asynchronous sequential circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits
20	Alfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni	A Family of Self-Repair SRAM Cores.	IOLTW	2000	DBLP DOI BibTeX RDF	Memory Self-Repair, Memory BIST, BISR
20	Patrick Girard 0001	Low Power Testing of VLSI Circuits: Problems and Solutions.	ISQED	2000	DBLP DOI BibTeX RDF	Test, Low Power, ATPG, BIST, Low Energy
20	Jeongjin Roh, Jacob A. Abraham	A Comprehensive TDM Comparator Scheme for Effective Analysis of Oscillation-Based Test.	VTS	2000	DBLP DOI BibTeX RDF	oscillation test, BIST, signature, analog, time-division multiplexing, comparator, mixed-signal
20	Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar	Built-in Self Test Based on Multiple On-Chip Signature Checking.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	multiple signature comparison testing, BIST, aliasing probability
20	Marco Brazzarola, Franco Fummi	Power Characterization of LFSRs.	DFT	1999	DBLP DOI BibTeX RDF	BIST, Power consumption, LFSR
20	Sujit Dey, Anand Raghunathan, Kenneth D. Wagner	Design for Testability Techniques at the Behavioral and Register-Transfer Levels.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	behavioral synthesis for testability, behavioral synthesis for BIST, high-level test generation, RTL synthesis for testability, design for testability
20	Kelly A. Ockunzzi, Christos A. Papachristou	Testability Enhancement for Control-Flow Intensive Behaviors.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	behavioral testability analysis and insertion, BIST, test synthesis
20	Joan Carletta, Christos A. Papachristou	Behavioral Testability Insertion for Datapath/Controller Circuits.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	behavioral testability analysis, BIST, test synthesis
20	Gang-Min Park, Hoon Chang	An extended march test algorithm for embedded memories.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	efficient test algorithm, BIST architecture, neighborhood pattern sensitive fault, background data, word-oriented memory testing, extended march test algorithm, stuck-at fault, transition fault, embedded memories, integrated memory circuits, coupling fault
20	Toshinobu Ono, Kazuo Wakui, Hitoshi Hikima, Yoshiyuki Nakamura, Masaaki Yoshida	Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	core test, design-for-testability, BIST, scan, boundary scan, test bus
20	Andrzej Hlawiczka, Michael Gössel, Egor S. Sogomonyan	A linear code-preserving signature analyzer COPMISR.	VTS	1997	DBLP DOI BibTeX RDF	linear separable code, code preserving multi-input signature register, COPMISR, concurrent checking, parity code, group -parity code, BIST, linear codes, Hamming code, duplication code, XOR-gate, signature analyzer, on-line error detection
20	Franco Fummi, Donatella Sciuto	Implicit test pattern generation constrained to cellular automata embedding.	VTS	1997	DBLP DOI BibTeX RDF	implicit test pattern generation, cellular automata embedding, test sequence identification, autonomous finite state machine, off-line self-testable circuit, BIST strategy, deterministic test sequences, MCNC benchmarks, controller, built-in self test, stuck-at faults, ASIC design, circuit under test
20	Vladimir Castro Alves, A. Ribeiro Antunes, Meryem Marzouki	A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	high-level synthesis for testability, systematic flexible synthesis, testability methodology, industrial tools, pragmatic synthesis, AMICAL synthesis, programmable test pattern generation, BUS-based circuit, embedded test paths, high level synthesis, design for testability, BIST, automatic generation, data path, scan path
20	Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo	An Efficient PRPG Strategy By Utilizing Essential Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	PRPG, essential fault, multiple polynomial, Gauss elimination, pseudorandom test pattern, multivariable linear equation, deterministic test set, random pattern resistant circuit, don't care value, intelligent heuristic, ISCAS-85 benchmark, ISCAS-89 benchmark, built-in self test, BIST, fault coverage, LFSR, test length, hardware overhead, multiple seed
20	Jacob Savir	Generator choices for delay test.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST based delay test, generator choices, delay test vector generator, nonscan designs, transition test, skewed-load delay test, shift dependency, digital logic circuits, performance, VLSI, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, automatic testing, flexibility, linear feedback shift register, cost, shift registers, scan designs, boundary scan testing, test vectors, timing requirement, pseudo-random test
20	Mitrajit Chatterjee, Dhiraj K. Pradhan	A novel pattern generator for near-perfect fault-coverage.	VTS	1995	DBLP DOI BibTeX RDF	near-perfect fault-coverage, onchip BIST, GLFSR, logic mapping technique, weighted pattern technique, logic testing, built-in self test, integrated circuit testing, design methodology, combinational circuits, automatic testing, integrated logic circuits, shift registers, combinational logic, digital integrated circuits, pattern generator, single stuck-at fault
20	Xinli Gu	RT level testability-driven partitioning.	VTS	1995	DBLP DOI BibTeX RDF	testability-driven partitioning, RT level designs, hard-to-test points, testability analysis algorithm, normal mode, design function, test mode, acyclic partition, BIST technique, fault diagnosis, logic testing, built-in self test, integrated circuit testing, design for testability, ATPG, automatic testing, logic CAD, fault coverage, logic partitioning, test application time, data path, testability measurements, DFT techniques
20	Shridhar K. Mukund, Edward J. McCluskey, T. R. N. Rao	An apparatus for pseudo-deterministic testing.	VTS	1995	DBLP DOI BibTeX RDF	pseudo-deterministic testing, deterministic patterns, at-speed BIST, arbitrary length shift register, care bits, tap configurations, test segments, don't care bits, random pattern resistant faults, interconnected logic blocks, logic testing, built-in self test, integrated circuit testing, LFSR, shift registers, computational efficiency, test vector, pseudo-random sequences
20	Nazar S. Haider, Nick Kanopoulos	Efficient board interconnect testing using the split boundary scan register.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	IEEE std. 1149.1-1990, split boundary scan register, BIST, boundary scan
16	G. Seetharaman, B. Venkataramani	Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	FPGA, pipelining, SOC, CORDIC, wave-pipelining, DAA
16	Wimol San-Um, Masayoshi Tachibana	Simultaneous impulse stimulation and response sampling technique for built-in self test of linear analog integrated circuits.	SBCCI	2009	DBLP DOI BibTeX RDF	impulse stimulation, linear analog integrated circuits, response sampling technique, built-in self test
16	Shantanu Dutt, Vinay Verma, Vishal Suthar	Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
16	Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir	C-testable bit parallel multipliers over GF(2m).	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	testing, cryptography, built-in self-test, digital signal processing, polynomials, VLSI design, stuck-at fault, TPG, fault, multiplier, Galois field, error control code, C-testable
16	Tian Chen, Huaguo Liang, Minsheng Zhang, Wei Wang 0310	A Scheme of Test Pattern Generation Based on Reseeding of Segment-Fixing Counter.	ICYCS	2008	DBLP DOI BibTeX RDF
16	Aman Kokrady, C. P. Ravikumar, Nitin Chandrachoodan	Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models.	VLSI Design	2008	DBLP DOI BibTeX RDF
16	Rupsa Chakraborty, Dipanwita Roy Chowdhury	coreBIST: A Cellular Automata Based Core for Self Testing System-on-Chips.	ACRI	2008	DBLP DOI BibTeX RDF	Response-Analyzer, Built-in self-test, System-on-Chip, Cellular Automata, Test-Pattern-Generator
16	Jen-Chieh Yeh, Kuo-Liang Cheng, Yung-Fa Chou, Cheng-Wen Wu	Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
16	Marcelo Negreiros, Adão Antônio de Souza Jr., Luigi Carro, Altamiro Amadeu Susin	RF Digital Signal Generation Beyond Nyquist.	VTS	2007	DBLP DOI BibTeX RDF
16	Foster F. Dai, Charles E. Stroud, Dayu Yang	Automatic linearity and frequency response tests with built-in pattern generator and analyzer.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
16	Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy 0001	A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
16	Gildas Léger, Adoración Rueda	Experimental Validation of a Fully Digital BISTfor Cascaded Sigma Delta Modulators.	ETS	2006	DBLP DOI BibTeX RDF
16	Marcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas 0001, Jorge Semião, Isabel C. Teixeira, João Paulo Teixeira 0001	Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes.	IOLTS	2006	DBLP DOI BibTeX RDF
16	Shyue-Kung Lu, Ting-Yu Chen, Wei-Yuan Liu	Efficient Built-In Self-Test Schemes for Video Coding Cores: a Case Study on DCT/IDCT Circuits.	PRDC	2006	DBLP DOI BibTeX RDF
16	Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey	Optimized reseeding by seed ordering and encoding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
16	Cheng-Wen Wu	SOC Testing Methodology and Practice.	DATE	2005	DBLP DOI BibTeX RDF
16	Janusz Rajski	Embedded Test Technology - Brief History, Current Status, and Future Directions.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
16	Biplab K. Sikdar, Arijit Sarkar, Samir Roy, Debesh K. Das	Synthesis of Testable Finite State Machine Through Decomposition.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	emitability, FSM state encoding, decomposition, reachability, degree-of-freedom
16	Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng	Hardware Ef.cient LBISTWith Complementary Weights.	ICCD	2005	DBLP DOI BibTeX RDF
16	João Goes, Nuno Paulino 0002, Guiomar Evans	On-chip built-in self-test of video-rate ADCs using Gaussian noise.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
16	Kuen-Jong Lee, Chia-Yi Chu, Yu-Ting Hong	An embedded processor based SOC test platform.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
16	Mohammad Tehranipoor	Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure.	DFT	2005	DBLP DOI BibTeX RDF
16	Aditya Sankar Medury, Ingvar Carlson, Atila Alvandpour, John Stensby	Structural Fault Diagnosis in Charge-Pump Based Phase-Locked Loops.	VLSI Design	2005	DBLP DOI BibTeX RDF
16	B. K. S. V. L. Varaprasad, Lalit M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal	A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
16	M. Amir Abas, Gordon Russell 0002, D. J. Kinniment	Design of Sub-10-Picoseconds On-Chip Time Measurement Circuit.	DATE	2004	DBLP DOI BibTeX RDF
16	Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang	A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
16	Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu	A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories.	MTDT	2004	DBLP DOI BibTeX RDF
16	Zhongjun Yu, Degang Chen 0001, Randall L. Geiger	Accurate testing of ADC's spectral performance using imprecise sinusoidal excitations.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
16	Thomas O'Shea, Ian Andrew Grout	A Matlab Based On-Chip Signal Generation and Analysis Environment for Mixed Signal Circuits.	IOLTS	2004	DBLP DOI BibTeX RDF
16	Charles E. Stroud, John Sunwoo, Srinivas M. Garimella, Jonathan Harris	Built-In Self-Test for System-on-Chip: A Case Study.	ITC	2004	DBLP DOI BibTeX RDF
16	Heinz Mattes, Claus Dworski, Sebastian Sattler	Controlled Sine Wave Fitting for ADC Test.	ITC	2004	DBLP DOI BibTeX RDF