Search results for "FPGA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Joydip Das, Steven J. E. Wilton	An analytical model relating FPGA architecture parameters to routability.	FPGA	2011	DBLP DOI BibTeX RDF
1	Eric S. Chung, James C. Hoe, Ken Mai	CoRAM: an in-fabric memory architecture for FPGA-based computing.	FPGA	2011	DBLP DOI BibTeX RDF
1	Kan Huang, Junlin Lu, Jiufeng Pang, Yansong Zheng, Hao Li, Dong Tong 0001, Xu Cheng 0001	FPGA prototyping of an amba-based windows-compatible SoC.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, microsoft windows, amba, x86
1	Charles Eric LaForest, J. Gregory Steffan	Efficient multi-ported memories for FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, parallel, memory, multi-port
1	Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu 0001, Xu Cheng 0001, Jason Cong	Bit-level optimization for high-level synthesis and FPGA-based acceleration.	FPGA	2010	DBLP DOI BibTeX RDF	bit-level optimization, fpga, high-level synthesis
1	Marcus Dutton, David C. Keezer	An architecture for graphics processing in an FPGA (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, scalability, architecture, flexibility, gpu
1	Jason Lee, Lesley Shannon	Predicting the performance of application-specific NoCs implemented on FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	performance, FPGAs, topologies, heterogeneous, NoCs, homogeneous, application-specific, routability
1	Zhanpeng Jin, Richard Neil Pittman, Alessandro Forin	Reconfigurable custom floating-point instructions (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	emips, reconfigurable, extension, floating-point, partial reconfiguration
1	Yangyang Pan, Tong Zhang 0002	DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dram-based fpga, memory stacking, 3d integration
1	Dharmendra P. Gupta, Paul Chow	Acceleration of an analytical approach to collateralized debt obligation pricing.	FPGA	2010	DBLP DOI BibTeX RDF	cdo, financial simulation
1	Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev	A 3d-audio reconfigurable processor.	FPGA	2010	DBLP DOI BibTeX RDF	reconfigurable computing, communication systems, beamforming, 3d-audio, wave field synthesis
1	Chun Zhang, Yu Hu 0002, Lingli Wang, Lei He 0001, Jiarong Tong	Building a faster boolean matcher using bloom filter.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, SAT, bloom filter, boolean matching, re-synthesis
1	Jonathan M. Johnson, Michael J. Wirthlin	Voter insertion algorithms for FPGA designs using triple modular redundancy.	FPGA	2010	DBLP DOI BibTeX RDF	scc, tmr, voter insertion, fpga, algorithm, reliability, synchronization
1	Shaoshan Liu, Richard Neil Pittman, Alessandro Forin	Minimizing partial reconfiguration overhead with fully streaming DMA engines and intelligent ICAP controller (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, partial reconfiguration
1	Doris Chen, Deshanand P. Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz	A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	mtbf, fpga, metastability
1	Mingjie Lin, Yaling Ma	Scalable architecture for programmable quantum gate array (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	reconfigurable, computing, quantum
1	Kyle Rupnow, Jacob Adriaens, Wenyin Fu, Katherine Compton	Accurately evaluating application performance in simulated hybrid multi-tasking systems.	FPGA	2010	DBLP DOI BibTeX RDF	performance evaluation, hybrid systems, heterogeneous systems, full system simulation, multi-tasking systems
1	Deepak Unnikrishnan, Ramakrishna Vadlamani, Yong Liao, Abhishek Dwaraki, Jérémie Crenne, Lixin Gao 0001, Russell Tessier	Scalable network virtualization using FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, virtual networks
1	Huimin Bian, Andrew C. Ling, Alexander Choong, Jianwen Zhu	Towards scalable placement for FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, convex optimization, quadratic placement, bipartite matching
1	Zefu Dai, Nick Ni, Jianwen Zhu	A 1 cycle-per-byte XML parsing accelerator.	FPGA	2010	DBLP DOI BibTeX RDF	bart, schema validation, string comparison, xml parsing, ethernet, bloom filter, dom, tree construction
1	Diana Göhringer, Michael Hübner 0001, Michael Benz, Jürgen Becker 0001	A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	designflow, toolchain, fpga, partitioning, reconfigurable computing, mpsoc, hardware/software co-design
1	Sunwoo Kim, Won Woo Ro	FPGA implementation of highly parallelized decoder logic for network coding (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, network coding, fpga implementation, galois field arithmetic
1	Chen Chen 0018, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra	Efficient FPGAs using nanoelectromechanical relays.	FPGA	2010	DBLP DOI BibTeX RDF	CMOS-NEM FPGA, nanoelectromechanical relay
1	Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita	High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dopant-segregated schottky transistor, nonvolatile configurable memory
1	Donglai Dai, Aniruddha S. Vaidya, Roy Saharoy, Seungjoon Park, Dongkook Park, Hariharan L. Thantry, Ralf Plate, Elmar Maas, Akhilesh Kumar, Mani Azimi	FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, routing algorithm, on-chip interconnect, router architecture
1	Yi Shan, Bo Wang 0067, Jing Yan, Yu Wang 0002, Ningyi Xu, Huazhong Yang	FPMR: MapReduce framework on FPGA.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA framework, RankBoost, MapReduce
1	Jan R. Frigo, Eric Y. Raby, Sean M. Brennan, Christophe Wolinski, Charles Wagner, François Charot, Edward Rosten, Vinod Kulathumani	Energy efficient sensor node implementations.	FPGA	2010	DBLP DOI BibTeX RDF	distributed sensor network (dsn), seismic, fpga, video, acoustic, vehicle classification, dsp
1	Edward A. Stott, Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung	Degradation in FPGAs: measurement and modelling.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, self test
1	Shreesha Srinath, Katherine Compton	Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks.	FPGA	2010	DBLP DOI BibTeX RDF	asymmetric multipliers, composable multipliers, multiplier design
1	Sunita Chandrasekaran, Shilpa Shanbagh, Douglas L. Maskell	A dependency graph based methodology for parallelizing HLL applications on FPGA (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpgas, bioinformatics, sequence alignment, data dependency analysis, smith-waterman algorithm
1	Huandong Wang, Xiang Gao, Yunji Chen, Dan Tang, Weiwu Hu	A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	loongson, multi-fpga, fpga, evaluation, verification, emulation
1	Gregory Lucas, Chen Dong 0003, Deming Chen	Variation-aware placement for FPGAs with multi-cycle statistical timing analysis.	FPGA	2010	DBLP DOI BibTeX RDF	multi-cycle, variation-aware, fpga, placement, ssta, statistical static timing analysis
1	Hao Wang, Shi Pu, Gabriel Knezek, Jyh-Charn Liu	A modular NFA architecture for regular expression matching.	FPGA	2010	DBLP DOI BibTeX RDF	character class constraint repetition, overlapped matching, FPGA, regular expression, NFA
1	Kenneth M. Zick, John P. Hayes	On-line sensing for healthier FPGA systems.	FPGA	2010	DBLP DOI BibTeX RDF	on-line sensing, physically-adaptive computing., fpgas, reliability, process variation, leakage, temperature, dynamic power, ring oscillator, static power, health management
1	Shaoshan Liu, Richard Neil Pittman, Alessandro Forin	Energy reduction with run-time partial reconfiguration (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, energy
1	Larkhoon Leem, James A. Weaver, Metha Jeeradit, James S. Harris Jr.	Nano-magnetic non-volatile CMOS circuits for nano-scale FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	spin-torque devices, fpga, spintronics
1	Chen Huang 0005, Frank Vahid	Server-side coprocessor updating for mobile devices with FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	coprocessing, fpgas, dynamic optimization, acceleration
1	Hoang Le, Yi-Hua E. Yang, Viktor K. Prasanna	Memory efficient string matching: a modular approach on FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	deep packet classification, fpga, packet filtering
1	Behzad Mahdavikhah, Ramin Mafi, Shahin Sirouspour, Nicola Nicolici	Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture.	FPGA	2010	DBLP DOI BibTeX RDF	conjugate gradient (CG), finite-element modeling (FEM), field-programmable gate array (FPGA)
1	Brahim Al Farisi, Karel Bruneel, Harald Devos, Dirk Stroobandt	Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	parameterizable configurations, tmap, fpga, reconfigurable computing, run-time reconfiguration, srl, icap
1	Mingjie Lin, Ilia A. Lebedev, John Wawrzynek	High-throughput bayesian computing machine with reconfigurable hardware.	FPGA	2010	DBLP DOI BibTeX RDF	reconfigurable hardware, bayesian computing
1	Jason Helge Anderson, Chirag Ravishankar	FPGA power reduction by guarded evaluation.	FPGA	2010	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, logic synthesis, technology mapping
1	Jing Yan, Ningyi Xu, Xiongfei Cai, Rui Gao, Yu Wang 0002, Rong Luo, Feng-Hsiung Hsu	LambdaRank acceleration for relevance ranking in web search engines (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	lambdarank algorithms
1	Alan Mishchenko, Robert K. Brayton, Stephen Jang	Global delay optimization using structural choices.	FPGA	2010	DBLP DOI BibTeX RDF	technology mpping, FPGA, interpolation, windowing, boolean satisfiability, logic optimization
1	Mike Brugge, Mohammed A. S. Khalid	Design and evaluation of a parameterizable NoC router for FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, architecture, system-on-chip, network-on-chip, design space exploration, router
1	Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu 0006, Kirill Minkovich, Bo Yuan, Yi Zou	Accelerating Monte Carlo based SSTA using FPGA.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, monte carlo, SSTA
1	Skyler Schneider, Daniel Y. Deng, Daniel Lo, Greg Malysa, G. Edward Suh	Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dynamic inspection, reconfigurable microprocessors, fpga
1	Shepard Siegel, Michael J. Wirthlin	FPGA-2010 pre-conference workshop on open-source for FPGA.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, open-source
1	Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003	Intel nehalem processor core made FPGA synthesizable.	FPGA	2010	DBLP DOI BibTeX RDF	intel nehalem, synthesizable core, fpga, emulator
1	Peter A. Jamieson, Kenneth B. Kent	Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, verilog hdl
1	Julien Lamoureux, Scott Miller, Mihai Sima	Fine-grained vs. coarse-grained shift-and-add arithmetic in FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	shift-and-add arithmetic, fpga, cordic, coarse-grained
1	Kristian Stevens, Henry Chen, Terry Filiba, Peter L. McMahon, Yun S. Song	Application of a reconfigurable computing cluster to ultra high throughput genome resequencing (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	genome resequencing, fpga, acceleration, reconfigurable logic
1	Kees A. Vissers, Devada Varma, Vinod Kathail, Jeff Bier, Don MacMillen, Joseph R. Cavallaro	Programming high performance signal processing systems in high level languages.	FPGA	2010	DBLP DOI BibTeX RDF	high level programming models, fpga, signal processing, dsp
1	Kuen Hung Tsoi, Wayne Luk	Axel: a heterogeneous cluster with FPGAs and GPUs.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, heterogeneous cluster
1	David L. Foster, Darrin M. Hanna	Maximizing area-constrained partial fault tolerance in reconfigurable logic.	FPGA	2010	DBLP DOI BibTeX RDF	area-constrained, FPGA
1	Marc-André Daigneault, Jean-Pierre David	Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	time-to-digital converter, vernier method, field programmable gate array, dynamic reconfiguration
1	Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita	Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	overclocking, timing error detection, timing error recovery, fpga
1	Mohammed Y. Niamat, Sowmya Panuganti, Tejas Raviraj	Modeling and simulation of nano quantum FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	nano, fpga, qca, quantum
1	Jirí Simsa, Satnam Singh	Designing hardware with dynamic memory abstraction.	FPGA	2010	DBLP DOI BibTeX RDF	c to gates, high-level synthesis, parallel execution, dynamic memory, bluespec
1	Yi-Hua E. Yang, Viktor K. Prasanna	High throughput and large capacity pipelined dynamic search tree on FPGA.	FPGA	2010	DBLP DOI BibTeX RDF	2-3 tree, in-place update, ip forwarding, pipelined tree, b-tree, dynamic update, incremental update, openflow
1	Jason Cong, Kirill Minkovich	LUT-based FPGA technology mapping for reliability (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	logic synthesis, error analysis, windowing, technology mapping, don't cares, fpga lookup table
1	Y. Hamid, Martin Langhammer	Multiplier architectures for FPGA double precision functions (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, floating point
1	Rahul Bhattacharya, Santosh Biswas, Siddhartha Mukhopadhyay	FPGA based chip emulation system for test development and verification of analog and mixed signal circuits (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	ams testing, concurrent test development, behavioral modeling
1	Taiga Takata, Yusuke Matsunaga	A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, technology mapping
1	Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain	Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, dynamic programming, systolic array, throughput optimization, recurrences
1	Zhimin Chen 0002, Richard Neil Pittman, Alessandro Forin	Combining multicore and reconfigurable instruction set extensions.	FPGA	2010	DBLP DOI BibTeX RDF	extensible microprocessors, reconfigurable instruction set extensions, embedded, multi-core
1	Peter Y. K. Cheung, John Wawrzynek (eds.)	Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010	FPGA	2010	DBLP DOI BibTeX RDF
1	Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton	The impact of interconnect architecture on via-programmed structured ASICs (VPSAs).	FPGA	2010	DBLP DOI BibTeX RDF	structured asics, via programmable fabric
1	Husain Parvez, Zied Marrakchi, Habib Mehrez	Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	asif, fpga, architecture, application specific, cad
1	Lei Chen 0010, Zhiquan Zhang, Zhiping Wen 0001	A novel BIST approach for testing input/output buffers in FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	i/o buffers, built-in self-test, fpga testing
1	Viktor Pus, Jan Korenek	Fast and scalable packet classification using perfect hash functions.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, sram, packet classification
1	Alastair M. Smith, Steven J. E. Wilton, Joydip Das	Wirelength modeling for homogeneous and heterogeneous FPGA architectural development.	FPGA	2009	DBLP DOI BibTeX RDF	fpga modeling, wirelength estimation, fpga, architecture design
1	Gaurav Mittal, David Zaretsky, Prithviraj Banerjee	Streaming implementation of a sequential decompression algorithm on an FPGA.	FPGA	2009	DBLP DOI BibTeX RDF	fix., fpga, system-on-chip, binary translation, hardware-software co-design, streaming architecture
1	Sayyed Arash Ostadzadeh, Roel Meeuws, Kamana Sigdel, Koen Bertels	A clustering framework for task partitioning based on function-level data usage analysis.	FPGA	2009	DBLP DOI BibTeX RDF	task clustering, reconfigurable computing, hardware/software co-design, heterogeneous multiprocessors
1	Mohammed A. S. Abdallah, Omar S. Elkeelany, Ali T. Alouani	Simultaneous multi-channel data acquisition with variable sampling frequencies using a scalable adaptive synchronous controller.	FPGA	2009	DBLP DOI BibTeX RDF	adc, sd card, fpga, real-time, multiplexing, data acquisition, fft
1	Like Yan, Gang Wang, Tianzhou Chen	The input-aware dynamic adaptation of area and performance for reconfigurable accelerator.	FPGA	2009	DBLP DOI BibTeX RDF	dynamic adaption, reconfigurable system, loop unrolling, loop accelerator
1	Raphael Rubin, André DeHon	Choose-your-own-adventure routing: lightweight load-time defect avoidance.	FPGA	2009	DBLP DOI BibTeX RDF	bitstream load, in-field repair, defect tolerance, alternatives, programmable interconnect
1	Süleyman Sirri Demirsoy, Martin Langhammer	Cholesky decomposition using fused datapath synthesis.	FPGA	2009	DBLP DOI BibTeX RDF	cholesky, fused datapath synthesis, fpga, floating-point
1	Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau	Measuring and modeling variabilityusing low-cost FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	variability
1	Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour	Towards automated ECOs in FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	pst, optimization, fpga, boolean satisfiability, resynthesis
1	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Soft vector processors vs FPGA custom hardware: measuring and reducing the gap.	FPGA	2009	DBLP DOI BibTeX RDF	eembc, soft, viram, fpga, adaptable, vector, data parallel, processor, simd
1	Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox	FPGA technology mapping with encoded libraries andstaged priority cuts.	FPGA	2009	DBLP DOI BibTeX RDF	priority cuts, fpga, synthesis, technology mapping
1	Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang	A comparison of via-programmable gate array logic cell circuits.	FPGA	2009	DBLP DOI BibTeX RDF	logic cell, via-programmable gate arrays
1	Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton	SmartOpt: an industrial strength framework for logic synthesis.	FPGA	2009	DBLP DOI BibTeX RDF	abc, blif, edge flow, smartopt, fpga, interface, technology mapping
1	Yanteng Sun, Peng Li 0031, Guochang Gu, Yuan Wen, Yuan Liu, Dong Liu	HMMer acceleration using systolic array based reconfigurable architecture.	FPGA	2009	DBLP DOI BibTeX RDF	reconfigurable., systolic array, acceleration, hmmer
1	Weirong Jiang, Viktor K. Prasanna	Large-scale wire-speed packet classification on FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, decision tree, pipeline, sram, packet classification
1	Dirk Koch, Christian Beckhoff, Jürgen Teich	A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, reconfiguration, communication architecture
1	Seunghun Jin, Dongkyun Kim, Thien Cong Pham, Jae Wook Jeon	FPGA implementation of real-time skin color detection with mean-based surface flattening.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, hardware design, skin detection
1	Zuo Wang, Feng Shi 0009, Qi Zuo, Weixing Ji, Mengxiao Liu	N-port memory mapping for LUT-based FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	logical-to-physical mapping, n-port memory, fpga, hierarchy
1	Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet	Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing
1	Claudio Favi, Edoardo Charbon	A 17ps time-to-digital converter implemented in 65nm FPGA technology.	FPGA	2009	DBLP DOI BibTeX RDF	65nm fpga, deep sub-nanosecond time resolution, high-speed readout, time-correlated instrumentation, time-to-digital converters, ultra-fast digital electronics, optical communications, tdc
1	Liu Ling, Neal Oliver, Bhushan Chitlur, Qigang Wang, Alvin Chen, Wenbo Shen, Zhihong Yu, Arthur Sheiman, Ian McCallum, Joseph Grecco, Henry Mitchel, Dong Liu, Prabhat Gupta	High-performance, energy-efficient platforms using in-socket FPGA accelerators.	FPGA	2009	DBLP DOI BibTeX RDF	in-socket accelerator, fpga, agility
1	David B. Thomas, Lee W. Howes, Wayne Luk	A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation.	FPGA	2009	DBLP DOI BibTeX RDF	mppa, fpga, monte-carlo, random numbers, gpu
1	Florian Dittmann 0001, Elmar Weber, Norma Montealegre	Implementation of the reconfiguration port scheduling on the erlangen slot machine.	FPGA	2009	DBLP DOI BibTeX RDF	erlangen slot machine, scheduling, fpgas, reconfiguration
1	Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck, Wendy McDougald, Don Dewitt	FPGA-based front-end electronics for positron emission tomography.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, localization, timing, positron emission tomography
1	Melina Demertzi, Pedro C. Diniz, Mary W. Hall, Anna C. Gilbert, Yi Wang	Computation reuse in domain-specific optimization of signal recognition.	FPGA	2009	DBLP DOI BibTeX RDF	computation reuse, signal recognition, fpga
1	Edward C. Lin, Rob A. Rutenbar	A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer.	FPGA	2009	DBLP DOI BibTeX RDF	in silico vox, fpga, speech recognition, dsp
1	Cristinel Ababei	Parallel placement for FPGAs revisited.	FPGA	2009	DBLP DOI BibTeX RDF	fpga placement, multithreading, parallel simulated annealing
1	David Sheldon, Frank Vahid	Making good points: application-specific pareto-point generation for design space exploration using statistical methods.	FPGA	2009	DBLP DOI BibTeX RDF	configurable platform, fpga, low-power, exploration, speedup, pruning, pareto-optimal, design of experiments
1	JIanDe Yu, Jinmei Lai	A novel minloop SB design to improve FPGA routability.	FPGA	2009	DBLP DOI BibTeX RDF	minimum-loop-size maximization method, minloop switch box, routing resources design, fpga

Publications at "FPGA"( http://dblp.L3S.de/Venues/FPGA )