Search results for "32nm"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
89	Stephen P. Kornachuk, Michael C. Smayling	New strategies for gridded physical design for 32nm technologies and beyond.	ISPD	2009	DBLP DOI BibTeX RDF	28nm, 32nm, 45nm, litho, rdr, placement, layout, physical design, manufacturability, lithography, standard cell, vlsi, drc, dfm
53	David Z. Pan, Stephen Renwick, Vivek Singh, Judy Huckabay	Nanolithography and CAD challenges for 32nm/22nm and beyond.	ICCAD	2008	DBLP DOI BibTeX RDF
53	Yiming Li 0005, Chih-Hong Hwang, Shao-Ming Yu	Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors.	International Conference on Computational Science (4)	2007	DBLP DOI BibTeX RDF	computational statistics, SRAM, modeling and simulation, FinFET
53	Samuel Rodríguez, Bruce L. Jacob	Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm).	ISLPED	2006	DBLP DOI BibTeX RDF	nanometer design, pipelined caches, cache design
53	Brian Swahn, Soha Hassoun	Gate sizing: finFETs vs 32nm bulk MOSFETs.	DAC	2006	DBLP DOI BibTeX RDF	gate sizing, thermal modeling, FinFET
38	Spandana Remarsu, Sandip Kundu	On process variation tolerant low cost thermal sensor design in 32nm CMOS technology.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	self compensating comparator, dithering, thermal sensor
38	Kelin J. Kuhn	CMOS scaling beyond 32nm: challenges and opportunities.	DAC	2009	DBLP DOI BibTeX RDF	high-k, CMOS, orientation, strain, metal-gate
31	Sani R. Nassif, Kevin J. Nowka	Physical design challenges beyond the 22nm node.	ISPD	2010	DBLP DOI BibTeX RDF	technology, scaling
31	Mehrtash Manoochehri, Alireza Ejlali, Seyed Ghassem Miremadi	Joint write policy and fault-tolerance mechanism selection for caches in DSM technologies: Energy-reliability trade-off.	ISQED	2009	DBLP DOI BibTeX RDF
31	David Z. Pan	Lithography friendly routing: from construct-by-correction to correct-by-construction.	SBCCI	2008	DBLP DOI BibTeX RDF	routing
31	Jin Ouyang, Yuan Xie 0001	Power optimization for FinFET-based circuits using genetic algorithms.	SoCC	2008	DBLP DOI BibTeX RDF
31	Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones	Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	reliable design, sensor network-on-chip, robust design
22	Yash Bahuguna, Ayush Sinha, Sahil Adhikari, Vinay Kumar	32nm CMOS Analog Circuit Implementation of STDP for SNNs.	ICCCNT	2023	DBLP DOI BibTeX RDF
22	Monica Gupta, Kirti Gupta, Neeta Pandey	Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm.	Microprocess. Microsystems	2021	DBLP DOI BibTeX RDF
22	Lionel Trojman, David Rivadeneira, Marco Villegas, Eliana Acurio, Marco Lanuzza, Luis-Miguel Procel, Ramiro Taco	RF-DC Multiplier for RF Energy Harvester based on 32nm and TFET technologies.	LASCAS	2021	DBLP DOI BibTeX RDF
22	Parmoon Seddighrad, Yorgos Palaskas, Hongtao Xu, Paolo Madoglio, Kailash Chandrashekar, David J. Allstot	Transformer-Combining Digital PA with Efficiency Peaking at 0, -6, and -12 dB Backoff in 32nm CMOS.	ISCAS	2020	DBLP DOI BibTeX RDF
22	Mir Muntasir Hossain, Satyendra N. Biswas	Analysis and Design of a 32nm FinFET Dynamic Latch Comparator.	CoRR	2019	DBLP BibTeX RDF
22	Jen-Chieh Hsueh, Vanessa H.-C. Chen, Jean-Olivier Plouchart	An ultra-high bandwidth sub-ranging ADC with programmable dynamic range in 32nm CMOS SOI.	MWSCAS	2017	DBLP DOI BibTeX RDF
22	Giane Ulloa, Vinicius Lucena, Cristina Meinhardt	Comparing 32nm full adder TMR and DTMR architectures.	ICECS	2017	DBLP DOI BibTeX RDF
22	William Y. Li, Hyung Seok Kim, Kailash Chandrashekar, Khoa Minh Nguyen, Ashoke Ravi	A 32nm, 0.65-10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O.	ISLPED	2017	DBLP DOI BibTeX RDF
22	Sen Tao, Naveen Verma, Ryan M. Corey, Andrew C. Singer	A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS.	ISCAS	2017	DBLP DOI BibTeX RDF
22	Sergey V. Rylov, Troy J. Beukema, Zeynep Toprak Deniz, Thomas Toifl, Yong Liu 0023, Ankur Agrawal, Peter Buchmann, Alexander V. Rylyakov, Michael P. Beakes, Benjamin D. Parker, Mounir Meghelli	3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI.	ISSCC	2016	DBLP DOI BibTeX RDF
22	Drew A. Hall, Jonathan S. Daniels, Bibiche M. Geuskens, Noureddine Tayebi, Grace M. Credo, David J. Liu, Handong Li, Kai Wu, Xing Su, Madoo Varma, Oguz H. Elibol	16.1 A nanogap transducer array on 32nm CMOS for electrochemical DNA sequencing.	ISSCC	2016	DBLP DOI BibTeX RDF
22	Brent Bohnenstiehl, Aaron Stillmaker, Jon J. Pimentel, Timothy Andreas, Bin Liu 0037, Anh Tran, Emmanuel Adeagbo, Bevan M. Baas	A 5.8 pJ/Op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor array.	VLSI Circuits	2016	DBLP DOI BibTeX RDF
22	Pong-Fei Lu, Keith A. Jenkins, K. Paul Muller, Ralf Schaufler	Long-term data for BTI degradation in 32nm IBM microprocessor using HKMG technology.	IRPS	2015	DBLP DOI BibTeX RDF
22	Rafael B. Schivittz, Cristina Meinhardt, Paulo F. Butzen	An evaluation of BTI degradation of 32nm standard cells.	ICECS	2015	DBLP DOI BibTeX RDF
22	Mayank Raj, Manuel Monge, Azita Emami	A 20Gb/s 0.77pJ/b VCSEL transmitter with nonlinear equalization in 32nm SOI CMOS.	CICC	2015	DBLP DOI BibTeX RDF
22	Timothy O. Dickson, Yong Liu 0023, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Mounir Meghelli, Daniel J. Friedman	A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.	CICC	2015	DBLP DOI BibTeX RDF
22	Toke Meyer Andersen, Florian Krismer, Johann Walter Kolar, Thomas Toifl, Christian Menolfi, Lukas Kull, Thomas Morf, Marcel A. Kossel, Matthias Braendli, Pier Andrea Francese	20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS.	ISSCC	2015	DBLP DOI BibTeX RDF
22	Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman	10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme.	ISSCC	2015	DBLP DOI BibTeX RDF
22	Xiaoyang Mi, Debashis Mandal, Visvesh S. Sathe 0001, Bertan Bakkaloglu, Jae-sun Seo	Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS.	ISLPED	2015	DBLP DOI BibTeX RDF
22	Alessandro Cevrero, Cosimo Aprile, Pier Andrea Francese, U. Bapst, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Lukas Kull, Hazar Yueksel, Ilter Oezkaya, Yusuf Leblebici, Volkan Cevher, Thomas Toifl	A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS.	VLSIC	2015	DBLP DOI BibTeX RDF
22	Navneet Gupta, Adam Makosiej, Oliver Thomas, Amara Amara, Andrei Vladimirescu, Costin Anghel	Ultra-low leakage sub-32nm TFET/CMOS hybrid 32kb pseudo DualPort scratchpad with GHz speed for embedded applications.	ISCAS	2015	DBLP DOI BibTeX RDF
22	Anand Ramaswamy, Jonathan E. Roth, Erik J. Norberg, Robert S. Guzzon, Jae-Hyuk Shin, J. T. Imamura, Brian R. Koch, Daniel K. Sparacin, Gregory A. Fish, Benjamin G. Lee, Renato Rimolo-Donadio, Christian W. Baks, Alexander V. Rylyakov, Jonathan E. Proesel, Mounir Meghelli, Clint L. Schow	A WDM 4×28Gbps integrated silicon photonic transmitter driven by 32nm CMOS driver ICs.	OFC	2015	DBLP BibTeX RDF
22	S. Vijayakumar, Reeba Korah	Circuit level, 32nm, 1-bit MOSSI-ULP adder: power, PDP and area efficient base cell for unsigned multiplier.	IEICE Electron. Express	2014	DBLP DOI BibTeX RDF
22	Jyoti Sharma, Mohammad Samar Ansari, Jankiballabh Sharma	Electronically Tunable Resistor-less Universal Filter in ±0.5V 32nm CNFET.	ISED	2014	DBLP DOI BibTeX RDF
22	Timothy O. Dickson, Yong Liu 0023, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman	A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.	CICC	2014	DBLP DOI BibTeX RDF
22	Toke Meyer Andersen, Florian Krismer, Johann W. Kolar, Thomas Toifl, Christian Menolfi, Lukas Kull, Thomas Morf, Marcel A. Kossel, Matthias Braendli, Peter Buchmann, Pier Andrea Francese	4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS.	ISSCC	2014	DBLP DOI BibTeX RDF
22	Vanessa Hung-Chu Chen, Lawrence T. Pileggi	22.2 A 69.5mW 20GS/s 6b time-interleaved ADC with embedded time-to-digital calibration in 32nm CMOS SOI.	ISSCC	2014	DBLP DOI BibTeX RDF
22	Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici	22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS.	ISSCC	2014	DBLP DOI BibTeX RDF
22	Smriti Joshi, Anne Lombardot, Marc Belleville, Edith Beigné, Stéphane Girard	A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits.	DATE	2013	DBLP DOI BibTeX RDF
22	Edith Beigné, Ivan Miro-Panades, Yvain Thonnart, Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Farhat Thabet, Benoît Tain, K. Benchehida, Sylvain Engels, Robin Wilson, Didier Fuin	A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC.	ESSCIRC	2013	DBLP DOI BibTeX RDF
22	Francesco Radice, Melchiorre Bruccoleri, Marcello Ganzerli, Giorgio Spelgatti, Davide Sanzogni, Massimo Pozzoni, Andrea Mazzanti	A 6-bit 6-GS/s 95mW background calibrated flash ADC with integrating preamplifiers and half-rate comparators in 32nm LP CMOS.	ESSCIRC	2013	DBLP DOI BibTeX RDF
22	William Lepkowski, Seth J. Wilk, J. Kam, Trevor J. Thornton	40V MESFETs fabricated on 32nm SOI CMOS.	CICC	2013	DBLP DOI BibTeX RDF
22	Mihai A. T. Sanduleanu, Alberto Valdes-Garcia, Y. Liu, Benjamin D. Parker, Shlomo Shlafman, Benny Sheinman, Danny Elad, Scott K. Reynolds, Daniel J. Friedman	A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI.	CICC	2013	DBLP DOI BibTeX RDF
22	Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici	A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS.	ISSCC	2013	DBLP DOI BibTeX RDF
22	Zheng Wang 0014, Pei-Yuan Chiang, Peyman Nazari, Chun-Cheng Wang, Zhiming Chen 0001, Payam Heydari	A 210GHz fully integrated differential transceiver with fundamental-frequency VCO in 32nm SOI CMOS.	ISSCC	2013	DBLP DOI BibTeX RDF
22	John Davis, Paul Bunce, Diana M. Henderson, Yuen H. Chan, Uma Srinivasan 0002, Daniel Rodko, Pradip Patel, Thomas J. Knips, Tobias Werner 0001	7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor.	ISSCC	2013	DBLP DOI BibTeX RDF
22	Weiwu Hu, Yifu Zhang, Liang Yang, Bao-Xia Fan, Yunji Chen, Shi-Qiang Zhong, Huandong Wang, Zichu Qi, Pengyu Wang, Xiang Gao, Xu Yang, Bin Xiao 0006, Hongsheng Wang, Zongren Yang, Liqiong Yang, Shuai Chen	Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-core processor.	ISSCC	2013	DBLP DOI BibTeX RDF
22	Mozhgan Mansuri, James E. Jaussi, Joseph T. Kennedy, Tzu-Chien Hsueh, Sudip Shekhar, Ganesh Balamurugan, Frank O'Mahony, Clark Roberts, Randy Mooney, Bryan Casper	A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS.	ISSCC	2013	DBLP DOI BibTeX RDF
22	Enrico Mammei, Enrico Monaco, Andrea Mazzanti, Francesco Svelto	A 33.6-to-46.2GHz 32nm CMOS VCO with 177.5dBc/Hz minimum noise FOM using inductor splitting for tuning extension.	ISSCC	2013	DBLP DOI BibTeX RDF
22	Naagesh S. Bhat	Design and modelling of different SRAM's based on CNTFET 32nm technology	CoRR	2012	DBLP BibTeX RDF
22	Hung Viet Nguyen, Myunghwan Ryu, Youngmin Kim	A novel methodology for speeding up IC performance in 32nm FinFET.	IEICE Electron. Express	2012	DBLP DOI BibTeX RDF
22	Gregory Ruhl, Saurabh Dighe, Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Paolo A. Aseron, Howard Wilson, Nitin Borkar	An IA-32 processor with a wide voltage operating range in 32nm CMOS.	Hot Chips Symposium	2012	DBLP DOI BibTeX RDF
22	H. A. Elgomati, B. Y. Majlis, A. M. Abdul Hamid, P. M. Susthitha, Ibrahim Ahmad	Modelling of Process Parameters for 32nm PMOS Transistor Using Taguchi Method.	Asia International Conference on Modelling and Simulation	2012	DBLP DOI BibTeX RDF
22	Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan 0001, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman	A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS.	CICC	2012	DBLP DOI BibTeX RDF
22	Arijit Raychowdhury, Carlos Tokunaga, Willem Marco Beltman, Michael Deisher, James W. Tschanz, Vivek De	A 2.3nJ/frame Voice Activity Detector based audio front-end for context-aware System-on-Chip applications in 32nm CMOS.	CICC	2012	DBLP DOI BibTeX RDF
22	Min Huang, Moty Mehalel, Ramesh Arvapalli, Songnian He	An energy efficient 32nm 20 MB L3 cache for Intel® Xeon® processor E5 family.	CICC	2012	DBLP DOI BibTeX RDF
22	Kailash Chandrashekar, Stefano Pellerano, Paolo Madoglio, Ashoke Ravi, Yorgos Palaskas	A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management.	ISSCC	2012	DBLP DOI BibTeX RDF
22	Se-Hyun Yang, Seogjun Lee, Jae Young Lee, Jeonglae Cho, Hoi-Jin Lee, Dongsik Cho, Junghun Heo, Sunghoon Cho, Youngmin Shin, Sunghee Yun, Euiseok Kim, Ukrae Cho, Edward Pyo, Man Hyuk Park, Jae-Cheol Son, Chinhyun Kim, Jeongnam Youn, Youngki Chung, Sungho Park, Seung Ho Hwang	A 32nm high-k metal gate application processor with GHz multi-core CPU.	ISSCC	2012	DBLP DOI BibTeX RDF
22	Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Saurabh Dighe, Gregory Ruhl, Paolo A. Aseron, Howard Wilson, Nitin Borkar, Vivek De, Shekhar Borkar	A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS.	ISSCC	2012	DBLP DOI BibTeX RDF
22	John F. Bulzacchelli, Troy J. Beukema, Daniel W. Storaska, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati 0002, Christian Menolfi, David Hanson, Juergen Hertle, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William Kelly, Glenn Ritter, Jon Garlett, Robert Callan, Thomas Toifl, Daniel J. Friedman	A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology.	ISSCC	2012	DBLP DOI BibTeX RDF
22	Farhana Sheikh, Sanu Mathew, Mark A. Anders 0001, Himanshu Kaul, Steven Hsu, Amit Agarwal 0001, Ram Krishnamurthy 0001, Shekhar Borkar	A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS.	ISSCC	2012	DBLP DOI BibTeX RDF
22	Hasnain Lakdawala, Mark Schaecher, Chang-Tsung Fu, Rahul Dilip Limaye, Jon Duster, Yulin Tan, Ajay Balankutty, Erkan Alpman, Chun C. Lee, Satoshi Suzuki, Brent R. Carlton, Hyung Seok Kim, Marian Verhelst, Stefano Pellerano, Tong Kim, Durgesh Srivastava, Satish Venkatesan, Hyung-Jin Lee, Peter Vandervoorn, Jad Rizk, Chia-Hong Jan, Krishnamurthy Soumyanath, Sunder Ramamurthy	32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver.	ISSCC	2012	DBLP DOI BibTeX RDF
22	Christian Menolfi, Juergen Hertle, Thomas Toifl, Thomas Morf, Daniele Gardellini, Matthias Braendli, Peter Buchmann, Marcel A. Kossel	A 28Gb/s source-series terminated TX in 32nm CMOS SOI.	ISSCC	2012	DBLP DOI BibTeX RDF
22	Joseph Shor, Kosta Luria, Dror Zilberman	Ratiometric BJT-based thermal sensor in 32nm and 22nm technologies.	ISSCC	2012	DBLP DOI BibTeX RDF
22	Paolo Madoglio, Ashoke Ravi, Hongtao Xu, Kailash Chandrashekar, Marian Verhelst, Stefano Pellerano, Luis Cuellar, Mariano Aguirre, Masoud Sajadieh, Ofir B. Degani, Hasnain Lakdawala, Yorgos Palaskas	A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS.	ISSCC	2012	DBLP DOI BibTeX RDF
22	Himanshu Kaul, Mark A. Anders 0001, Sanu Mathew, Steven Hsu, Amit Agarwal 0001, Farhana Sheikh, Ram Krishnamurthy 0001, Shekhar Borkar	A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS.	ISSCC	2012	DBLP DOI BibTeX RDF
22	Steven Hsu, Amit Agarwal 0001, Mark A. Anders 0001, Himanshu Kaul, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy 0001, Shekhar Borkar	A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS.	VLSIC	2012	DBLP DOI BibTeX RDF
22	Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan 0001, Alexander V. Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu, Alberto Valdes-Garcia, José A. Tierno, Daniel J. Friedman	An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.	VLSIC	2012	DBLP DOI BibTeX RDF
22	Yulin Tan, Jon Duster, Chang-Tsung Fu, Erkan Alpman, Ajay Balankutty, Chun C. Lee, Ashoke Ravi, Stefano Pellerano, Kailash Chandrashekar, Hyung Seok Kim, Brent R. Carlton, Satoshi Suzuki, M. Shafi, Yorgos Palaskas, Hasnain Lakdawala	A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS.	VLSIC	2012	DBLP DOI BibTeX RDF
22	Thomas Toifl, Michael Ruegg, Rajesh Inti, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Peter Buchmann, Pier Andrea Francese, Thomas Morf	A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS.	VLSIC	2012	DBLP DOI BibTeX RDF
22	John Barth 0001, Don Plass, Adis Vehabovic, Rajiv V. Joshi, Rouwaida Kanj, Steven Burns 0001, Todd Weaver	Isolated Preset Architecture for a 32nm SOI embedded DRAM macro.	VLSIC	2012	DBLP DOI BibTeX RDF
22	Arijit Raychowdhury, Dinesh Somasekhar, James W. Tschanz, Vivek De	A fully-digital phase-locked low dropout regulator in 32nm CMOS.	VLSIC	2012	DBLP DOI BibTeX RDF
22	Daniel Fainstein, Sami Rosenblatt, Alberto Cestero, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer	Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM.	VLSIC	2012	DBLP DOI BibTeX RDF
22	Adam Makosiej, Rutwick Kumar Kashyap, Andrei Vladimirescu, Amara Amara, Costin Anghel	A 32nm tunnel FET SRAM for ultra low leakage.	ISCAS	2012	DBLP DOI BibTeX RDF
22	Golam R. Chowdhury, Arjang Hassibi	A 0.001mm2 100µW on-chip temperature sensor with ±1.95 °C (3σ) Inaccuracy in 32nm SOI CMOS.	ISCAS	2012	DBLP DOI BibTeX RDF
22	Nitin Gupta, Tapas Nandy, Somnath Kundu	HDMI transmitter in 32nM technology using 28Å MOS.	ISCAS	2012	DBLP DOI BibTeX RDF
22	Phil Nigh	How are failure modes, defect types and test methods changing for 32nm/28nm technologies and beyond?	ITC	2012	DBLP DOI BibTeX RDF
22	Florian Chouard, Shailesh More, Michael Fulde, Doris Schmitt-Landsiedel	An analog perspective on device reliability in 32nm high-κ metal gate technology.	DDECS	2011	DBLP DOI BibTeX RDF
22	Simon Vanden Bussche, Pieter De Wit, Elie Maricau, Georges G. E. Gielen	Impact analysis of stochastic transistor aging on current-steering DACs in 32nm CMOS.	ICECS	2011	DBLP DOI BibTeX RDF
22	Amit Agarwal 0001, Steven Hsu, Sanu Mathew, Mark A. Anders 0001, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy 0001	A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS.	ESSCIRC	2011	DBLP DOI BibTeX RDF
22	Michael Clinton, Clive Bittlestone, G. Girishankar, Viet Le, Vinod Menezes	Design and technology interaction beyond 32nm.	CICC	2011	DBLP DOI BibTeX RDF
22	Yulin Tan, Hongtao Xu, Mohammed A. El-Tanani, Stewart S. Taylor, Hasnain Lakdawala	A flip-chip-packaged 1.8V 28dBm class-AB power amplifier with shielded concentric transformers in 32nm SoC CMOS.	ISSCC	2011	DBLP DOI BibTeX RDF
22	Shankar Sawant, Utpal Desai, Gururaj Shamanna, Lokesh Sharma, Mandar Ranade, Anil Agarwal, Sampath Dakshinamurthy, Rajagopal Narayanan	A 32nm Westmere-EX Xeon® enterprise processor.	ISSCC	2011	DBLP DOI BibTeX RDF
22	Tim C. Fischer, Srikanth Arekapudi, Eric Busta, Carl Dietz, Michael Golden, Scott Hilker, Aaron Horiuchi, Kevin A. Hurd, Dave Johnson 0002, Hugh McIntyre, Samuel Naffziger, James Vinh, Jonathan White, Kathryn Wilcox	Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU.	ISSCC	2011	DBLP DOI BibTeX RDF
22	Don Weiss, Michael Dreesen, Michael Ciraula, Carson Henrion, Chris Helt, Ryan Freese, Tommy Miles, Anita Karegar, Russell Schreiber, Bryan Schneller, John J. Wuu	An 8MB level-3 cache in 32nm SOI with column-select aliasing.	ISSCC	2011	DBLP DOI BibTeX RDF
22	Shenggao Li, Ashwin Krishnakumar, Edward Helder, Roan Nicholson, Vivian Jia	Clock generation for a 32nm server processor with scalable cores.	ISSCC	2011	DBLP DOI BibTeX RDF
22	Reid J. Riedlinger, Rohit Bhatia, Larry Biro, William J. Bowhill, Eric S. Fetzer, Paul E. Gronowski, Tom Grutkowski	A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers.	ISSCC	2011	DBLP DOI BibTeX RDF
22	Chang-Tsung Fu, Hasnain Lakdawala, Stewart S. Taylor, Krishnamurthy Soumyanath	A 2.5GHz 32nm 0.35mm2 3.5dB NF -5dBm P1dB fully differential CMOS push-pull LNA with integrated 34dBm T/R switch and ESD protection.	ISSCC	2011	DBLP DOI BibTeX RDF
22	Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John A. Gabric, Robert M. Houle, Steve Lamphier, Frank Pavlik, Adnan Seferagic, Liang-Yu Chen, Shang-Bin Ko, Carl Radens	A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements.	ISSCC	2011	DBLP DOI BibTeX RDF
22	Marcelo Yuffe, Ernest Knoll, Moty Mehalel, Joseph Shor, Tsvika Kurts	A fully integrated multi-CPU, GPU and memory controller 32nm processor.	ISSCC	2011	DBLP DOI BibTeX RDF
22	Hyung-Jin Lee, Alexandra M. Kern, Sami Hyvonen, Ian A. Young	A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in 32nm CMOS.	ISSCC	2011	DBLP DOI BibTeX RDF
22	Jenlung Liu, Sehyung Jeon, Tae-Kwang Jang, Dohyung Kim, Jihyun F. Kim, Jaejin Park, Hojin Park	A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS.	A-SSCC	2011	DBLP DOI BibTeX RDF
22	Arash Abadian, Mojtaba Lotfizad, Nasser Erfani Majd, Mohammad Bagher Ghaznavi Ghoushchi, H. Mirzaie	A new low-power and low-complexity all digital PLL (ADPLL) in 180nm and 32nm.	ICECS	2010	DBLP DOI BibTeX RDF
22	Hongtao Xu, Yorgos Palaskas, Ashoke Ravi, Krishnamurthy Soumyanath	A highly linear 25dBm outphasing power amplifier in 32nm CMOS for WLAN application.	ESSCIRC	2010	DBLP DOI BibTeX RDF
22	Florian Chouard, Michael Fulde, Doris Schmitt-Landsiedel	Reliability assessment of voltage controlled oscillators in 32nm high-κ metal gate technology.	ESSCIRC	2010	DBLP DOI BibTeX RDF
22	Jente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter F. Wendel, Sudesh Saroop, Tuyet Nguyen, Thomas Fröhnel, Antje Müller, Christopher M. Durham, Rolf Sautter, Bryan Lloyd, Bryan J. Robbins, Juergen Pille, Sani R. Nassif, Kevin J. Nowka	A 32nm 0.5V-supply dual-read 6T SRAM.	CICC	2010	DBLP DOI BibTeX RDF
22	David E. Duarte, Paola Zepeda, Suching Hsu, Atul Maheshwari, Greg Taylor	HVM performance validation and DFM techniques used in a 32nm CMOS thermal sensor system.	CICC	2010	DBLP DOI BibTeX RDF
22	Aminul Islam 0002, Mohd. Hasan	High Speed Cache Design Using Multi-diameter CNFET at 32nm Technology.	ICT	2010	DBLP DOI BibTeX RDF