Search results for "DRAMs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
138	Betty Prince	Application Specific DRAMs Today.	MTDT	2003	DBLP DOI BibTeX RDF
123	Betty Prince	A Tribute to Graphics Drams.	MTDT	1999	DBLP DOI BibTeX RDF
108	Mrinmoy Ghosh, Hsien-Hsin S. Lee	Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs.	MICRO	2007	DBLP DOI BibTeX RDF
74	Sang-Hoon Lee, Chang-hoon Choi, Jeong-Taek Kong, Wong-Seong Lee, Jei-Hwan Yoo	An efficient statistical analysis methodology and its application to high-density DRAMs.	ICCAD	1997	DBLP DOI BibTeX RDF	statistical SPICE modeling, High-Density DRAMs, Principal Component Analysis, Design for Manufacturing, Gradient Method
59	Zemo Yang, Samiha Mourad	Crosstalk Induced Fault Analysis and Test in DRAMs.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	crosstalk, DRAMs, pattern sensitive faults
59	Zaid Al-Ars, Martin Herzog, Ivo Schanstra, Ad J. van de Goor	Influence of Bit Line Twisting on the Faulty Behavior of DRAMs.	MTDT	2004	DBLP DOI BibTeX RDF	Bit line twisting, bit line coupling, DRAMs, crosstalk noise, defect simulation, faulty behavior
59	Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor	Effects of Bit Line Coupling on the Faulty Behavior of DRAMs.	VTS	2004	DBLP DOI BibTeX RDF	bit line coupling, DRAMs, Spice simulation, data backgrounds, faulty behavior
53	Zaid Al-Ars, Ad J. van de Goor	Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes.	MTDT	2003	DBLP DOI BibTeX RDF	two floating nodes, memory testing, DRAMs, dynamic faults, defect simulation
50	Tung-Han Tsai, Chin-Lin Chen, Ching-Li Lee, Chua-Chin Wang	Power-saving nano-scale DRAMs with an adaptive refreshing clock generator.	ISCAS	2008	DBLP DOI BibTeX RDF
50	Sang-uhn Cha, Hongil Yoon	High Speed, Minimal Area, and Low Power SEC Code for DRAMs with Large I/O Data Widths.	ISCAS	2007	DBLP DOI BibTeX RDF
50	Y. Chang, Minsu Choi, Nohpill Park, Fabrizio Lombardi	Repairability Evaluation of Embedded Multiple Region DRAMs.	DFT	2002	DBLP DOI BibTeX RDF
50	C. Wickman, Duncan G. Elliott, Bruce F. Cockburn	Cost Models for Large File Memory DRAMs with ECC and Bad Block Marking.	DFT	1999	DBLP DOI BibTeX RDF
45	Zaid Al-Ars, Ad J. van de Goor	Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests.	MTDT	2001	DBLP DOI BibTeX RDF	detection conditions, memory testing, DRAMs, transient faults, functional fault models, defect simulation
45	Zaid Al-Ars, Ad J. van de Goor	Impact of memory cell array bridges on the faulty behavior in embedded DRAMs.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	memory cell array bridges, memory fault models, dynamic faulty behavior, dynamic RAM, fault simulation, memory tests, circuit simulation, random-access storage, integrated memory circuits, functional faults, embedded DRAMs, faulty behavior, fault primitives
44	Bo Zhao 0007, Yu Du, Youtao Zhang, Jun Yang 0002	Variation-tolerant non-uniform 3D cache management in die stacked multicore processor.	MICRO	2009	DBLP DOI BibTeX RDF	3D die stacking, NUCA, process variation, DRAM
44	Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor	Space of DRAM fault models and corresponding testing.	DATE	2006	DBLP DOI BibTeX RDF
44	Mahmut T. Kandemir, Ozcan Ozturk 0001, Mary Jane Irwin, Ibrahim Kolcu	Using Data Compression to Increase Energy Savings in Multi-bank Memories.	Euro-Par	2004	DBLP DOI BibTeX RDF
44	Gian Carlo Cardarilli, Stefano Bertazzoni, Marcello Salmeri, Adelio Salsano, P. Marinucci	Design of Fault-Tolerant Solid State Mass Memory.	DFT	1999	DBLP DOI BibTeX RDF
41	Yi-Jung Chen, Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu	Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs.	RACS	2015	DBLP DOI BibTeX RDF
41	Ping-Sheng Lin, Yi-Jung Chen, Chia-Lin Yang, Yi-Chang Lu	Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs.	ISLPED	2013	DBLP DOI BibTeX RDF
39	Zaid Al-Ars, Ad J. van de Goor	Approximating Infinite Dynamic Behavior for DRAM Cell Defects.	VTS	2002	DBLP DOI BibTeX RDF	infinite dynamic faults, memory testing, DRAMs, functional fault models, defect simulation
39	Stephen J. Walsh, John A. Board	Pollution control caching.	ICCD	1995	DBLP DOI BibTeX RDF	pollution control caching, high speed processors, bandwidth mismatch, standard DRAMS, on-chip caches, miss ratio statistics, expected clock cycles per instruction, main memory latencies, PCC+VB, discrete event simulation, memory architecture, trace driven simulation, cache storage, memory performance, ANOVA, DRAM chips
35	Wei Zhang 0032, Ki Chul Chun, Chris H. Kim	Variation aware performance analysis of gain cell embedded DRAMs.	ISLPED	2010	DBLP DOI BibTeX RDF	bitline delay, gain cell, process variation, monte carlo simulation, embedded DRAM
35	Chua-Chin Wang, Yih-Long Tseng, Chih-Chiang Chiu	A temperature-insensitive self-recharging circuitry used in DRAMs.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
35	Ju Yeob Kim, Sung Je Hong, Jong Kim 0001	Parallely testable design for detection of neighborhood pattern sensitive faults in high density DRAMs.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
35	Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik	Efficient Online and Offline Testing of Embedded DRAMs.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	online checking, BIST, systems-on-a-chip, Embedded memories
35	Zemo Yang, Samiha Mourad	Crosstalk in Deep Submicron DRAMs.	MTDT	2000	DBLP DOI BibTeX RDF	Noise and Submicron, Crosstalk, DRAM
35	Yasunao Katayama, Yasushi Negishi, Sumio Morioka	Efficient Error Correction Code Configurations for Quasi-Nonvolatile Data Retention by DRAMs.	DFT	2000	DBLP DOI BibTeX RDF
35	Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik	Error Detecting Refreshment for Embedded DRAMs.	VTS	1999	DBLP DOI BibTeX RDF
29	Daniel Schmidt 0001, Norbert Wehn	DRAM power management and energy consumption: a critical assessment.	SBCCI	2009	DBLP DOI BibTeX RDF	modelling, measurement, power management, SDRAM
29	Joohee Kim, Marios C. Papaefthymiou	Block-based multiperiod dynamic memory design for low data-retention power.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
29	Shyue-Kung Lu	A Novel Built-In Self-Repair Approach for Embedded RAMs.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	divided word line, fault tolerance, redundancy, low power design, embedded memory
29	Norman Margolus	An FPGA architecture for DRAM-based systolic computations.	FCCM	1997	DBLP DOI BibTeX RDF
29	Tsuneo Ikedo	Design and performance evaluation of a pixel cache implemented within application- specific integrated circuits.	Vis. Comput.	1996	DBLP DOI BibTeX RDF	Polygon rendering, Multimedia systems, Graphics processor, HDTV
24	Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath	Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	memory testing, DRAMs, defect simulation, analytical evaluation, faulty behavior
24	Zaid Al-Ars, Ad J. van de Goor	Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	border resistance trace, process variations, memory testing, DRAMs, defect simulation
24	Zaid Al-Ars, Ad J. van de Goor	Modeling Techniques and Tests for Partial Faults in Memory Devices.	DATE	2002	DBLP DOI BibTeX RDF	partial faults, completing operations, fault models, memory testing, DRAMs, defect simulation
24	Manoj Franklin, Kewal K. Saluja	Hypergraph Coloring and Reconfigured RAM Testing.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	hypergraph coloring, reconfigured RAM testing, RAM decoders, critical path lengths, memory chips, physical neighborhood pattern sensitive faults, reconfigured DRAMs, decoder faults, computational complexity, logic testing, redundancy, reconfigurable architectures, stuck-at faults, graph colouring, random-access storage, integrated memory circuits, test lengths, test algorithms, DRAM chips, silicon area
21	Eduardo Ortega, Jonti Talukdar, Woohyun Paik, Tyler K. Bletsch, Krishnendu Chakrabarty	Rowhammer Vulnerability of DRAMs in 3-D Integration.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
21	Yok Jye Tang, Xinmiao Zhang	Generalized Integrated Interleaved Codes for High-Density DRAMs.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
21	In Jun Jung, Tae-Hyun Kim, Keonhee Cho, Ki-Ryong Kim, Seong-Ook Jung	An Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Boosted Internal-Voltage-Difference.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
21	Sai Qian Zhang, Thierry Tambe, Nestor Cuevas, Gu-Yeon Wei, David Brooks 0001	CAMEL: Co-Designing AI Models and Embedded DRAMs for Efficient On-Device Learning.	CoRR	2023	DBLP DOI BibTeX RDF
21	Rachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif, Muhammad Shafique 0001	EnforceSNN: Enabling Resilient and Energy-Efficient Spiking Neural Network Inference considering Approximate DRAMs for Embedded Systems.	CoRR	2023	DBLP DOI BibTeX RDF
21	Florian Frank 0004, Wenjie Xiong 0001, Nikolaos Athanasios Anagnostopoulos, André Schaller, Tolga Arul, Farinaz Koushanfar, Stefan Katzenbeisser 0001, Ulrich Rührmair, Jakub Szefer	Abusing Commodity DRAMs in IoT Devices to Remotely Spy on Temperature.	IEEE Trans. Inf. Forensics Secur.	2023	DBLP DOI BibTeX RDF
21	Sungmock Ha, S. Lee, G. H. Bae, D. S. Lee, S. H. Kim, B. W. Woo, N.-H. Lee, Y. S. Lee, S. Pae	Reliability Characterization of HBM featuring $\text{HK}+\text{MG}$ Logic Chip with Multi-stacked DRAMs.	IRPS	2023	DBLP DOI BibTeX RDF
21	Yichen Jiang, Shuo Wang 0003, Renato Figueiredo, Yier Jin	Warm-Boot Attack on Modern DRAMs.	DATE	2023	DBLP DOI BibTeX RDF
21	Rob A. Damsteegt, Ramon W. J. Overwater, Masoud Babaie, Fabio Sebastiano	A Benchmark of Cryo-CMOS 40-nm Embedded SRAM/DRAMs for Quantum Computing.	ESSCIRC	2023	DBLP DOI BibTeX RDF
21	Soheil Khadirsharbiyani, Jagadish Kotra, Karthik Rao, Mahmut T. Kandemir	Data Convection: A GPU-Driven Case Study for Thermal-Aware Data Placement in 3D DRAMs.	Proc. ACM Meas. Anal. Comput. Syst.	2022	DBLP DOI BibTeX RDF
21	Florian Frank 0004, Wenjie Xiong 0001, Nikolaos Athanasios Anagnostopoulos, André Schaller, Tolga Arul, Farinaz Koushanfar, Stefan Katzenbeisser 0001, Ulrich Rührmair, Jakub Szefer	Abusing Commodity DRAMs in IoT Devices to Remotely Spy on Temperature.	CoRR	2022	DBLP DOI BibTeX RDF
21	Soheil Khadirsharbiyani, Jagadish Kotra, Karthik Rao, Mahmut Taylan Kandemir	Data Convection: A GPU-Driven Case Study for Thermal-Aware Data Placement in 3D DRAMs.	SIGMETRICS (Abstracts)	2022	DBLP DOI BibTeX RDF
21	Deepak M. Mathew, Hammam Kattan, Christian Weis, Jörg Henkel, Norbert Wehn, Hussam Amrouch	Longevity of Commodity DRAMs in Harsh Environments Through Thermoelectric Cooling.	IEEE Access	2021	DBLP DOI BibTeX RDF
21	Bobby Bose, Ishan G. Thakkar	Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs.	CoRR	2021	DBLP BibTeX RDF
21	Zhwen Chen, Young-Suk Kim, Tadashi Fukuda, Koji Sakui, Takayuki Ohba, Tatsuji Kobayashi, Takashi Obara	Reliability of Wafer-Level Ultra-Thinning down to 3 µm using 20 nm-Node DRAMs.	IRPS	2021	DBLP DOI BibTeX RDF
21	Bobby Bose, Ishan G. Thakkar	Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs.	ACM Great Lakes Symposium on VLSI	2021	DBLP DOI BibTeX RDF
21	Jungmin Yoon, Hyungrok Do, Daehyun Koh, Seunghan Oak, Junphyo Lee, Deog-Kyoon Jeong	A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced Variation of Decision Threshold Voltage.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
21	Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg	Gain-Cell Embedded DRAMs: Modeling and Design Space.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
21	Yi Jiang, Gina Giase, Kay Grennan, Annie W. Shieh, Yan Xia, Lide Han, Quan Wang 0004, Qiang Wei, Rui Chen 0021, Sihan Liu, Kevin P. White, Chao Chen, Bingshan Li, Chunyu Liu	DRAMS: A tool to detect and re-align mixed-up samples for integrative studies of multi-omics data.	PLoS Comput. Biol.	2020	DBLP DOI BibTeX RDF
21	Robert Giterman, Andrea Bonetti, Ester Vicario Bravo, Tzachi Noy, Adam Teman, Andreas Burg	Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space.	IEEE Trans. Circuits Syst. I Fundam. Theory Appl.	2020	DBLP DOI BibTeX RDF
21	Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg	Gain-Cell Embedded DRAMs: Modeling and Design Space.	ISCAS	2020	DBLP DOI BibTeX RDF
21	Tsung-Fu Hsieh, Jin-Fu Li 0001, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou	Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method.	ITC-Asia	2020	DBLP DOI BibTeX RDF
21	Jae Young Hur, Sang Woo Rhim, Beom Hak Lee, Wooyoung Jang	Adaptive Linear Address Map for Bank Interleaving in DRAMs.	IEEE Access	2019	DBLP DOI BibTeX RDF
21	Tengtao Li, Sachin S. Sapatnekar	Stress-Induced Performance Shifts in 3D DRAMs.	ACM Trans. Design Autom. Electr. Syst.	2019	DBLP DOI BibTeX RDF
21	Fei Gao 0016, Georgios Tziantzioulis, David Wentzlaff	ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs.	MICRO	2019	DBLP DOI BibTeX RDF
21	Abdessamad Najdi, Daniele Rossi 0001, Vasileios Tenentes	Analysis on Retention Time and Adaptive Refresh in Embedded DRAMs with Aging Benefits.	IOLTS	2019	DBLP DOI BibTeX RDF
21	Nima Karimian, Fatemeh Tehranipoor	How to Generate Robust Keys from Noisy DRAMs?	ACM Great Lakes Symposium on VLSI	2019	DBLP DOI BibTeX RDF
21	Marco Widmer, Andrea Bonetti, Andreas Burg	FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems.	DAC	2019	DBLP DOI BibTeX RDF
21	Hoseok Seol, Wongyu Shin, Jaemin Jang, Jungwhan Choi, Hakseung Lee, Lee-Sup Kim	Elaborate Refresh: A Fine Granularity Retention Management for Deep Submicron DRAMs.	IEEE Trans. Computers	2018	DBLP DOI BibTeX RDF
21	Esteve Amat, Antonio Calomarde, Ramon Canal, Antonio Rubio 0001	Optimization of FinFET-Based Gain Cells for Low Power Sub-V T Embedded DRAMs.	J. Low Power Electron.	2018	DBLP DOI BibTeX RDF
21	Jeong Cho, Young-Jae Min	An all-digital duty-cycle and phase-skew correction circuit for QDR DRAMs.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
21	Jongsun Kim, S. W. Han	A low-power fast-lock DCC with a digital duty-cycle adjuster for LPDDR3 and LPDDR4 DRAMs.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
21	Konstantinos Tovletoglou, Lev Mukhanov, Georgios Karakonstantis, Athanasios Chatzidimitriou, George Papadimitriou 0001, Manolis Kaliorakis, Dimitris Gizopoulos, Zacharias Hadjilambrou, Yiannakis Sazeides, Alejandro Lampropulos, Shidhartha Das, Phong Vo	Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs.	DSN Workshops	2018	DBLP DOI BibTeX RDF
21	Deepak M. Mathew, Martin Schultheis, Carl Christian Rheinländer, Chirag Sudarshan, Christian Weis, Norbert Wehn, Matthias Jung 0001	An analysis on retention error behavior and power consumption of recent DDR4 DRAMs.	DATE	2018	DBLP DOI BibTeX RDF
21	Kuan-Te Wu, Jin-Fu Li 0001, Chih-Yen Lo, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou	A channel-sharable built-in self-test scheme for multi-channel DRAMs.	ASP-DAC	2018	DBLP DOI BibTeX RDF
21	Anaam Ansari, Tokunbo Ogunfunmi	Selective Data Transfer from DRAMs for CNNs.	SiPS	2018	DBLP DOI BibTeX RDF
21	Bibhas Ghoshal, Chittaranjan Mandal 0002, Indranil Sengupta 0001	Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs.	Integr.	2017	DBLP DOI BibTeX RDF
21	Matthias Jung 0001, Kira Kraft, Norbert Wehn	A new state model for DRAMs using Petri Nets.	SAMOS	2017	DBLP DOI BibTeX RDF
21	Chia-Ming Chang, Yong-Xiao Chen, Jin-Fu Li 0001	A built-in self-test scheme for classifying refresh periods of DRAMs.	ETS	2017	DBLP DOI BibTeX RDF
21	Tengtao Li, Sachin S. Sapatnekar	Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs.	ICCAD	2017	DBLP DOI BibTeX RDF
21	Lei Jiang 0001, Minje Kim, Wujie Wen, Danghui Wang	XNOR-POP: A processing-in-memory architecture for binary Convolutional Neural Networks in Wide-IO2 DRAMs.	ISLPED	2017	DBLP DOI BibTeX RDF
21	Tsung-Fu Hsieh, Jin-Fu Li 0001, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou	Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs.	ITC-Asia	2017	DBLP DOI BibTeX RDF
21	Yiorgos Sfikas, Yiorgos Tsiatouhas	Testing Neighbouring Cell Leakage and Transition Induced Faults in DRAMs.	IEEE Trans. Computers	2016	DBLP DOI BibTeX RDF
21	Sherif M. Sharroush	Performance optimization of 1T-1C DRAMs: A quantitative study.	Microelectron. J.	2016	DBLP DOI BibTeX RDF
21	Klaus Hofmann, Tu Darmstadt	The long way to power efficient, high performance DRAMs.	PATMOS	2016	DBLP DOI BibTeX RDF
21	Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján	HAPPY: Hybrid Address-based Page Policy in DRAMs.	MEMSYS	2016	DBLP DOI BibTeX RDF
21	Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján	DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs.	MEMSYS	2016	DBLP DOI BibTeX RDF
21	Matthias Jung 0001, Carl Christian Rheinländer, Christian Weis, Norbert Wehn	Reverse Engineering of DRAMs: Row Hammer with Crosshair.	MEMSYS	2016	DBLP DOI BibTeX RDF
21	Dae Hyun Kim 0003, Linda S. Milor	ECC-ASPIRIN: An ECC-assisted post-package repair scheme for aging errors in DRAMs.	VTS	2016	DBLP DOI BibTeX RDF
21	Zichuan Liu, Yuan Liang, Nan Li, Guangyin Feng, Hao Yu 0001, Shaojie Chen	An Energy-efficient Adaptive Sub-THz Wireless Interconnect with MIMO-Beamforming between Cores and DRAMs.	NANOCOM	2016	DBLP DOI BibTeX RDF
21	Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li 0001, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou	A built-in self-repair scheme for DRAMs with spare rows, columns, and bits.	ITC	2016	DBLP DOI BibTeX RDF
21	Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang	SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs.	ACM Trans. Archit. Code Optim.	2015	DBLP DOI BibTeX RDF
21	Mohsen Ghasempour, Jim D. Garside, Aamer Jaleel, Mikel Luján	DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs.	CoRR	2015	DBLP BibTeX RDF
21	Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján	HAPPY: Hybrid Address-based Page Policy in DRAMs.	CoRR	2015	DBLP BibTeX RDF
21	Dae Hyun Kim 0003, Soonyoung Cha, Linda S. Milor	AVERT: An elaborate model for simulating variable retention time in DRAMs.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
21	Dae Hyun Kim 0003, Soonyoung Cha, Linda S. Milor	Built-in self-test for bias temperature instability, hot-carrier injection, and gate oxide breakdown in embedded DRAMs.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
21	Krishna M. Kavi, Stefano Pianelli, Giandomenico Pisano, Giuseppe Regina, Mike Ignatowski	Memory organizations for 3D-DRAMs and PCMs in processor memory hierarchy.	J. Syst. Archit.	2015	DBLP DOI BibTeX RDF
21	Aimed Lutfi Elgreatly, Aimed Ahmed Shaaban, El-Sayed M. El-Rabaie	Enhancing Power Delay Product in DRAMs using resonant tunneling diode buffer.	ICM	2015	DBLP DOI BibTeX RDF
21	Christian Weis, Matthias Jung 0001, Omar Naji, Norbert Wehn, Cristiano Santos, Pascal Vivet, Andreas Hansson 0001	Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs.	ISVLSI	2015	DBLP DOI BibTeX RDF
21	Yiorgos Sfikas, Yiorgos Tsiatouhas, Mottaqiallah Taouil, Said Hamdioui	On resistive open defect detection in DRAMs: The charge accumulation effect.	ETS	2015	DBLP DOI BibTeX RDF
21	Che-Wei Chou, Yong-Xiao Chen, Jin-Fu Li 0001	Testing Inter-Word Coupling Faults of Wide I/O DRAMs.	ATS	2015	DBLP DOI BibTeX RDF
21	Matthias Jung 0001, Éder Zulian, Deepak M. Mathew, Matthias Herrmann, Christian Brugger, Christian Weis, Norbert Wehn	Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs.	MEMSYS	2015	DBLP DOI BibTeX RDF