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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 188 occurrences of 110 keywords
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Results
Found 257 publication records. Showing 257 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
138 | Betty Prince |
Application Specific DRAMs Today. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 7-13, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
123 | Betty Prince |
A Tribute to Graphics Drams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 7th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT '99), August 9-10, 1999, San Jose, CA, USA, pp. 123-, 1999, IEEE Computer Society, 0-7695-0259-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
108 | Mrinmoy Ghosh, Hsien-Hsin S. Lee |
Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA, pp. 134-145, 2007, IEEE Computer Society, 0-7695-3047-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
74 | Sang-Hoon Lee, Chang-hoon Choi, Jeong-Taek Kong, Wong-Seong Lee, Jei-Hwan Yoo |
An efficient statistical analysis methodology and its application to high-density DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 678-683, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
statistical SPICE modeling, High-Density DRAMs, Principal Component Analysis, Design for Manufacturing, Gradient Method |
59 | Zemo Yang, Samiha Mourad |
Crosstalk Induced Fault Analysis and Test in DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(2), pp. 173-187, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
crosstalk, DRAMs, pattern sensitive faults |
59 | Zaid Al-Ars, Martin Herzog, Ivo Schanstra, Ad J. van de Goor |
Influence of Bit Line Twisting on the Faulty Behavior of DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 32-37, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Bit line twisting, bit line coupling, DRAMs, crosstalk noise, defect simulation, faulty behavior |
59 | Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor |
Effects of Bit Line Coupling on the Faulty Behavior of DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 117-122, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
bit line coupling, DRAMs, Spice simulation, data backgrounds, faulty behavior |
53 | Zaid Al-Ars, Ad J. van de Goor |
Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 27-32, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
two floating nodes, memory testing, DRAMs, dynamic faults, defect simulation |
50 | Tung-Han Tsai, Chin-Lin Chen, Ching-Li Lee, Chua-Chin Wang |
Power-saving nano-scale DRAMs with an adaptive refreshing clock generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 612-615, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
50 | Sang-uhn Cha, Hongil Yoon |
High Speed, Minimal Area, and Low Power SEC Code for DRAMs with Large I/O Data Widths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3026-3029, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
50 | Y. Chang, Minsu Choi, Nohpill Park, Fabrizio Lombardi |
Repairability Evaluation of Embedded Multiple Region DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 428-436, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
50 | C. Wickman, Duncan G. Elliott, Bruce F. Cockburn |
Cost Models for Large File Memory DRAMs with ECC and Bad Block Marking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 319-, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
45 | Zaid Al-Ars, Ad J. van de Goor |
Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 9th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2001), 6-7 August 2001, San Jose, CA, USA, pp. 59-64, 2001, IEEE Computer Society, 0-7695-1242-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
detection conditions, memory testing, DRAMs, transient faults, functional fault models, defect simulation |
45 | Zaid Al-Ars, Ad J. van de Goor |
Impact of memory cell array bridges on the faulty behavior in embedded DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 282-289, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
memory cell array bridges, memory fault models, dynamic faulty behavior, dynamic RAM, fault simulation, memory tests, circuit simulation, random-access storage, integrated memory circuits, functional faults, embedded DRAMs, faulty behavior, fault primitives |
44 | Bo Zhao 0007, Yu Du, Youtao Zhang, Jun Yang 0002 |
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 222-231, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
3D die stacking, NUCA, process variation, DRAM |
44 | Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor |
Space of DRAM fault models and corresponding testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1252-1257, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
44 | Mahmut T. Kandemir, Ozcan Ozturk 0001, Mary Jane Irwin, Ibrahim Kolcu |
Using Data Compression to Increase Energy Savings in Multi-bank Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2004 Parallel Processing, 10th International Euro-Par Conference, Pisa, Italy, August 31-September 3, 2004, Proceedings, pp. 310-317, 2004, Springer, 3-540-22924-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
44 | Gian Carlo Cardarilli, Stefano Bertazzoni, Marcello Salmeri, Adelio Salsano, P. Marinucci |
Design of Fault-Tolerant Solid State Mass Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 302-310, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
41 | Yi-Jung Chen, Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu |
Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RACS ![In: Proceedings of the 2015 Conference on research in adaptive and convergent systems, RACS 2015, Prague, Czech Republic, October 9-12, 2015, pp. 430-436, 2015, ACM, 978-1-4503-3738-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
41 | Ping-Sheng Lin, Yi-Jung Chen, Chia-Lin Yang, Yi-Chang Lu |
Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: International Symposium on Low Power Electronics and Design (ISLPED), Beijing, China, September 4-6, 2013, pp. 304, 2013, IEEE, 978-1-4799-1235-3. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
39 | Zaid Al-Ars, Ad J. van de Goor |
Approximating Infinite Dynamic Behavior for DRAM Cell Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 401-406, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
infinite dynamic faults, memory testing, DRAMs, functional fault models, defect simulation |
39 | Stephen J. Walsh, John A. Board |
Pollution control caching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 300-306, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
pollution control caching, high speed processors, bandwidth mismatch, standard DRAMS, on-chip caches, miss ratio statistics, expected clock cycles per instruction, main memory latencies, PCC+VB, discrete event simulation, memory architecture, trace driven simulation, cache storage, memory performance, ANOVA, DRAM chips |
35 | Wei Zhang 0032, Ki Chul Chun, Chris H. Kim |
Variation aware performance analysis of gain cell embedded DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 19-24, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
bitline delay, gain cell, process variation, monte carlo simulation, embedded DRAM |
35 | Chua-Chin Wang, Yih-Long Tseng, Chih-Chiang Chiu |
A temperature-insensitive self-recharging circuitry used in DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(3), pp. 405-408, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Ju Yeob Kim, Sung Je Hong, Jong Kim 0001 |
Parallely testable design for detection of neighborhood pattern sensitive faults in high density DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5854-5857, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik |
Efficient Online and Offline Testing of Embedded DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(7), pp. 801-809, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
online checking, BIST, systems-on-a-chip, Embedded memories |
35 | Zemo Yang, Samiha Mourad |
Crosstalk in Deep Submicron DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 8th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2000), 7-8 August 2000, San Jose, CA, USA, pp. 125-130, 2000, IEEE Computer Society, 0-7695-0689-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Noise and Submicron, Crosstalk, DRAM |
35 | Yasunao Katayama, Yasushi Negishi, Sumio Morioka |
Efficient Error Correction Code Configurations for Quasi-Nonvolatile Data Retention by DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings, pp. 201-, 2000, IEEE Computer Society, 0-7695-0719-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
35 | Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik |
Error Detecting Refreshment for Embedded DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 384-390, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Daniel Schmidt 0001, Norbert Wehn |
DRAM power management and energy consumption: a critical assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
modelling, measurement, power management, SDRAM |
29 | Joohee Kim, Marios C. Papaefthymiou |
Block-based multiperiod dynamic memory design for low data-retention power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(6), pp. 1006-1018, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Shyue-Kung Lu |
A Novel Built-In Self-Repair Approach for Embedded RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(3), pp. 315-324, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
divided word line, fault tolerance, redundancy, low power design, embedded memory |
29 | Norman Margolus |
An FPGA architecture for DRAM-based systolic computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 16-18 April 1997, Napa Valley, CA, USA, pp. 2-11, 1997, IEEE Computer Society, 0-8186-8159-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
29 | Tsuneo Ikedo |
Design and performance evaluation of a pixel cache implemented within application- specific integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Vis. Comput. ![In: Vis. Comput. 12(5), pp. 215-233, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Polygon rendering, Multimedia systems, Graphics processor, HDTV |
24 | Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath |
Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 434-439, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
memory testing, DRAMs, defect simulation, analytical evaluation, faulty behavior |
24 | Zaid Al-Ars, Ad J. van de Goor |
Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 24-27, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
border resistance trace, process variations, memory testing, DRAMs, defect simulation |
24 | Zaid Al-Ars, Ad J. van de Goor |
Modeling Techniques and Tests for Partial Faults in Memory Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 89-93, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
partial faults, completing operations, fault models, memory testing, DRAMs, defect simulation |
24 | Manoj Franklin, Kewal K. Saluja |
Hypergraph Coloring and Reconfigured RAM Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(6), pp. 725-736, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
hypergraph coloring, reconfigured RAM testing, RAM decoders, critical path lengths, memory chips, physical neighborhood pattern sensitive faults, reconfigured DRAMs, decoder faults, computational complexity, logic testing, redundancy, reconfigurable architectures, stuck-at faults, graph colouring, random-access storage, integrated memory circuits, test lengths, test algorithms, DRAM chips, silicon area |
21 | Eduardo Ortega, Jonti Talukdar, Woohyun Paik, Tyler K. Bletsch, Krishnendu Chakrabarty |
Rowhammer Vulnerability of DRAMs in 3-D Integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 32(5), pp. 967-971, May 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
21 | Yok Jye Tang, Xinmiao Zhang |
Generalized Integrated Interleaved Codes for High-Density DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 71(1), pp. 410-414, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
21 | In Jun Jung, Tae-Hyun Kim, Keonhee Cho, Ki-Ryong Kim, Seong-Ook Jung |
An Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Boosted Internal-Voltage-Difference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(9), pp. 3243-3247, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Sai Qian Zhang, Thierry Tambe, Nestor Cuevas, Gu-Yeon Wei, David Brooks 0001 |
CAMEL: Co-Designing AI Models and Embedded DRAMs for Efficient On-Device Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2305.03148, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Rachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif, Muhammad Shafique 0001 |
EnforceSNN: Enabling Resilient and Energy-Efficient Spiking Neural Network Inference considering Approximate DRAMs for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2304.04039, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Florian Frank 0004, Wenjie Xiong 0001, Nikolaos Athanasios Anagnostopoulos, André Schaller, Tolga Arul, Farinaz Koushanfar, Stefan Katzenbeisser 0001, Ulrich Rührmair, Jakub Szefer |
Abusing Commodity DRAMs in IoT Devices to Remotely Spy on Temperature. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Forensics Secur. ![In: IEEE Trans. Inf. Forensics Secur. 18, pp. 2991-3005, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Sungmock Ha, S. Lee, G. H. Bae, D. S. Lee, S. H. Kim, B. W. Woo, N.-H. Lee, Y. S. Lee, S. Pae |
Reliability Characterization of HBM featuring $\text{HK}+\text{MG}$ Logic Chip with Multi-stacked DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2023, Monterey, CA, USA, March 26-30, 2023, pp. 1-7, 2023, IEEE, 978-1-6654-5672-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Yichen Jiang, Shuo Wang 0003, Renato Figueiredo, Yier Jin |
Warm-Boot Attack on Modern DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023, pp. 1-2, 2023, IEEE, 978-3-9819263-7-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Rob A. Damsteegt, Ramon W. J. Overwater, Masoud Babaie, Fabio Sebastiano |
A Benchmark of Cryo-CMOS 40-nm Embedded SRAM/DRAMs for Quantum Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023, Lisbon, Portugal, September 11-14, 2023, pp. 165-168, 2023, IEEE, 979-8-3503-0420-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Soheil Khadirsharbiyani, Jagadish Kotra, Karthik Rao, Mahmut T. Kandemir |
Data Convection: A GPU-Driven Case Study for Thermal-Aware Data Placement in 3D DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. ACM Meas. Anal. Comput. Syst. ![In: Proc. ACM Meas. Anal. Comput. Syst. 6(1), pp. 7:1-7:25, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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21 | Florian Frank 0004, Wenjie Xiong 0001, Nikolaos Athanasios Anagnostopoulos, André Schaller, Tolga Arul, Farinaz Koushanfar, Stefan Katzenbeisser 0001, Ulrich Rührmair, Jakub Szefer |
Abusing Commodity DRAMs in IoT Devices to Remotely Spy on Temperature. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2208.02125, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Soheil Khadirsharbiyani, Jagadish Kotra, Karthik Rao, Mahmut Taylan Kandemir |
Data Convection: A GPU-Driven Case Study for Thermal-Aware Data Placement in 3D DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS (Abstracts) ![In: SIGMETRICS/PERFORMANCE '22: ACM SIGMETRICS/IFIP PERFORMANCE Joint International Conference on Measurement and Modeling of Computer Systems, Mumbai, India, June 6 - 10, 2022, pp. 37-38, 2022, ACM, 978-1-4503-9141-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Deepak M. Mathew, Hammam Kattan, Christian Weis, Jörg Henkel, Norbert Wehn, Hussam Amrouch |
Longevity of Commodity DRAMs in Harsh Environments Through Thermoelectric Cooling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 83950-83962, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Bobby Bose, Ishan G. Thakkar |
Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2106.09308, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
21 | Zhwen Chen, Young-Suk Kim, Tadashi Fukuda, Koji Sakui, Takayuki Ohba, Tatsuji Kobayashi, Takashi Obara |
Reliability of Wafer-Level Ultra-Thinning down to 3 µm using 20 nm-Node DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2021, Monterey, CA, USA, March 21-25, 2021, pp. 1-6, 2021, IEEE, 978-1-7281-6893-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Bobby Bose, Ishan G. Thakkar |
Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: GLSVLSI '21: Great Lakes Symposium on VLSI 2021, Virtual Event, USA, June 22-25, 2021., pp. 101-107, 2021, ACM, 978-1-4503-8393-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Jungmin Yoon, Hyungrok Do, Daehyun Koh, Seunghan Oak, Junphyo Lee, Deog-Kyoon Jeong |
A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced Variation of Decision Threshold Voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 55(8), pp. 2219-2227, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg |
Gain-Cell Embedded DRAMs: Modeling and Design Space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 28(3), pp. 646-659, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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21 | Yi Jiang, Gina Giase, Kay Grennan, Annie W. Shieh, Yan Xia, Lide Han, Quan Wang 0004, Qiang Wei, Rui Chen 0021, Sihan Liu, Kevin P. White, Chao Chen, Bingshan Li, Chunyu Liu |
DRAMS: A tool to detect and re-align mixed-up samples for integrative studies of multi-omics data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLoS Comput. Biol. ![In: PLoS Comput. Biol. 16(4), 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Robert Giterman, Andrea Bonetti, Ester Vicario Bravo, Tzachi Noy, Adam Teman, Andreas Burg |
Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Fundam. Theory Appl. ![In: IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(4), pp. 1207-1217, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg |
Gain-Cell Embedded DRAMs: Modeling and Design Space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, pp. 1, 2020, IEEE, 978-1-7281-3320-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Tsung-Fu Hsieh, Jin-Fu Li 0001, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou |
Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC-Asia ![In: IEEE International Test Conference in Asia, ITC-Asia 2020, Taipei, Taiwan, September 23-25, 2020, pp. 41-46, 2020, IEEE, 978-1-7281-8944-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Jae Young Hur, Sang Woo Rhim, Beom Hak Lee, Wooyoung Jang |
Adaptive Linear Address Map for Bank Interleaving in DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 129604-129616, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Tengtao Li, Sachin S. Sapatnekar |
Stress-Induced Performance Shifts in 3D DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 24(5), pp. 51:1-51:21, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Fei Gao 0016, Georgios Tziantzioulis, David Wentzlaff |
ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2019, Columbus, OH, USA, October 12-16, 2019., pp. 100-113, 2019, ACM, 978-1-4503-6938-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Abdessamad Najdi, Daniele Rossi 0001, Vasileios Tenentes |
Analysis on Retention Time and Adaptive Refresh in Embedded DRAMs with Aging Benefits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 25th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2019, Rhodes, Greece, July 1-3, 2019, pp. 281-286, 2019, IEEE, 978-1-7281-2490-2. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Nima Karimian, Fatemeh Tehranipoor |
How to Generate Robust Keys from Noisy DRAMs? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 2019 on Great Lakes Symposium on VLSI, GLSVLSI 2019, Tysons Corner, VA, USA, May 9-11, 2019, pp. 465-469, 2019, ACM, 978-1-4503-6252-8. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Marco Widmer, Andrea Bonetti, Andreas Burg |
FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019, pp. 36, 2019, ACM, 978-1-4503-6725-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Hoseok Seol, Wongyu Shin, Jaemin Jang, Jungwhan Choi, Hakseung Lee, Lee-Sup Kim |
Elaborate Refresh: A Fine Granularity Retention Management for Deep Submicron DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 67(10), pp. 1403-1415, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Esteve Amat, Antonio Calomarde, Ramon Canal, Antonio Rubio 0001 |
Optimization of FinFET-Based Gain Cells for Low Power Sub-V T Embedded DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 14(2), pp. 236-243, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Jeong Cho, Young-Jae Min |
An all-digital duty-cycle and phase-skew correction circuit for QDR DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 15(9), pp. 20180331, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Jongsun Kim, S. W. Han |
A low-power fast-lock DCC with a digital duty-cycle adjuster for LPDDR3 and LPDDR4 DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 15(7), pp. 20180156, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Konstantinos Tovletoglou, Lev Mukhanov, Georgios Karakonstantis, Athanasios Chatzidimitriou, George Papadimitriou 0001, Manolis Kaliorakis, Dimitris Gizopoulos, Zacharias Hadjilambrou, Yiannakis Sazeides, Alejandro Lampropulos, Shidhartha Das, Phong Vo |
Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN Workshops ![In: 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, DSN Workshops 2018, Luxembourg, June 25-28, 2018, pp. 6-9, 2018, IEEE Computer Society, 978-1-5386-6553-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Deepak M. Mathew, Martin Schultheis, Carl Christian Rheinländer, Chirag Sudarshan, Christian Weis, Norbert Wehn, Matthias Jung 0001 |
An analysis on retention error behavior and power consumption of recent DDR4 DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018, pp. 293-296, 2018, IEEE, 978-3-9819263-0-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Kuan-Te Wu, Jin-Fu Li 0001, Chih-Yen Lo, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou |
A channel-sharable built-in self-test scheme for multi-channel DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea (South), January 22-25, 2018, pp. 245-250, 2018, IEEE, 978-1-5090-0602-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Anaam Ansari, Tokunbo Ogunfunmi |
Selective Data Transfer from DRAMs for CNNs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: 2018 IEEE International Workshop on Signal Processing Systems, SiPS 2018, Cape Town, South Africa, October 21-24, 2018, pp. 7-12, 2018, IEEE, 978-1-5386-6318-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Bibhas Ghoshal, Chittaranjan Mandal 0002, Indranil Sengupta 0001 |
Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 59, pp. 168-178, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Matthias Jung 0001, Kira Kraft, Norbert Wehn |
A new state model for DRAMs using Petri Nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2017, Pythagorion, Greece, July 17-20, 2017, pp. 221-226, 2017, IEEE, 978-1-5386-3437-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Chia-Ming Chang, Yong-Xiao Chen, Jin-Fu Li 0001 |
A built-in self-test scheme for classifying refresh periods of DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 22nd IEEE European Test Symposium, ETS 2017, Limassol, Cyprus, May 22-26, 2017, pp. 1-2, 2017, IEEE, 978-1-5090-5457-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Tengtao Li, Sachin S. Sapatnekar |
Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017, Irvine, CA, USA, November 13-16, 2017, pp. 645-650, 2017, IEEE, 978-1-5386-3093-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Lei Jiang 0001, Minje Kim, Wujie Wen, Danghui Wang |
XNOR-POP: A processing-in-memory architecture for binary Convolutional Neural Networks in Wide-IO2 DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017, Taipei, Taiwan, July 24-26, 2017, pp. 1-6, 2017, IEEE, 978-1-5090-6023-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Tsung-Fu Hsieh, Jin-Fu Li 0001, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou |
Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC-Asia ![In: International Test Conference in Asia, ITC-Asia 2017, Taipei, Taiwan, September 13-15, 2017, pp. 107-111, 2017, IEEE, 978-1-5386-3051-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Yiorgos Sfikas, Yiorgos Tsiatouhas |
Testing Neighbouring Cell Leakage and Transition Induced Faults in DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 65(7), pp. 2339-2345, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Sherif M. Sharroush |
Performance optimization of 1T-1C DRAMs: A quantitative study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 52, pp. 147-164, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Klaus Hofmann, Tu Darmstadt |
The long way to power efficient, high performance DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Bremen, Germany, September 21-23, 2016, pp. 289-290, 2016, IEEE, 978-1-5090-0733-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján |
HAPPY: Hybrid Address-based Page Policy in DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMSYS ![In: Proceedings of the Second International Symposium on Memory Systems, MEMSYS 2016, Alexandria, VA, USA, October 3-6, 2016, pp. 311-321, 2016, ACM, 978-1-4503-4305-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján |
DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMSYS ![In: Proceedings of the Second International Symposium on Memory Systems, MEMSYS 2016, Alexandria, VA, USA, October 3-6, 2016, pp. 362-373, 2016, ACM, 978-1-4503-4305-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Matthias Jung 0001, Carl Christian Rheinländer, Christian Weis, Norbert Wehn |
Reverse Engineering of DRAMs: Row Hammer with Crosshair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMSYS ![In: Proceedings of the Second International Symposium on Memory Systems, MEMSYS 2016, Alexandria, VA, USA, October 3-6, 2016, pp. 471-476, 2016, ACM, 978-1-4503-4305-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Dae Hyun Kim 0003, Linda S. Milor |
ECC-ASPIRIN: An ECC-assisted post-package repair scheme for aging errors in DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 34th IEEE VLSI Test Symposium, VTS 2016, Las Vegas, NV, USA, April 25-27, 2016, pp. 1-6, 2016, IEEE Computer Society, 978-1-4673-8454-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Zichuan Liu, Yuan Liang, Nan Li, Guangyin Feng, Hao Yu 0001, Shaojie Chen |
An Energy-efficient Adaptive Sub-THz Wireless Interconnect with MIMO-Beamforming between Cores and DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOCOM ![In: Proceedings of the 3rd ACM International Conference on Nanoscale Computing and Communication, NANOCOM 2016, New York, NY, USA, September 28-30, 2016, pp. 26:1-26:6, 2016, ACM, 978-1-4503-4061-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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21 | Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li 0001, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou |
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2016 IEEE International Test Conference, ITC 2016, Fort Worth, TX, USA, November 15-17, 2016, pp. 1-7, 2016, IEEE, 978-1-4673-8773-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang |
SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 12(2), pp. 19:19:1-19:19:24, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
21 | Mohsen Ghasempour, Jim D. Garside, Aamer Jaleel, Mikel Luján |
DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1509.03721, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
21 | Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján |
HAPPY: Hybrid Address-based Page Policy in DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1509.03740, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
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21 | Dae Hyun Kim 0003, Soonyoung Cha, Linda S. Milor |
AVERT: An elaborate model for simulating variable retention time in DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 55(9-10), pp. 1313-1319, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
21 | Dae Hyun Kim 0003, Soonyoung Cha, Linda S. Milor |
Built-in self-test for bias temperature instability, hot-carrier injection, and gate oxide breakdown in embedded DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 55(9-10), pp. 2113-2118, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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21 | Krishna M. Kavi, Stefano Pianelli, Giandomenico Pisano, Giuseppe Regina, Mike Ignatowski |
Memory organizations for 3D-DRAMs and PCMs in processor memory hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 61(10), pp. 539-552, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
21 | Aimed Lutfi Elgreatly, Aimed Ahmed Shaaban, El-Sayed M. El-Rabaie |
Enhancing Power Delay Product in DRAMs using resonant tunneling diode buffer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: 27th International Conference on Microelectronics, ICM 2015, Casablanca, Morocco, December 20-23, 2015, pp. 230-233, 2015, IEEE, 978-1-4673-8759-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
21 | Christian Weis, Matthias Jung 0001, Omar Naji, Norbert Wehn, Cristiano Santos, Pascal Vivet, Andreas Hansson 0001 |
Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2015 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015, Montpellier, France, July 8-10, 2015, pp. 609-614, 2015, IEEE Computer Society, 978-1-4799-8719-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
21 | Yiorgos Sfikas, Yiorgos Tsiatouhas, Mottaqiallah Taouil, Said Hamdioui |
On resistive open defect detection in DRAMs: The charge accumulation effect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 20th IEEE European Test Symposium, ETS 2015, Cluj-Napoca, Romania, 25-29 May, 2015, pp. 1-6, 2015, IEEE, 978-1-4799-7603-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
21 | Che-Wei Chou, Yong-Xiao Chen, Jin-Fu Li 0001 |
Testing Inter-Word Coupling Faults of Wide I/O DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 24th IEEE Asian Test Symposium, ATS 2015, Mumbai, India, November 22-25, 2015, pp. 67-72, 2015, IEEE Computer Society, 978-1-4673-9739-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
21 | Matthias Jung 0001, Éder Zulian, Deepak M. Mathew, Matthias Herrmann, Christian Brugger, Christian Weis, Norbert Wehn |
Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMSYS ![In: Proceedings of the 2015 International Symposium on Memory Systems, MEMSYS 2015, Washington DC, DC, USA, October 5-8, 2015, pp. 85-91, 2015, ACM, 978-1-4503-3604-8. The full citation details ...](Pics/full.jpeg) |
2015 |
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