Search results for "Gating"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
107	Fei Li 0003, Lei He 0001	Maximum current estimation considering power gating.	ISPD	2001	DBLP DOI BibTeX RDF	low-power design, ATPG, power estimation, power gating
95	Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija	Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements.	PATMOS	2008	DBLP DOI BibTeX RDF	Clocked storage elements, VLSI, power consumption, flip-flops, voltage scaling, clock gating, power gating, energy optimization, MTCMOS, circuit optimization, circuit tuning, circuit analysis
90	Chung-Yu Chang, Wei-Bin Yang, Ching-Ji Huang, Cheng-Hsing Chien	New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode.	ISCAS	2007	DBLP DOI BibTeX RDF
88	Ranan Fraer, Gila Kamhi, Muhammad K. Mhameed	A new paradigm for synthesis and propagation of clock gating conditions.	DAC	2008	DBLP DOI BibTeX RDF	low-power design, clock gating
88	Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee	Compilation for compact power-gating controls.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Compilers for low power, balanced scheduling, power-gating mechanisms, data-flow analysis, leakage-power reduction
88	Yingmin Li, Mark Hempstead, Patrick Mauro, David M. Brooks, Zhigang Hu, Kevin Skadron	Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices.	ISLPED	2005	DBLP DOI BibTeX RDF	architecture, power, temperature, clock gating
85	Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos	Efficient partial scan cell gating for low-power scan-based testing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	partial gating, scan cell gating, Low-power testing, scan-based testing
85	Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz	Experimental measurement of a novel power gating structure with intermediate power saving mode.	ISLPED	2004	DBLP DOI BibTeX RDF	system-on-a-chip (SOC) design, wake-up latency, clock gating, power gating, inductive noise, ground bounce
80	Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
80	Harmander Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka	Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
80	Peng Tu, David A. Padua	Efficient Building and Placing of Gating Functions.	PLDI	1995	DBLP DOI BibTeX RDF
78	Anja Niedermeier, Kjetil Svarstad, Frank Bouwens, Jos Hulzink, Jos Huisken	The challenges of implementing fine-grained power gating.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	leakage power minimization, analysis, power management, register-transfer-level, power modeling, power gating
78	Eli Arbel, Cindy Eisner, Oleg Rokhlenko	Resurrecting infeasible clock-gating functions.	DAC	2009	DBLP DOI BibTeX RDF	clustering, low power, approximation, clock gating
78	Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose	Microarchitectural techniques for power gating of execution units.	ISLPED	2004	DBLP DOI BibTeX RDF	execution units, low power, microarchitecture, power-gating
76	Tong Lin 0002, Laura I. Cervino, Xiaoli Tang, Nuno Vasconcelos, Steve B. Jiang	Tumor Targeting for Lung Cancer Radiotherapy Using Machine Learning Techniques.	ICMLA	2008	DBLP DOI BibTeX RDF
76	Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel	Understanding and minimizing ground bounce during mode transition of power gating structures.	ISLPED	2003	DBLP DOI BibTeX RDF	system-on-a-chip (SOC) design, wake-up latency, clock gating, power gating, inductive noise, ground bounce
74	Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee	A sink-n-hoist framework for leakage power reduction.	EMSOFT	2005	DBLP DOI BibTeX RDF	balanced scheduling, compilers for low power, power-gating mechanisms, data-flow analysis, leakage power reduction
71	Nainesh Agarwal, Nikitas J. Dimopoulos	DSPstone Benchmark of CoDeL's Automated Clock Gating Platform.	ISVLSI	2007	DBLP DOI BibTeX RDF
71	Philip Teichmann, Jürgen Fischer, Stephan Henzler, Ettore Amirante, Doris Schmitt-Landsiedel	Power-Clock Gating in Adiabatic Logic Circuits.	PATMOS	2005	DBLP DOI BibTeX RDF
71	Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler	Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.	HPCA	2005	DBLP DOI BibTeX RDF
71	Pilar Parra Fernández, Antonio J. Acosta 0001, Manuel Valencia-Barrero	Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1.	PATMOS	2002	DBLP DOI BibTeX RDF
69	Jun Seomun, Insup Shin, Youngsoo Shin	Synthesis and implementation of active mode power gating circuits.	DAC	2010	DBLP DOI BibTeX RDF	active leakage, active-mode power gating, low power
66	Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar	A critical-path-aware partial gating approach for test power reduction.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	partial gating, scan cell gating, Low-power testing, scan testing
66	Enrico Macii, Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino	Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits.	DSD	2008	DBLP DOI BibTeX RDF
61	Juanjuan Chen, Xing Wei, Yunjian Jiang, Qiang Zhou 0001	Improve clock gating through power-optimal enable function selection.	DDECS	2009	DBLP DOI BibTeX RDF
61	Ying Cui, Jennifer G. Dy, Gregory C. Sharp, Brian M. Alexander, Steve B. Jiang	Learning methods for lung tumor markerless gating in image-guided radiotherapy.	KDD	2008	DBLP DOI BibTeX RDF	applied machine learning, image-guided radiotherapy, clustering, classification, support vector machine, mixture model
61	Nainesh Agarwal, Nikitas J. Dimopoulos	Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction.	SAMOS	2007	DBLP DOI BibTeX RDF
61	Aida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang	Analysis and optimization of power-gated ICs with multiple power gating configurations.	ICCAD	2007	DBLP DOI BibTeX RDF
61	Vishwanadh Tirumalashetty, Hamid Mahmoodi	Clock Gating and Negative Edge Triggering for Energy Recovery Clock.	ISCAS	2007	DBLP DOI BibTeX RDF
61	Hailin Jiang, Malgorzata Marek-Sadowska	Power-Gating Aware Floorplanning.	ISQED	2007	DBLP DOI BibTeX RDF
61	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy 0001	Low-power scan design using first-level supply gating.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
61	Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif	Benefits and Costs of Power-Gating Technique.	ICCD	2005	DBLP DOI BibTeX RDF
55	Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	A low power VLIW processor generation method by means of extracting non-redundant activation conditions.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	low power, ASIP, clock gating, VLIW processor
52	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	A Scalable Algorithmic Framework for Row-Based Power-Gating.	DATE	2008	DBLP DOI BibTeX RDF
52	Carlo Gatta, Oriol Pujol, Oriol Rodriguez-Leor, Josepa Mauri, Petia Radeva	Robust Image-Based IVUS Pullbacks Gating.	MICCAI (2)	2008	DBLP DOI BibTeX RDF
52	Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula	Temperature and Process Variations Aware Power Gating of Functional Units.	VLSI Design	2008	DBLP DOI BibTeX RDF
52	Xiaotao Chang, Mingming Zhang, Ge Zhang 0007, Zhimin Zhang, Jun Wang	Adaptive Clock Gating Technique for Low Power IP Core in SoC Design.	ISCAS	2007	DBLP DOI BibTeX RDF
52	Nainesh Agarwal, Nikitas J. Dimopoulos	Efficient Automated Clock Gating Using CoDeL.	SAMOS	2006	DBLP DOI BibTeX RDF
52	Yan Zhang, Jussi Roivainen, Aarne Mämmelä	Clock-Gating in FPGAs: A Novel and Comparative Evaluation.	DSD	2006	DBLP DOI BibTeX RDF
52	Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy 0001	A Novel Low-Power Scan Design Technique Using Supply Gating.	ICCD	2004	DBLP DOI BibTeX RDF
50	Tak-Kei Lam, Steve Yang, Wai-Chung Tang, Yu-Liang Wu	Logic synthesis for low power using clock gating and rewiring.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	low power, logic synthesis, clock gating
50	Andrea Calimera, Enrico Macii, Massimo Poncino	NBTI-aware power gating for concurrent leakage and aging optimization.	ISLPED	2009	DBLP DOI BibTeX RDF	aging, leakage, power-gating, nbti
50	Liangpeng Guo, Yici Cai, Qiang Zhou 0001, Le Kang, Xianlong Hong	A novel performance driven power gating based on distributed sleep transistor network.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	physical design, power-gating, sleep transistors
50	Hailin Jiang, Malgorzata Marek-Sadowska	Power gating scheduling for power/ground noise reduction.	DAC	2008	DBLP DOI BibTeX RDF	scheduling, power gating, power supply noise
50	Hyung-Ock Kim, Youngsoo Shin, Hyuk Kim, Iksoo Eo	Physical design methodology of power gating circuits for standard-cell-based design.	DAC	2006	DBLP DOI BibTeX RDF	low power, leakage current, power gating
50	Hans M. Jacobson	Improved clock-gating through transparent pipelining.	ISLPED	2004	DBLP DOI BibTeX RDF	adaptive pipeline depth, dynamic pipeline scaling, optimal pipeline clocking, pipeline stage unification, transparent pipeline, low power, high performance, microarchitecture, circuits, clock gating
50	Jia Di, Jiann-Shiun Yuan	Power-aware pipelined multiplier design based on 2-dimensional pipeline gating.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	2-D pipeline gating, power-awareness, array multiplier
48	Haitham Akkary, Srikanth T. Srinivasan, Rajendar Koltur, Yogesh Patil, Wael Refaai	Perceptron-Based Branch Confidence Estimation.	HPCA	2004	DBLP DOI BibTeX RDF
48	Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose	Energy Efficient Co-Adaptive Instruction Fetch and Issue.	ISCA	2003	DBLP DOI BibTeX RDF
45	Yan Yang, Jinwen Ma	A Single Loop EM Algorithm for the Mixture of Experts Architecture.	ISNN (2)	2009	DBLP DOI BibTeX RDF	The mixture of experts (ME) architecture, The EM algorithm, Gating network, Single loop, Least mean square regression
45	Seungwhun Paik, Youngsoo Shin	Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements.	DAC	2008	DBLP DOI BibTeX RDF	sleep vector, zigzag power gating, low power, leakage current, standard-cell
45	Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi	Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm
45	Aida Todri, Shih-Chieh Chang, Malgorzata Marek-Sadowska	Electromigration and voltage drop aware power grid optimization for power gated ICs.	ISLPED	2007	DBLP DOI BibTeX RDF	power supply grid, power gating, electromigration
45	Yi-Ping You, Chingren Lee, Jenq Kuen Lee	Compilers for leakage power reduction.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Compilers for low power, power-gating mechanisms, leakage-power reduction
45	Eric L. Hill, Mikko H. Lipasti	Stall cycle redistribution in a transparent fetch pipeline.	ISLPED	2006	DBLP DOI BibTeX RDF	pipeline gating, microarchitecture, dynamic power, instruction fetch
45	Chunhong Chen, Changjun Kang, Majid Sarrafzadeh	Activity-sensitive clock tree construction for low power.	ISLPED	2002	DBLP DOI BibTeX RDF	low power, clock gating, clock tree, activity pattern
42	Hans Vandierendonck, André Seznec	Fetch Gating Control through Speculative Instruction Window Weighting.	Trans. High Perform. Embed. Archit. Compil.	2009	DBLP DOI BibTeX RDF
42	Li Li, Ken Choi, Seongmo Park, MooKyung Chung	Selective clock gating by using wasting toggle rate.	EIT	2009	DBLP DOI BibTeX RDF
42	Shih-Hsu Huang, Chun-Hua Cheng	Timing driven power gating in high-level synthesis.	ASP-DAC	2009	DBLP DOI BibTeX RDF
42	Jithendra Srinivas, Madhusudan Rao, Sukumar Jairam, H. Udayakumar, Jagdish C. Rao	Clock gating effectiveness metrics: Applications to power optimization.	ISQED	2009	DBLP DOI BibTeX RDF
42	Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi	An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition.	ISQED	2009	DBLP DOI BibTeX RDF
42	Ehsan Pakbaznia, Massoud Pedram	Design and application of multimodal power gating structures.	ISQED	2009	DBLP DOI BibTeX RDF
42	Eli Arbel, Oleg Rokhlenko, Karen Yorav	SAT-based synthesis of clock gating functions using 3-valued abstraction.	FMCAD	2009	DBLP DOI BibTeX RDF
42	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating.	PATMOS	2008	DBLP DOI BibTeX RDF
42	Yu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang	A novel sequential circuit optimization with clock gating logic.	ICCAD	2008	DBLP DOI BibTeX RDF
42	Petr Kadlec, Bogdan Gabrys	Learnt Topology Gating Artificial Neural Networks.	IJCNN	2008	DBLP DOI BibTeX RDF
42	Ku He, Rong Luo, Yu Wang 0002	A power gating scheme for ground bounce reduction during mode transition.	ICCD	2007	DBLP DOI BibTeX RDF
42	Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki	An automated runtime power-gating scheme.	ICCD	2007	DBLP DOI BibTeX RDF
42	Sukmoon Chang, Jinghao Zhou, Qingshan Liu 0001, Dimitris N. Metaxas, Bruce G. Haffty, Sung N. Kim, Salma J. Jabbour, Ning J. Yue	Registration of Lung Tissue Between Fluoroscope and CT Images: Determination of Beam Gating Parameters in Radiotherapy.	MICCAI (1)	2007	DBLP DOI BibTeX RDF
42	Hans Vandierendonck, André Seznec	Fetch Gating Control Through Speculative Instruction Window Weighting.	HiPEAC	2007	DBLP DOI BibTeX RDF
42	Hyung-Ock Kim, Youngsoo Shin	Analysis and optimization of gate leakage current of power gating circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF
42	Kanak Agarwal, Kevin J. Nowka, Harmander Deogun, Dennis Sylvester	Power Gating with Multiple Sleep Modes.	ISQED	2006	DBLP DOI BibTeX RDF
42	Changbo Long, Jinjun Xiong, Yongpan Liu	Techniques of Power-gating to Kill Sub-Threshold Leakage.	APCCAS	2006	DBLP DOI BibTeX RDF
42	Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson	A low-leakage twin-precision multiplier using reconfigurable power gating.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
42	Martin von Siebenthal, Philippe C. Cattin, U. Gamper, Alan J. Lomax, Gábor Székely	4D MR Imaging Using Internal Respiratory Gating.	MICCAI (2)	2005	DBLP DOI BibTeX RDF
42	Ramon Canal, Antonio González 0001, James E. Smith 0001	Software-Controlled Operand-Gating.	CGO	2004	DBLP DOI BibTeX RDF
42	Karen A. Moxon, Greg A. Gerhardt, Maria Gulinello, Lawrence E. Adler	Inhibitory control of sensory gating in a computer model of the CA3 region of the hippocampus.	Biol. Cybern.	2003	DBLP DOI BibTeX RDF
42	Karen A. Moxon, Greg A. Gerhardt, Lawrence E. Adler	Dopaminergic modulation of the P50 auditory-evoked potential in a computer model of the CA3 region of the hippocampus: its relationship to sensory gating in schizophrenia.	Biol. Cybern.	2003	DBLP DOI BibTeX RDF
40	Martin Saint-Laurent, Animesh Datta	A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology.	ISLPED	2010	DBLP DOI BibTeX RDF	clock gater, clock gating cell, local clock buffer, set-reset latch
40	Seungwhun Paik, Sangmin Kim, Youngsoo Shin	Wakeup synthesis and its buffered tree construction for power gating circuit designs.	ISLPED	2010	DBLP DOI BibTeX RDF	wakeup synthesis, leakage, power gating
40	Rahul Singh, AhReum Kim, SoYoung Kim, Suhwan Kim	A three-step power-gating turn-on technique for controlling ground bounce noise.	ISLPED	2010	DBLP DOI BibTeX RDF	mode transition, system-on-a-chip (SOC) design, power-gating, inductive noise, ground bounce
40	Anita Lungu, Pradip Bose, Alper Buyuktosunoglu, Daniel J. Sorin	Dynamic power gating with quality guarantees.	ISLPED	2009	DBLP DOI BibTeX RDF	execution units, low power, power management, microarchitecture, power gating
40	Jungseob Lee, Nam Sung Kim	Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating.	DAC	2009	DBLP DOI BibTeX RDF	multicore processor, DVFS, power gating
40	Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy 0001	Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Enhanced scan, Supply gating, Delay fault testing, Two-pattern testing
40	Aaron P. Hurst	Automatic synthesis of clock gating logic with controlled netlist perturbation.	DAC	2008	DBLP DOI BibTeX RDF	low power, clock gating, logic optimization, dynamic power
40	De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh	Timing driven power gating.	DAC	2006	DBLP DOI BibTeX RDF	leakage current, power gating, IR drop
38	Ramkumar Jayaseelan, Tulika Mitra	Dynamic thermal management via architectural adaptation.	DAC	2009	DBLP DOI BibTeX RDF	architecture adaptation, dynamic thermal management
38	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Gate planning during placement for gated clock network.	ICCD	2008	DBLP DOI BibTeX RDF
38	Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi	Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
38	Pietro Babighian, Luca Benini, Enrico Macii	A scalable algorithm for RTL insertion of gated clocks based on ODCs computation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
38	Philippe Manet, David Bol, Renaud Ambroise, Jean-Didier Legat	Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications.	PATMOS	2005	DBLP DOI BibTeX RDF
38	Juan Chen 0001, Yong Dong, Huizhan Yi, Xuejun Yang	Power Consumption Analysis of Embedded Multimedia Application.	ICESS	2005	DBLP DOI BibTeX RDF
38	Nithya Raghavan, Venkatesh Akella, Smita Bakshi	Automatic Insertion of Gated Clocks at Register Transfer Level.	VLSI Design	1999	DBLP DOI BibTeX RDF
36	Ashutosh Chakraborty, David Z. Pan	Skew management of NBTI impacted gated clock trees.	ISPD	2010	DBLP DOI BibTeX RDF	clock skew, clock gating, NBTI
36	Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shayan Arani, A. Ege Engin, Chung-Kuan Cheng	Predicting the worst-case voltage violation in a 3D power network.	SLIP	2009	DBLP DOI BibTeX RDF	worst case violation prediction, integer linear programming, leakage, clock gating, power networks
36	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Optimal sleep transistor synthesis under timing and area constraints.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
36	Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee	Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling.	ASP-DAC	2007	DBLP DOI BibTeX RDF	wire-length driven floorplan, noise-direct, power supply noise aware floorplanning, microarchitecture profiling, aggressive power saving techniques, power delivery network, power consumption reduction, self weighting, correlation weighting, force-directed floorplanning algorithm, power pin affinity, current consumption, di/dt control, supply-noise margin violations, clock-gating, microprocessor designers, power constraints, inductive noise, decoupling capacitances
36	Dharmesh Parikh, Kevin Skadron, Yan Zhang 0028, Mircea R. Stan	Power-Aware Branch Prediction: Characterization and Design.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	target prediction, highly-biased branches, pipeline gating, speculation control, Low-power design, power, branch prediction, processor architecture, energy-aware systems, banking
36	Wael El-Essawy, David H. Albonesi, Balaram Sinharoy	A microarchitectural-level step-power analysis tool.	ISLPED	2002	DBLP DOI BibTeX RDF	Ldi/dt, step-power, microprocessors, clock-gating, architectural simulation, inductive noise
34	Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg	A case for dynamic pipeline scaling.	CASES	2002	DBLP DOI BibTeX RDF	configurable pipeline, fetch gating, power and energy management, shallow and deep pipelines, variable-depth pipeline, dynamic voltage scaling, clock gating