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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 519 occurrences of 286 keywords
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Results
Found 1650 publication records. Showing 1650 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
107 | Fei Li 0003, Lei He 0001 |
Maximum current estimation considering power gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001, pp. 106-111, 2001, ACM, 1-58113-347-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
low-power design, ATPG, power estimation, power gating |
95 | Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija |
Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 268-276, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Clocked storage elements, VLSI, power consumption, flip-flops, voltage scaling, clock gating, power gating, energy optimization, MTCMOS, circuit optimization, circuit tuning, circuit analysis |
90 | Chung-Yu Chang, Wei-Bin Yang, Ching-Ji Huang, Cheng-Hsing Chien |
New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3740-3743, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
88 | Ranan Fraer, Gila Kamhi, Muhammad K. Mhameed |
A new paradigm for synthesis and propagation of clock gating conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 658-663, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
low-power design, clock gating |
88 | Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee |
Compilation for compact power-gating controls. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(4), pp. 51, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Compilers for low power, balanced scheduling, power-gating mechanisms, data-flow analysis, leakage-power reduction |
88 | Yingmin Li, Mark Hempstead, Patrick Mauro, David M. Brooks, Zhigang Hu, Kevin Skadron |
Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 173-178, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
architecture, power, temperature, clock gating |
85 | Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos |
Efficient partial scan cell gating for low-power scan-based testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(2), pp. 28:1-28:15, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
partial gating, scan cell gating, Low-power testing, scan-based testing |
85 | Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz |
Experimental measurement of a novel power gating structure with intermediate power saving mode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 20-25, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
system-on-a-chip (SOC) design, wake-up latency, clock gating, power gating, inductive noise, ground bounce |
80 | Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2761-2764, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
80 | Harmander Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka |
Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(11), pp. 1215-1224, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
80 | Peng Tu, David A. Padua |
Efficient Building and Placing of Gating Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'95 Conference on Programming Language Design and Implementation (PLDI), La Jolla, California, USA, June 18-21, 1995, pp. 47-55, 1995, ACM, 0-89791-697-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
78 | Anja Niedermeier, Kjetil Svarstad, Frank Bouwens, Jos Hulzink, Jos Huisken |
The challenges of implementing fine-grained power gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 361-364, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
leakage power minimization, analysis, power management, register-transfer-level, power modeling, power gating |
78 | Eli Arbel, Cindy Eisner, Oleg Rokhlenko |
Resurrecting infeasible clock-gating functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 160-165, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
clustering, low power, approximation, clock gating |
78 | Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose |
Microarchitectural techniques for power gating of execution units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 32-37, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
execution units, low power, microarchitecture, power-gating |
76 | Tong Lin 0002, Laura I. Cervino, Xiaoli Tang, Nuno Vasconcelos, Steve B. Jiang |
Tumor Targeting for Lung Cancer Radiotherapy Using Machine Learning Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMLA ![In: Seventh International Conference on Machine Learning and Applications, ICMLA 2008, San Diego, California, USA, 11-13 December 2008, pp. 533-538, 2008, IEEE Computer Society, 978-0-7695-3495-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
76 | Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel |
Understanding and minimizing ground bounce during mode transition of power gating structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 22-25, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
system-on-a-chip (SOC) design, wake-up latency, clock gating, power gating, inductive noise, ground bounce |
74 | Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee |
A sink-n-hoist framework for leakage power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: EMSOFT 2005, September 18-22, 2005, Jersey City, NJ, USA, 5th ACM International Conference On Embedded Software, Proceedings, pp. 124-133, 2005, ACM, 1-59593-091-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
balanced scheduling, compilers for low power, power-gating mechanisms, data-flow analysis, leakage power reduction |
71 | Nainesh Agarwal, Nikitas J. Dimopoulos |
DSPstone Benchmark of CoDeL's Automated Clock Gating Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 508-509, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
71 | Philip Teichmann, Jürgen Fischer, Stephan Henzler, Ettore Amirante, Doris Schmitt-Landsiedel |
Power-Clock Gating in Adiabatic Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 638-646, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
71 | Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler |
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA, pp. 238-242, 2005, IEEE Computer Society, 0-7695-2275-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
71 | Pilar Parra Fernández, Antonio J. Acosta 0001, Manuel Valencia-Barrero |
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002, pp. 448-457, 2002, Springer, 3-540-44143-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
69 | Jun Seomun, Insup Shin, Youngsoo Shin |
Synthesis and implementation of active mode power gating circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 487-492, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
active leakage, active-mode power gating, low power |
66 | Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar |
A critical-path-aware partial gating approach for test power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(2), pp. 17, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
partial gating, scan cell gating, Low-power testing, scan testing |
66 | Enrico Macii, LetÃcia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino |
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 298-303, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
61 | Juanjuan Chen, Xing Wei, Yunjian Jiang, Qiang Zhou 0001 |
Improve clock gating through power-optimal enable function selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 30-33, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
61 | Ying Cui, Jennifer G. Dy, Gregory C. Sharp, Brian M. Alexander, Steve B. Jiang |
Learning methods for lung tumor markerless gating in image-guided radiotherapy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KDD ![In: Proceedings of the 14th ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, Las Vegas, Nevada, USA, August 24-27, 2008, pp. 902-910, 2008, ACM, 978-1-60558-193-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
applied machine learning, image-guided radiotherapy, clustering, classification, support vector machine, mixture model |
61 | Nainesh Agarwal, Nikitas J. Dimopoulos |
Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings, pp. 294-303, 2007, Springer, 978-3-540-73622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
61 | Aida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang |
Analysis and optimization of power-gated ICs with multiple power gating configurations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 783-790, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
61 | Vishwanadh Tirumalashetty, Hamid Mahmoodi |
Clock Gating and Negative Edge Triggering for Energy Recovery Clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1141-1144, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
61 | Hailin Jiang, Malgorzata Marek-Sadowska |
Power-Gating Aware Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 853-860, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
61 | Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy 0001 |
Low-power scan design using first-level supply gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(3), pp. 384-395, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
61 | Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif |
Benefits and Costs of Power-Gating Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 559-566, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
55 | Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
A low power VLIW processor generation method by means of extracting non-redundant activation conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 227-232, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
low power, ASIP, clock gating, VLIW processor |
52 | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
A Scalable Algorithmic Framework for Row-Based Power-Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 379-384, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
52 | Carlo Gatta, Oriol Pujol, Oriol Rodriguez-Leor, Josepa Mauri, Petia Radeva |
Robust Image-Based IVUS Pullbacks Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICCAI (2) ![In: Medical Image Computing and Computer-Assisted Intervention - MICCAI 2008, 11th International Conference, New York, NY, USA, September 6-10, 2008, Proceedings, Part II, pp. 518-525, 2008, Springer, 978-3-540-85989-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
52 | Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
Temperature and Process Variations Aware Power Gating of Functional Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 515-520, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
52 | Xiaotao Chang, Mingming Zhang, Ge Zhang 0007, Zhimin Zhang, Jun Wang |
Adaptive Clock Gating Technique for Low Power IP Core in SoC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2120-2123, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
52 | Nainesh Agarwal, Nikitas J. Dimopoulos |
Efficient Automated Clock Gating Using CoDeL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings, pp. 79-88, 2006, Springer, 3-540-36410-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
52 | Yan Zhang, Jussi Roivainen, Aarne Mämmelä |
Clock-Gating in FPGAs: A Novel and Comparative Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 584-590, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
52 | Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy 0001 |
A Novel Low-Power Scan Design Technique Using Supply Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 60-65, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
50 | Tak-Kei Lam, Steve Yang, Wai-Chung Tang, Yu-Liang Wu |
Logic synthesis for low power using clock gating and rewiring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 179-184, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
low power, logic synthesis, clock gating |
50 | Andrea Calimera, Enrico Macii, Massimo Poncino |
NBTI-aware power gating for concurrent leakage and aging optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 127-132, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
aging, leakage, power-gating, nbti |
50 | Liangpeng Guo, Yici Cai, Qiang Zhou 0001, Le Kang, Xianlong Hong |
A novel performance driven power gating based on distributed sleep transistor network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 255-260, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
physical design, power-gating, sleep transistors |
50 | Hailin Jiang, Malgorzata Marek-Sadowska |
Power gating scheduling for power/ground noise reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 980-985, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
scheduling, power gating, power supply noise |
50 | Hyung-Ock Kim, Youngsoo Shin, Hyuk Kim, Iksoo Eo |
Physical design methodology of power gating circuits for standard-cell-based design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 109-112, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
low power, leakage current, power gating |
50 | Hans M. Jacobson |
Improved clock-gating through transparent pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 26-31, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
adaptive pipeline depth, dynamic pipeline scaling, optimal pipeline clocking, pipeline stage unification, transparent pipeline, low power, high performance, microarchitecture, circuits, clock gating |
50 | Jia Di, Jiann-Shiun Yuan |
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 64-67, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
2-D pipeline gating, power-awareness, array multiplier |
48 | Haitham Akkary, Srikanth T. Srinivasan, Rajendar Koltur, Yogesh Patil, Wael Refaai |
Perceptron-Based Branch Confidence Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 14-18 February 2004, Madrid, Spain, pp. 265-275, 2004, IEEE Computer Society, 0-7695-2053-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
48 | Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose |
Energy Efficient Co-Adaptive Instruction Fetch and Issue. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, pp. 147-156, 2003, IEEE Computer Society, 0-7695-1945-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
45 | Yan Yang, Jinwen Ma |
A Single Loop EM Algorithm for the Mixture of Experts Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (2) ![In: Advances in Neural Networks - ISNN 2009, 6th International Symposium on Neural Networks, ISNN 2009, Wuhan, China, May 26-29, 2009, Proceedings, Part II, pp. 959-968, 2009, Springer, 978-3-642-01509-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
The mixture of experts (ME) architecture, The EM algorithm, Gating network, Single loop, Least mean square regression |
45 | Seungwhun Paik, Youngsoo Shin |
Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 600-605, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
sleep vector, zigzag power gating, low power, leakage current, standard-cell |
45 | Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi |
Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 654-659, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm |
45 | Aida Todri, Shih-Chieh Chang, Malgorzata Marek-Sadowska |
Electromigration and voltage drop aware power grid optimization for power gated ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 391-394, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
power supply grid, power gating, electromigration |
45 | Yi-Ping You, Chingren Lee, Jenq Kuen Lee |
Compilers for leakage power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(1), pp. 147-164, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Compilers for low power, power-gating mechanisms, leakage-power reduction |
45 | Eric L. Hill, Mikko H. Lipasti |
Stall cycle redistribution in a transparent fetch pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 31-36, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
pipeline gating, microarchitecture, dynamic power, instruction fetch |
45 | Chunhong Chen, Changjun Kang, Majid Sarrafzadeh |
Activity-sensitive clock tree construction for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 279-282, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
low power, clock gating, clock tree, activity pattern |
42 | Hans Vandierendonck, André Seznec |
Fetch Gating Control through Speculative Instruction Window Weighting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. High Perform. Embed. Archit. Compil. ![In: Transactions on High-Performance Embedded Architectures and Compilers II, pp. 128-148, 2009, Springer, 978-3-642-00903-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Li Li, Ken Choi, Seongmo Park, MooKyung Chung |
Selective clock gating by using wasting toggle rate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2009 IEEE International Conference on Electro/Information Technology, EIT 2009, Windsor, Ontario, Canada, June 7-9, 2009, pp. 399-404, 2009, IEEE, 978-1-4244-3355-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Shih-Hsu Huang, Chun-Hua Cheng |
Timing driven power gating in high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 173-178, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Jithendra Srinivas, Madhusudan Rao, Sukumar Jairam, H. Udayakumar, Jagdish C. Rao |
Clock gating effectiveness metrics: Applications to power optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 482-487, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi |
An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 116-119, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Ehsan Pakbaznia, Massoud Pedram |
Design and application of multimodal power gating structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 120-126, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Eli Arbel, Oleg Rokhlenko, Karen Yorav |
SAT-based synthesis of clock gating functions using 3-valued abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2009, 15-18 November 2009, Austin, Texas, USA, pp. 198-204, 2009, IEEE, 978-1-4244-4966-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 42-51, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
42 | Yu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang |
A novel sequential circuit optimization with clock gating logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 230-233, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
42 | Petr Kadlec, Bogdan Gabrys |
Learnt Topology Gating Artificial Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN ![In: Proceedings of the International Joint Conference on Neural Networks, IJCNN 2008, part of the IEEE World Congress on Computational Intelligence, WCCI 2008, Hong Kong, China, June 1-6, 2008, pp. 2604-2611, 2008, IEEE, 978-1-4244-1820-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
42 | Ku He, Rong Luo, Yu Wang 0002 |
A power gating scheme for ground bounce reduction during mode transition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 388-394, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki |
An automated runtime power-gating scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 382-387, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Sukmoon Chang, Jinghao Zhou, Qingshan Liu 0001, Dimitris N. Metaxas, Bruce G. Haffty, Sung N. Kim, Salma J. Jabbour, Ning J. Yue |
Registration of Lung Tissue Between Fluoroscope and CT Images: Determination of Beam Gating Parameters in Radiotherapy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICCAI (1) ![In: Medical Image Computing and Computer-Assisted Intervention - MICCAI 2007, 10th International Conference, Brisbane, Australia, October 29 - November 2, 2007, Proceedings, Part I, pp. 751-758, 2007, Springer, 978-3-540-75756-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Hans Vandierendonck, André Seznec |
Fetch Gating Control Through Speculative Instruction Window Weighting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings, pp. 120-135, 2007, Springer, 978-3-540-69337-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Hyung-Ock Kim, Youngsoo Shin |
Analysis and optimization of gate leakage current of power gating circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 565-569, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Kanak Agarwal, Kevin J. Nowka, Harmander Deogun, Dennis Sylvester |
Power Gating with Multiple Sleep Modes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 633-637, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Changbo Long, Jinjun Xiong, Yongpan Liu |
Techniques of Power-gating to Kill Sub-Threshold Leakage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 952-955, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson |
A low-leakage twin-precision multiplier using reconfigurable power gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1654-1657, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
42 | Martin von Siebenthal, Philippe C. Cattin, U. Gamper, Alan J. Lomax, Gábor Székely |
4D MR Imaging Using Internal Respiratory Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICCAI (2) ![In: Medical Image Computing and Computer-Assisted Intervention - MICCAI 2005, 8th International Conference, Palm Springs, CA, USA, October 26-29, 2005, Proceedings, Part II, pp. 336-343, 2005, Springer, 3-540-29326-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
42 | Ramon Canal, Antonio González 0001, James E. Smith 0001 |
Software-Controlled Operand-Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 125-136, 2004, IEEE Computer Society, 0-7695-2102-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
42 | Karen A. Moxon, Greg A. Gerhardt, Maria Gulinello, Lawrence E. Adler |
Inhibitory control of sensory gating in a computer model of the CA3 region of the hippocampus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Biol. Cybern. ![In: Biol. Cybern. 88(4), pp. 247-264, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
42 | Karen A. Moxon, Greg A. Gerhardt, Lawrence E. Adler |
Dopaminergic modulation of the P50 auditory-evoked potential in a computer model of the CA3 region of the hippocampus: its relationship to sensory gating in schizophrenia. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Biol. Cybern. ![In: Biol. Cybern. 88(4), pp. 265-275, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
40 | Martin Saint-Laurent, Animesh Datta |
A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 159-164, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
clock gater, clock gating cell, local clock buffer, set-reset latch |
40 | Seungwhun Paik, Sangmin Kim, Youngsoo Shin |
Wakeup synthesis and its buffered tree construction for power gating circuit designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 413-418, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
wakeup synthesis, leakage, power gating |
40 | Rahul Singh, AhReum Kim, SoYoung Kim, Suhwan Kim |
A three-step power-gating turn-on technique for controlling ground bounce noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 171-176, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
mode transition, system-on-a-chip (SOC) design, power-gating, inductive noise, ground bounce |
40 | Anita Lungu, Pradip Bose, Alper Buyuktosunoglu, Daniel J. Sorin |
Dynamic power gating with quality guarantees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 377-382, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
execution units, low power, power management, microarchitecture, power gating |
40 | Jungseob Lee, Nam Sung Kim |
Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 47-50, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
multicore processor, DVFS, power gating |
40 | Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy 0001 |
Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(6), pp. 577-590, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Enhanced scan, Supply gating, Delay fault testing, Two-pattern testing |
40 | Aaron P. Hurst |
Automatic synthesis of clock gating logic with controlled netlist perturbation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 654-657, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
low power, clock gating, logic optimization, dynamic power |
40 | De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh |
Timing driven power gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 121-124, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
leakage current, power gating, IR drop |
38 | Ramkumar Jayaseelan, Tulika Mitra |
Dynamic thermal management via architectural adaptation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 484-489, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
architecture adaptation, dynamic thermal management |
38 | Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu |
Gate planning during placement for gated clock network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 128-133, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi |
Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(7), pp. 758-766, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Pietro Babighian, Luca Benini, Enrico Macii |
A scalable algorithm for RTL insertion of gated clocks based on ODCs computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(1), pp. 29-42, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Philippe Manet, David Bol, Renaud Ambroise, Jean-Didier Legat |
Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 19-29, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Juan Chen 0001, Yong Dong, Huizhan Yi, Xuejun Yang |
Power Consumption Analysis of Embedded Multimedia Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, Second International Conference, ICESS 2005, Xi'an, China, December 16-18, 2005, Proceedings, pp. 596-607, 2005, Springer, 3-540-30881-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Nithya Raghavan, Venkatesh Akella, Smita Bakshi |
Automatic Insertion of Gated Clocks at Register Transfer Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 48-54, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
36 | Ashutosh Chakraborty, David Z. Pan |
Skew management of NBTI impacted gated clock trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 127-133, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
clock skew, clock gating, NBTI |
36 | Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shayan Arani, A. Ege Engin, Chung-Kuan Cheng |
Predicting the worst-case voltage violation in a 3D power network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 93-98, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
worst case violation prediction, integer linear programming, leakage, clock gating, power networks |
36 | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Optimal sleep transistor synthesis under timing and area constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 177-182, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
row-based, clustering, leakage power, power-gating, standard cell, sleep transistor |
36 | Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee |
Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 786-791, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
wire-length driven floorplan, noise-direct, power supply noise aware floorplanning, microarchitecture profiling, aggressive power saving techniques, power delivery network, power consumption reduction, self weighting, correlation weighting, force-directed floorplanning algorithm, power pin affinity, current consumption, di/dt control, supply-noise margin violations, clock-gating, microprocessor designers, power constraints, inductive noise, decoupling capacitances |
36 | Dharmesh Parikh, Kevin Skadron, Yan Zhang 0028, Mircea R. Stan |
Power-Aware Branch Prediction: Characterization and Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(2), pp. 168-186, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
target prediction, highly-biased branches, pipeline gating, speculation control, Low-power design, power, branch prediction, processor architecture, energy-aware systems, banking |
36 | Wael El-Essawy, David H. Albonesi, Balaram Sinharoy |
A microarchitectural-level step-power analysis tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 263-266, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Ldi/dt, step-power, microprocessors, clock-gating, architectural simulation, inductive noise |
34 | Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg |
A case for dynamic pipeline scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 1-8, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
configurable pipeline, fetch gating, power and energy management, shallow and deep pipelines, variable-depth pipeline, dynamic voltage scaling, clock gating |
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