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1959-1971 (20) 1972-1975 (16) 1976-1977 (20) 1978-1979 (20) 1980-1981 (32) 1982 (25) 1983 (27) 1984 (37) 1985 (74) 1986 (48) 1987 (62) 1988 (82) 1989 (98) 1990 (141) 1991 (93) 1992 (87) 1993 (126) 1994 (92) 1995 (181) 1996 (154) 1997 (169) 1998 (201) 1999 (275) 2000 (248) 2001 (303) 2002 (386) 2003 (400) 2004 (490) 2005 (540) 2006 (550) 2007 (631) 2008 (574) 2009 (424) 2010 (259) 2011 (227) 2012 (227) 2013 (252) 2014 (253) 2015 (259) 2016 (265) 2017 (290) 2018 (315) 2019 (331) 2020 (351) 2021 (407) 2022 (390) 2023 (514) 2024 (110)
Publication types (Num. hits)
article(3614) book(9) data(3) incollection(68) inproceedings(7258) phdthesis(123) proceedings(1)
Venues (Conferences, Journals, ...)
CoRR(514) DAC(463) IEEE Trans. Comput. Aided Des....(412) ICCAD(186) ICDAR(166) GD(139) ASP-DAC(135) VLSI Design(115) IEEE Trans. Very Large Scale I...(113) ISPD(112) ISQED(112) ISCAS(109) DATE(102) IEEE Trans. Vis. Comput. Graph...(89) WSC(74) IEEE Trans. Computers(73) More (+10 of total 2371)
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The graphs summarize 6705 occurrences of 3042 keywords

Results
Found 11076 publication records. Showing 11076 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
94Louis Monier, Ramsey W. Haddad, Jeremy Dion Recursive layout generation. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF BiCMOS digital integrated circuits, recursive layout generation, layout directives, netlist description, hand-drawn layout, synthesized layout, overall layout, dense VLSI, VLSI, logic CAD, circuit layout CAD, microprocessor chips, microprocessor chips, VLSI chips, seamless integration
82Ken Kennedy, Ulrich Kremer Automatic Data Layout for Distributed-Memory Machines. Search on Bibsonomy ACM Trans. Program. Lang. Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF high performance Fortran
81Neff Walker, John B. Smelcer A comparison of selection time from walking and pull-down menus. Search on Bibsonomy CHI The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
81Terry Winograd What can we teach about human-computer interaction? (plenary address). Search on Bibsonomy CHI The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
81Hans Brunner A snapshot of natural language interfaces (panel). Search on Bibsonomy CHI The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
81Jakob Nielsen Designing for international use (panel). Search on Bibsonomy CHI The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
81S. Joy Mountford Designers: meet your users (panel). Search on Bibsonomy CHI The full citation details ... 1990 DBLP  DOI  BibTeX  RDF Apple Computer, HyperCard, Inc
81Marcy Telles Updating an older interface. Search on Bibsonomy CHI The full citation details ... 1990 DBLP  DOI  BibTeX  RDF WordStar
74Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri A high level language for pre-layout extraction in parasite-aware analog circuit synthesis. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF MSL, pre-layout extraction, parasitics, analog VLSI
74Andrew Sears Layout Appropriateness: A Metric for Evaluating User Interface Widget Layout. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF layout appropriateness, user interface widget layout, simple task descriptions, Layout Appropriateness, simplified task analysis, LA-optimal layout, performance evaluation, user interfaces, human factors, software metrics, weighting
70Neungsoo Park, Bo Hong, Viktor K. Prasanna Tiling, Block Data Layout, and Memory Hierarchy Performance. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Block data layout, TLB misses, memory hierarchy, tiling, cache misses
70Peter Lüders, Rolf Ernst Research report: improving browsing in information by the automatic display layout. Search on Bibsonomy INFOVIS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF automatic display layout, graph structured information, automatic layout system, time consuming, manual layout, user requests, display layouts, information retrieval, graphical user interfaces, user modelling, user model, human factors, computer animation, information network, graphical representations, information browsing, layout algorithms
70Sanjay Rekhi, J. Donald Trotter HAL: heuristic algorithms for layout synthesis. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF layout synthesis, graph theory based algorithms, leaf cells, common poly gates, 1-1/2-d layout style, common circuit nodes, transistor sets, symbolic layouts, static dual type, static CMOS circuitry, pullup network, pulldown network, dynamic logic styles, graph theory, network topology, logic CAD, heuristic algorithms, circuit layout CAD, CMOS logic circuits, CMOS circuits, GENIE, run time efficient, layout area
67Akira Matsubayashi VLSI layout of trees into grids of minimum width. Search on Bibsonomy SPAA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF cutwidth, grid, tree, graph embedding, VLSI layout, graph layout, aspect ratio
64Hart Anway, Greg Farnham, Rebecca Reid PLINT layout system for VLSI chips. Search on Bibsonomy DAC The full citation details ... 1985 DBLP  DOI  BibTeX  RDF IC placement, IC routing, macrocell layout, standard cell layout, VLSI, computer-aided design, IC layout
62Syed M. Alam, Donald E. Troxel, Carl V. Thompson A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated Circuits. Search on Bibsonomy ISQED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF 3D integrated circuit, 3D IC layout, inter-wafer via, reliability CAD tool, FPGA, performance analysis, reliability analysis
60Shuo Zhang, Wayne Wei-Ming Dai TEG: a new post-layout optimization method. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
59Toyohide Watanabe, Qin Luo, Noboru Sugie Layout Recognition of Multi-Kinds of Table-Form Documents. Search on Bibsonomy IEEE Trans. Pattern Anal. Mach. Intell. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Recognition paradigm for multi-kinds of table-form documents, automatic acquisition of layout knowledge, recognition of document classes, recognition of layout structures, structure description tree, classification tree
57Oguzhan Ozmen, Kenneth Salem, Jiri Schindler, Steve Daniel Workload-aware storage layout for database systems. Search on Bibsonomy SIGMOD Conference The full citation details ... 2010 DBLP  DOI  BibTeX  RDF layout, physical design, storage systems
56Tim Dwyer, Kim Marriott, Falk Schreiber, Peter J. Stuckey, Michael Woodward, Michael Wybrow Exploration of Networks using overview+detail with Constraint-based cooperative layout. Search on Bibsonomy IEEE Trans. Vis. Comput. Graph. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
55Frederik Beeftink, Arjan J. van Genderen, N. P. van der Meijs Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF MOS integrated circuits, bipolar integrated circuits, BiCMOS integrated circuits, layout-to-circuit extraction, high-speed MOS integrated circuits, bipolar/BiCMOS integrated circuits, device recognition, equivalent network, layout parasitics, interconnects, circuit analysis computing, circuit layout CAD, Space, Spice, device modeling
54Tiziana Calamoneri, Annalisa Massini Nearly Optimal Three Dimensional Layout of Hypercube Networks. Search on Bibsonomy GD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Three Dimensional Layout, VLSI layout volume, Hypercube Network
54Mohamed Dessouky, Marie-Minerve Louërat A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits. Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Analog layout, layout generation
54Joni Dambre, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout On rent's rule for rectangular regions. Search on Bibsonomy SLIP The full citation details ... 2001 DBLP  DOI  BibTeX  RDF layout Rent parameters, rectangular layout region, wirelength distribution, Rent's rule
52Masahiro Nagamatu, Shakeel Ismail, Torao Yanaru Lagrangian method for wire routing of layout design. Search on Bibsonomy ANNES The full citation details ... 1995 DBLP  DOI  BibTeX  RDF wire routing, layout design, LSI layout design, continuous valued constrained optimization problem, continuous valued wires, dynamic equations, small switchbox routing problems, rip-up reroute maze router, neural nets, network routing, circuit layout CAD, circuit optimisation, integrated circuit layout, large scale integration, neurocomputing, Lagrangian method
52Chengliang Zhang, Martin Hirzel Online Phase-Adaptive Data Layout Selection. Search on Bibsonomy ECOOP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
52Takayoshi Noguchi, Jiro Tanaka Interactive Layout Method for Object Diagrams of OMT. Search on Bibsonomy APSEC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF software development tool, object-oriented methodology
51Jin-Tai Yan A simple yet effective genetic approach for the orientation assignment on cell-based layout. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF genetic approach, orientation assignment, cell-based layout, total wire length minimisation, placement phase, routing area reduction, orientation states, vertical orientation bit, horizontal orientation bit, genetic algorithms, VLSI, VLSI design, network routing, circuit layout CAD, integrated circuit layout
51Winfried Graf, Stefan Neurohr Constraint-Based Layout in Visual Program Design. Search on Bibsonomy VL The full citation details ... 1995 DBLP  DOI  BibTeX  RDF visual program design, constraint-based layout, visual program layout, graphical editing tasks, InLay constraint-based graphical editor, animated chart diagram layout, presentation part abstraction, active display object focussing, graphical history editing, hierarchical information structure visualisation, multimedia, data structures, knowledge based systems, interaction techniques, programming environments, visual programming, computer animation, intelligent system, data visualisation, multimedia computing, program visualization, constraint handling, visual programming environments, dynamic displays, communication media
51Nikolaos G. Bourbakis, Mohammad Mortazavi An efficient building block layout methodology for compact placement. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF building block layout methodology, compact placement, synthesis placement, GEOMETRIA, geometric reshapings, VLSI regulation, functional performance, connection lines, occupied chip area, neighboring relations, dead space, open holes, channels merging process, legal overlapping, VLSI, formal languages, formal language, network routing, circuit layout CAD, compaction, global routing, integrated circuit layout, integrated circuit interconnections, local routing
50Tim Dwyer, Kim Marriott, Michael Wybrow Integrating Edge Routing into Force-Directed Layout. Search on Bibsonomy GD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF constrained optimisation, edge routing, graph layout, force-directed layout
50Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi Correct-by-construction layout-centric retargeting of large analog designs. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF analog integrated circuit design, analog layout automation, analog synthesis and optimization, layout symmetry
50Hyunmo Kang, Ben Shneiderman, Gregory J. Wolff Dynamic Layout Management in a Multimedia Bulletin Board. Search on Bibsonomy HCC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Multimedia Bulletin Board (MBB), layout management, dynamic layout template (DLT), collaboration, asynchronous communication
50Toshiyuki Masui Evolutionary Learning of Graph Layout Constraints from Examples. Search on Bibsonomy ACM Symposium on User Interface Software and Technology The full citation details ... 1994 DBLP  DOI  BibTeX  RDF graphic object layout, genetic algorithms, genetic programming, adaptive user interface, programming by example, graph layout, TeX
49Edmund K. Burke, Karen M. Daniels, Graham Kendall 07112 Abstracts Collection - Cutting, Packing, Layout and Space Allocation. Search on Bibsonomy Cutting, Packing, Layout and Space Allocation The full citation details ... 2007 DBLP  BibTeX  RDF
49Edmund K. Burke, Karen M. Daniels, Graham Kendall 07112 Summary - Cutting, Packing, Layout and Space Allocation. Search on Bibsonomy Cutting, Packing, Layout and Space Allocation The full citation details ... 2007 DBLP  BibTeX  RDF
49Malgorzata Marek-Sadowska Issues in Timing Driven Layout. Search on Bibsonomy Algorithmic Aspects of VLSI Layout The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
49Teofilo F. Gonzalez, Sing-Ling Lee Routing around two Rectangles to minimize the Layout Area. Search on Bibsonomy Algorithmic Aspects of VLSI Layout The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
49Christof Lutteroth, Gerald Weber Modular Specification of GUI Layout Using Constraints. Search on Bibsonomy Australian Software Engineering Conference The full citation details ... 2008 DBLP  DOI  BibTeX  RDF user interfaces, constraints, modularity, layout
49Ian Kuon, Aaron Egier, Jonathan Rose Design, layout and verification of an FPGA using automated tools. Search on Bibsonomy FPGA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF FPGA, programmable logic, PLD, automatic layout
49Zhan Chen, Fook-Luen Heng A Fast Minimum Layout Perturbation Algorithm for Electromigration Reliability Enhancement. Search on Bibsonomy DFT The full citation details ... 1998 DBLP  DOI  BibTeX  RDF layout compaction, design for reliability, electromigration
47Akif Sultan, John Faricelli, Sushant Suryagandh, Hans vanMeer, Kaveri Mathur, James Pattison, Sean Hannon, Greg Constant, Kalyana Kumar, Kevin Carrejo, Joe Meier, Rasit Onur Topaloglu, Darin Chan, Uwe Hahn, Thorsten Knopp, Victor Andrade, Bill Gardiol, Steve Hejl, David Wu, James Buller, Larry Bair, Ali Icel, Yuri Apanovich CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
47Hiroaki Yoshida, Kaushik De, Vamsi Boppana Accurate pre-layout estimation of standard cell characteristics. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF cell characterization, transistor-level optimization, standard cell
47Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky Filling algorithms and analyses for layout density control. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
47Kazuo Sugihara, Kazunari Yamamoto, Isao Miyamoto Automatic Layout of Diagrams for Software Specification. Search on Bibsonomy SEKE The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
47David Eppstein, Elena Mumford, Bettina Speckmann, Kevin Verbeek Area-universal rectangular layouts. Search on Bibsonomy SCG The full citation details ... 2009 DBLP  DOI  BibTeX  RDF rectangular layouts
47Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi Multilevel symmetry-constraint generation for retargeting large analog layouts. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
46Floriana Esposito, Donato Malerba, Giovanni Semeraro A knowledge-based approach to the layout analysis. Search on Bibsonomy ICDAR The full citation details ... 1995 DBLP  DOI  BibTeX  RDF top-down technique, typesetting conventions, generic knowledge, processed documents, Layout EXpert, knowledge based systems, document image processing, document image, layout analysis, knowledge-based approach, LEX
44Christof Lutteroth, Robert Strandh, Gerald Weber Domain Specific High-Level Constraints for User Interface Layout. Search on Bibsonomy Constraints An Int. J. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Auckland Layout Model, Constraint, GUI
44Sambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy On Efficient and Robust Constraint Generation for Practical Layout Legalization. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Layout legalization, constraint reduction, compaction, constraint generation
44Payman Zarkesh-Ha, Ken Doniger Stochastic interconnect layout sensitivity model. Search on Bibsonomy SLIP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF critical area analysis, layout sensitivity, reliability, stochastic model, yield, design for manufacturability, defect density
44Yuying Wang, Xingshe Zhou 0001 Mutual Effect of Instruction Layout Optimization and Instruction Memory Hierarchy. Search on Bibsonomy ICPP Workshops The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Instruction Layout Optimization, Instruction Cache Miss Rate, Cache Memory Hierarchy
44Tim Dwyer, Yehuda Koren, Kim Marriott IPSep-CoLa: An Incremental Procedure for Separation Constraint Layout of Graphs. Search on Bibsonomy IEEE Trans. Vis. Comput. Graph. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF stress majorization, force directed algorithms, constraints, layout, Graph drawing, multidimensional scaling
44Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose Automatic transistor and physical design of FPGA tiles from an architectural specification. Search on Bibsonomy FPGA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF FPGA, programmable logic, PLD, automatic layout
44Carlton Bickford, Marie S. Teo, Gary Wallace, John A. Stankovic, Krithi Ramamritham A robotic assembly application on the Spring real-time system. Search on Bibsonomy IEEE Real Time Technology and Applications Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF printed circuit manufacture, printed circuit layout, robotic assembly application, Spring real-time system, run-time system support, predictability demands, robotic work-cell, circuit board assembly, user understanding, target hardware properties, process layout, resource layout, shared resource usage, process suspension, efficient run-time representation, real-time systems, robots, timing, completeness, flexibility, reengineering, timing analysis, circuit layout CAD, assembling, systems re-engineering, interprocess communication, program representation, porting, ease of use, industrial robots, software development tools
44Sandip Das 0001, Bhargab B. Bhattacharya Channel routing in Manhattan-diagonal model. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Manhattan-diagonal model, layout grid, cyclic vertical constraints, low via count, reduced wire length, VLSI, network routing, circuit layout CAD, VLSI layout, integrated circuit layout, channel routing, output-sensitive algorithm
44Saibal Das, Sanjeev Saxena Parallel algorithms for single row routing in narrow streets. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF narrow streets, optimal layout, parallel algorithms, parallel algorithms, VLSI, network routing, circuit layout CAD, VLSI layout, integrated circuit layout, single row routing, IC design, CREW PRAM, tree machine
43Yuji Shigehiro, Takashi Nagata, Isao Shirakawa, Itthichai Arungsrisangchai, Hiromitsu Takahashi Automatic layout recycling based on layout description and linear programming. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
43Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala Efficient Analog/RF Layout Closure with Compaction Based Legalization. Search on Bibsonomy VLSI Design The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
43Tim Dwyer, Kim Marriott, Michael Wybrow Topology Preserving Constrained Graph Layout. Search on Bibsonomy GD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
43Xiaofan Lin Active Document Layout Synthesis. Search on Bibsonomy ICDAR The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
43Ismail Kadayif, Mahmut T. Kandemir Quasidynamic Layout Optimizations for Improving Data Locality. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF array-intensive computations, dynamic optimization, Optimizing compilers, data locality
43Pierluigi Daglio, David Iezzi, Danilo Rimondi, Carlo Roma, Salvatore Santapa Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
43Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, C.-J. Richard Shi CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects. Search on Bibsonomy ASP-DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
43Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis. Search on Bibsonomy FPL The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
43Sanjay Khanna, Shaodi Gao, Krishnaiyan Thulasiraman Parallel hierarchical global routing for general cell layout. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF parallel hierarchical global routing, general cell layout, hierarchical decomposition strategy, network flow optimization, parallel algorithms, parallel processing, VLSI, integer programming, integer programming, routing algorithm, network routing, circuit layout CAD, integrated circuit layout, shared-memory machine
42Manjit Borah, Robert Michael Owens, Mary Jane Irwin Fast algorithm for performance-oriented Steiner routing. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF performance-oriented Steiner routing, fast routing algorithm, Elmore delay minimisation, layout generators, computational complexity, VLSI, data structures, data structures, delays, iterative methods, network routing, circuit layout CAD, integrated circuit layout, iterative techniques
41Saeedeh Bakhshi, Hamid Sarbazi-Azad Efficient VLSI Layout of Edge Product Networks. Search on Bibsonomy DELTA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Edge graph product, Collinear layout, Interconnection networks, Networks on chip, VLSI layout
41Derek Hoiem, Alexei A. Efros, Martial Hebert Recovering Surface Layout from an Image. Search on Bibsonomy Int. J. Comput. Vis. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF surface layout, spatial layout, geometric context, model-driven segmentation, multiple segmentations, context, object recognition, object detection, image understanding, scene understanding
41Ben L. Titzer, Jens Palsberg Vertical object layout and compression for fixed heaps. Search on Bibsonomy CASES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF heap optimization, object layout, pointer compression, program data compression, reference compression, vertical object layout, microcontrollers
41Yasuto Ishitani Document Layout Analysis Based on Emergent Computation. Search on Bibsonomy ICDAR The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Structural Layout Analysis, Bottom Up Strategy, Document Image Analysis, Document Layout Analysis
41Anikó Simon, Jean-Christophe Pret, A. Peter Johnson (Chem)DeTE/X automatic generation of a markup language description of (chemical) documents from bitmap images. Search on Bibsonomy ICDAR The full citation details ... 1995 DBLP  DOI  BibTeX  RDF markup language description, bitmap images, style file, layout recognition, Kruskal's algorithm, physical page structure, chemical documents, recursive parsing algorithm, document style description language, DSDL, document processing, layout analysis, document handling, scientific publications, page description languages
40Joseph H. Goldberg, Jonathan I. Helfman, Lynne Martin Information distance and orientation in liquid layout. Search on Bibsonomy CHI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF browser width, liquid layout, widescreen design, usability evaluation
40Huijun Zhu, Peng Gu, Jun Wang 0001 Shifted declustering: a placement-ideal layout scheme for multi-way replication storage architecture. Search on Bibsonomy ICS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF multi-way replication, optimal parallelism, data layout
40Christof Lutteroth, Gerald Weber User interface layout with ordinal and linear constraints. Search on Bibsonomy AUIC The full citation details ... 2006 DBLP  BibTeX  RDF 2D layout, formal constraints, user interface design, tables
40Simon Lok, Steven Feiner, Gary Ngai Evaluation of visual balance for automated layout. Search on Bibsonomy IUI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF automated layout, visual balance
40Seong-Whan Lee, Dae-Seok Ryu Parameter-Free Geometric Document Layout Analysis. Search on Bibsonomy IEEE Trans. Pattern Anal. Mach. Intell. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF Geometric document layout analysis, parameter-free method, periodicity estimation, page segmentation, multiscale analysis
40Chau-Shen Chen, TingTing Hwang Layout Driven Selection and Chaining of Partial Scan Flip-Flops. Search on Bibsonomy J. Electron. Test. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF design for testability, matching, placement, global routing, partial scan, digital testing, layout optimization
40Edmund K. Burke, Karen M. Daniels, Graham Kendall (eds.) Cutting, Packing, Layout and Space Allocation, 13.03. - 16.03.2007 Search on Bibsonomy Cutting, Packing, Layout and Space Allocation The full citation details ... 2007 DBLP  BibTeX  RDF
40S. M. Kang, M. Sriram Binary formulations for Placement and Routing Problems. Search on Bibsonomy Algorithmic Aspects of VLSI Layout The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
40Toshihiko Takahashi, Yoji Kajitani The Virtual Dimensions of a Straight Line Embedding of a plane Graph. Search on Bibsonomy Algorithmic Aspects of VLSI Layout The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
40D. Zhou, Franco P. Preparata On the Manhattan and knock-knee Routing Models. Search on Bibsonomy Algorithmic Aspects of VLSI Layout The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
40Prithviraj Banerjee A Survey of Parallel Algorithms for VLSI cell Placement. Search on Bibsonomy Algorithmic Aspects of VLSI Layout The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
40Shuji Tsukiyama, Keiichi Koike, Isao Shirakawa An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI floorplan. Search on Bibsonomy Algorithmic Aspects of VLSI Layout The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
40Tetsuo Asano, Takeshi Tokuyama Circuit Partitioning Algorithms based on Geometry Model. Search on Bibsonomy Algorithmic Aspects of VLSI Layout The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
40Martin L. Brady, Donna J. Brown, Patrick J. McGuiness The three-dimensional channel Routing Problem. Search on Bibsonomy Algorithmic Aspects of VLSI Layout The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
40Teofilo F. Gonzalez, Shashishekhar Kurki-Gowdara, Si-Qing Zheng Switch-Box Routing under the two-Overlap wiring Model. Search on Bibsonomy Algorithmic Aspects of VLSI Layout The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
40Chuan-Jin Shi Constrained via Minimization and Signed Hypergraph Partitioning. Search on Bibsonomy Algorithmic Aspects of VLSI Layout The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
40Thomas Lengauer, Martin Lügering Integer Program formulations of Global Routing and Placement Problems. Search on Bibsonomy Algorithmic Aspects of VLSI Layout The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
40Ting-Chi Wang, D. F. Wong 0001 A note on the Complexity of Stockmeyer's floorplan Optimization Technique. Search on Bibsonomy Algorithmic Aspects of VLSI Layout The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
40Fillia Makedon, Spyros Tragoudas Approximate solutions for Graph and Hypergraph Partitioning. Search on Bibsonomy Algorithmic Aspects of VLSI Layout The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
40Nathan Hurst, Kim Marriott, Peter Moulder Toward tighter tables. Search on Bibsonomy ACM Symposium on Document Engineering The full citation details ... 2005 DBLP  DOI  BibTeX  RDF table layout, optimisation techniques, conic programming
39Andrew Lim 0001, Sartaj K. Sahni, Venkat Thanvantri A fast algorithm to test planar topological routability. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF planar topological routability testing, pin nets, single layer routing, IC layout design, VLSI, network topology, network routing, circuit layout CAD, fast algorithm, VLSI layout, integrated circuit layout, linear time algorithm
39Roy Hartono, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi Automatic Device Layout Generation for Analog Layout Retargeting. Search on Bibsonomy VLSI Design The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39J. Apte, Gershon Kedem Strip Layout: A New Layout Methodology for Standard Circuit Modules. Search on Bibsonomy DAC The full citation details ... 1987 DBLP  DOI  BibTeX  RDF
39Vivek Joshi, Valeriy Sukharev, Andres Torres, Kanak Agarwal, Dennis Sylvester, David T. Blaauw Closed-form modeling of layout-dependent mechanical stress. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF mechanical stress, modeling, mobility
39Ming-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang An MILP-based wire spreading algorithm for PSM-aware layout modification. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
39Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi Hierarchical extraction and verification of symmetry constraints for analog layout automation. Search on Bibsonomy ASP-DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39Shuo Zhang, Wayne Wei-Ming Dai TEG: a new post-layout optimization method. Search on Bibsonomy ISPD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
39Bernd Meyer 0001 Self-Organizing Graphs - A Neural Network Perspective of Graph Layout. Search on Bibsonomy GD The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
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