Search results for "RTL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
103	Stefan Andrei, Albert M. K. Cheng	Verifying Linear Real-Time Logic Specifications.	RTSS	2007	DBLP DOI BibTeX RDF
94	Lin Zhong 0001, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	RTL-Aware Cycle-Accurate Functional Power Estimation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
88	Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira 0001	RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	fault modeling, DFT, TPG, RTL
86	Steve Haynal, Timothy Kam, Michael Kishinevsky, Emily Shriver, Xinning Wang	A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study.	MEMOCODE	2008	DBLP DOI BibTeX RDF
86	Alfred Kölbl, Jerry R. Burch, Carl Pixley	Memory Modeling in ESL-RTL Equivalence Checking.	DAC	2007	DBLP DOI BibTeX RDF
86	Indradeep Ghosh, Masahiro Fujita	Automatic test pattern generation for functional RTL circuits using assignment decision diagrams.	DAC	2000	DBLP DOI BibTeX RDF
80	Zdenek Kotásek, F. Zboril	RT level testability analysis to reduce test application time.	EUROMICRO	1997	DBLP DOI BibTeX RDF	register transfer level testability analysis, RTL element classification, RTL circuit transformation, labelled directed graph, PROLOG environment, implementation principles, logic testing, test application time reduction
79	Lin Zhong 0001, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Power estimation for cycle-accurate functional descriptions of hardware.	ICCAD	2004	DBLP DOI BibTeX RDF
79	Pascal Urard, Asma Maalej, Roberto Guizzetti, Nitin Chawla	Leveraging sequential equivalence checking to enable system-level to RTL flows.	DAC	2008	DBLP DOI BibTeX RDF	formal verification, high-level synthesis, equivalence checking, system-level models, RTL models
79	Stefan Andrei, Albert Mo Kim Cheng	Faster Verification of RTL-Specified Systems via Decomposition and Constraint Extension.	RTSS	2006	DBLP DOI BibTeX RDF
71	Indradeep Ghosh, Masahiro Fujita	Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
71	Alessandro Bogliolo, Luca Benini, Giovanni De Micheli	Regression-based RTL power modeling.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	RTL power modeling, adaptive characterization, functional macros, regression models, RTL design
71	Kelvin Ng	Challenges in using system-level models for RTL verification.	DAC	2008	DBLP DOI BibTeX RDF	simulation, equivalence checking, system-level model, RTL models
71	Aloysius K. Mok, Duu-Chung Tsou, Ruud C. M. de Rooij	The MSP.RTL real-time scheduler synthesis tool.	RTSS	1996	DBLP DOI BibTeX RDF	MSP RTL real time scheduler synthesis tool, scheduler synthesis algorithm, real time scheduling problem, temporal constraint satisfaction problem, temporal constraint graph, input timing specification, incremental positive cycle detection algorithm, real time scheduling theory, Boeing 777 Integrated Airplane Information Management System, AIMS, constraint satisfaction, processor scheduling, timing constraints, resource constraints, application domains, search strategies, cyclic schedules, feasible schedule, timing semantics, real time logic
71	Loganathan Lingappan, Srivaths Ravi 0001, Niraj K. Jha	Satisfiability-based test generation for nonseparable RTL controller-datapath circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
71	Liang Zhang 0012, Indradeep Ghosh, Michael S. Hsiao	A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
71	Shuqing Zhao, Daniel D. Gajski	Structural operational semantics for supporting multi-cycle operations in RTL HDLs.	MEMOCODE	2005	DBLP DOI BibTeX RDF
71	Farn Wang, Aloysius K. Mok	RTL and Refutation by Positive Cycles.	FME	1994	DBLP DOI BibTeX RDF
64	Luc Séméria, Renu Mehra, Barry M. Pangrle, Arjuna Ekanayake, Andrew Seawright, Daniel Ng	RTL c-based methodology for designing and verifying a multi-threaded processor.	DAC	2002	DBLP DOI BibTeX RDF	formal equivalence, design, verification, RTL, checking, C/C++
64	Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka	A Design for testability Method Using RTL Partitioning.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	line-up structure, internally balanced structure, acyclic structure, partitioning, ATPG, DFT, RTL, isolation, balanced structure
63	Prasenjit Basu, Sayantan Das 0001, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti 0001, Chunduri Rama Mohan, Limor Fix, Roy Armoni	Design-Intent Coverage - A New Paradigm for Formal Property Verification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
63	Simone Medardoni, Davide Bertozzi, Enrico Macii	Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	RTL synthesis, leakage-aware, power management, selection strategy
63	Shu-Hsuan Chou, Chi-Neng Wen, Yan-Ling Liu, Tien-Fu Chen	VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models.	ISQED	2009	DBLP DOI BibTeX RDF
63	Anmol Mathur, Qi Wang	Power Reduction Techniques and Flows at RTL and System Level.	VLSI Design	2009	DBLP DOI BibTeX RDF
63	Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel Gajski	An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
63	Nicola Bombieri, Franco Fummi, Valerio Guarnieri	Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction.	ETS	2011	DBLP DOI BibTeX RDF	RTL fault simulation, fault simulation acceleration, RTL-to-TLM abstraction
57	Li Shen 0002	VFSim: Concurrent Fault Simulation at Register Transfer Level.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	concurrent fault simulation, fault model, RTL, Verilog, high-level testing, circuit modeling
56	Farnam Jahanian, Aloysius K. Mok	Modechart: A Specification Language for Real-Time Systems.	IEEE Trans. Software Eng.	1994	DBLP DOI BibTeX RDF	Modechart, absolute timing, real-time clock, RTL formulas, RTL assertions, graphical implementation, SARTOR, real-time systems, real-time systems, semantics, specification languages, specification language, rapid prototyping, timing constraints, abstraction levels, logic programming languages, hierarchical organization, real-time logic
56	Xiushan Feng, Alan J. Hu	Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification.	DAC	2006	DBLP DOI BibTeX RDF	cutpoints, formal equivalence checking, software, RTL
56	Loganathan Lingappan, Niraj K. Jha	Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits.	VTS	2005	DBLP DOI BibTeX RDF
56	Stephen Paynter	Real-Time Logic Revisited.	FME	2001	DBLP DOI BibTeX RDF
56	Indradeep Ghosh, Srivaths Ravi 0001	On automatic generation of RTL validation test benches using circuit testing techniques.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	OCCOM, RTL ATPG, RTL testing, path coverage, small validation, toggle coverage, test, testing, generation, ATPG, fault coverage, code coverage, test sets, design validation, coverage metrics, universal test sets, testbench, branch coverage
55	Amin Asghari, Seied Ahmad Motamedi, Sepehr Attarchi	Effective RTL Method to Develop On-Line Self-Test Routine for the Processors Using the Wavelet Transform.	ACIS-ICIS	2008	DBLP DOI BibTeX RDF	On-line low-cost testing, Spectral test pattern generating, Software-based self-testing (SBST), Register transfer level (RTL), Processor testing
55	Elif Alpaslan, Yu Huang 0005, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak	Reducing Scan Shift Power at RTL.	VTS	2008	DBLP DOI BibTeX RDF	Test Power Reduction, Power-Sensitive Scan Cell, RTL DFT, Timing Closure, Scan Based Test
55	Yasuhiro Ito, Yutaka Sugawara, Mary Inaba, Kei Hiraki	CVC: The C to RTL compiler for callback-based verification model.	FPL	2008	DBLP DOI BibTeX RDF
55	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL.	DATE	2006	DBLP DOI BibTeX RDF
55	Shuqing Zhao, Daniel D. Gajski	Defining an Enhanced RTL Semantics.	DATE	2005	DBLP DOI BibTeX RDF
55	José M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João Paulo Teixeira 0001	A Probabilistic Method for the Computation of Testability of RTL Constructs.	DATE	2004	DBLP DOI BibTeX RDF
55	Qi Wang, Sumit Roy 0003	RTL Power Optimization with Gate-Level Accuracy.	ICCAD	2003	DBLP DOI BibTeX RDF
55	Loganathan Lingappan, Srivaths Ravi 0001, Niraj K. Jha	Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach.	ICCD	2003	DBLP DOI BibTeX RDF
55	Shuqing Zhao, Daniel Gajski	Modeling a new RTL semantics in C++.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
55	Peer Johannsen	BooStER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstarction.	CAV	2001	DBLP DOI BibTeX RDF
55	Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita	Hierarchical Error Diagnosis Targeting RTL Circuits.	VLSI Design	2000	DBLP DOI BibTeX RDF	Verification, Testing, Debugging, Diagnosis, Fault modeling, Error modeling
48	Wei Zhao, Christos A. Papachristou	Synthesis of reusable DSP cores based on multiple behaviors.	ICCAD	1996	DBLP DOI BibTeX RDF	RTL components, RTL structure, design process complexity, design time, multiple behaviors, reusable DSP cores synthesis, digital signal processing chips
48	George Sobral Silveira, Alisson Vasconcelos de Brito, Elmar U. K. Melcher	Functional verification of power gate design in SystemC RTL.	SBCCI	2009	DBLP DOI BibTeX RDF	simulation, SystemC, RTL, functional verification, power gate
48	Hyunuk Jung, Hoeseok Yang, Soonhoi Ha	Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	VHDL, system level design, RTL, dataflow graph (DFG), HW/SW codesign
48	Jens Horstmannshoff, Thorsten Grötker, Heinrich Meyr	Mapping multirate dataflow to complex RT level hardware models.	ASAP	1997	DBLP DOI BibTeX RDF	multirate dataflow mapping, complex RT level hardware models, digital signal processing systems, algorithm development phase, data flow specification, RTL target architecture, HDL code generation, cycle based timing model, ASIC design complexity, multirate dataflow graphs, signal processing, hardware architecture
48	Christian Dax, Felix Klaedtke, Martin Lange	On Regular Temporal Logics with Past, .	ICALP (2)	2009	DBLP DOI BibTeX RDF
48	Anand Raghunathan, Sujit Dey, Niraj K. Jha	High-level macro-modeling and estimation techniques for switching activity and power consumption.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
48	Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul	A test evaluation technique for VLSI circuits using register-transfer level fault modeling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
48	Ganesh Lakshminarayana, Niraj K. Jha	High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
48	Ganesh Lakshminarayana, Niraj K. Jha	Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions.	DAC	1998	DBLP DOI BibTeX RDF	transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band
47	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	Abstraction of RTL IPs into embedded software.	DAC	2010	DBLP DOI BibTeX RDF	RTL IP reuse, embedded software generation
47	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.	ICCD	1995	DBLP DOI BibTeX RDF	design for hierarchical testability, gate-level sequential test generation, controller data path circuits, large data path bit-widths, minimal test hardware, system-level test set, logic testing, high level synthesis, high level synthesis, integrated circuit testing, design for testability, design for testability, automatic testing, logic CAD, integrated circuit design, behavioral synthesis, logic gates, register-transfer level design, RTL circuits
47	Daniel Schwartz-Narbonne, Carven Chan, Yogesh S. Mahajan, Sharad Malik	Supporting RTL flow compatibility in a microarchitecture-level design framework.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	microarchitecture level, transactions, formal models, hierarchical design, hardware resources
47	Nicola Bombieri, Franco Fummi, Graziano Pravadelli, João Marques-Silva 0001	Towards Equivalence Checking Between TLM and RTL Models.	MEMOCODE	2007	DBLP DOI BibTeX RDF
47	Nitin Yogi, Vishwani D. Agrawal	Spectral RTL Test Generation for Microprocessors.	VLSI Design	2007	DBLP DOI BibTeX RDF
47	Anmol Mathur, Venkat Krishnaswamy	Design for Verification in System-level Models and RTL.	DAC	2007	DBLP DOI BibTeX RDF
47	Shujun Deng, Jinian Bian, Weimin Wu, Xiaoqing Yang, Yanni Zhao	EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure.	DAC	2007	DBLP DOI BibTeX RDF
47	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	A methodology for abstracting RTL designs into TL descriptions.	MEMOCODE	2006	DBLP DOI BibTeX RDF
47	Liang Zhang 0012, Indradeep Ghosh, Michael S. Hsiao	Efficient Sequential ATPG for Functional RTL Circuits.	ITC	2003	DBLP DOI BibTeX RDF
47	Srivaths Ravi 0001, Anand Raghunathan, Srimat T. Chakradhar	Efficient RTL Power Estimation for Large Designs.	VLSI Design	2003	DBLP DOI BibTeX RDF
47	Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras	RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST.	ITC	2002	DBLP DOI BibTeX RDF
47	Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar	Accurate Power Macro-modeling Techniques for Complex RTL Circuits.	VLSI Design	2001	DBLP DOI BibTeX RDF
47	Alessandro Bogliolo, Enrico Macii, Virgil Mihailovici, Massimo Poncino	Power Models for Semi-autonomous RTL Macros.	PATMOS	2000	DBLP DOI BibTeX RDF
47	Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie	Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
47	Pradip A. Thaker, Mona E. Zaghloul, Minesh B. Amin	Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementations.	VLSI Design	1999	DBLP DOI BibTeX RDF
46	Phan Cong Vinh, Jonathan P. Bowen	Semantics of RTL and Validation of Synthesized RTL Designs Using Formal Verification in Reconfigurable Computing Systems.	ECBS	2005	DBLP DOI BibTeX RDF
45	Shogo Semba, Hiroshi Saito, Masato Tatsuoka, Katsuya Fujimura	Optimization Methods during RTL Conversion from Synchronous RTL Models to Asynchronous RTL Models.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2020	DBLP DOI BibTeX RDF
41	Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001, Salvador Manich, Luz Balado, Joan Figueras	On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	low-power, BIST, RTL, test quality, defects-based test
40	Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira 0001	RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	Defect-Oriented Test (DOT), low-energy test, test generation, RTL
40	Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri	On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers.	VLSI Design	1997	DBLP DOI BibTeX RDF	fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model
40	Anand Raghunathan, Sujit Dey, Niraj K. Jha	Register-transfer level estimation techniques for switching activity and power consumption.	ICCAD	1996	DBLP DOI BibTeX RDF	gate-level implementation, register-transfer level estimation, logic design, power consumption, switching activity, glitching, RTL designs
40	Guillermo Maturana, James L. Ball, Jeffery Gee, Amaresh Iyer, J. Michael O'Connor	Incas: a cycle accurate model of UltraSPARC.	ICCD	1995	DBLP DOI BibTeX RDF	cycle accurate model, UltraSPARC, Incas, message-passing mechanism, simulating concurrent modules, performance evaluation, C++, virtual machines, logic testing, microprocessor chips, performance estimates, diagnostics, tuning, RTL simulations, processor verification
40	Sumit Ahuja, Deepak Mathaikutty, Gaurav Singh 0006, Joe Stetzer, Sandeep K. Shukla, Ajit Dingankar	Power estimation methodology for a high-level synthesis framework.	ISQED	2009	DBLP DOI BibTeX RDF
40	Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi	A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
40	Wolfgang Ecker, Volkan Esen, Michael Hull	Execution semantics and formalisms for multi-abstraction TLM assertions.	MEMOCODE	2006	DBLP DOI BibTeX RDF
40	Indradeep Ghosh	High Level Test Generation for Custom Hardware: An Industrial Perspective.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
40	Abhijit Ghosh, Srinivas Devadas, A. Richard Newton	Sequential Test Generation at the Register-Transfer and Logic Levels.	DAC	1990	DBLP DOI BibTeX RDF
39	Stuart Swan	SystemC transaction level models and RTL verification.	DAC	2006	DBLP DOI BibTeX RDF	RTL verification, hardware/software co-verification, systemC, hardware/software co-design, transaction level model, TLM
39	Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara	A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	test plan grouping, test controllers, partly compacted test plan tables, RTL data paths, test length
39	Michael Eiermann, Walter Stechele	Novel modeling techniques for RTL power estimation.	ISLPED	2002	DBLP DOI BibTeX RDF	RTL macromodels, low power, power estimation, power modeling
39	Haifeng Zhou, Zhenghui Lin, Wei Cao	Research on VHDL RTL Synthesis System.	DELTA	2002	DBLP DOI BibTeX RDF	VHDL RTL synthesis, ambiguous grammar, language level optimization, inference, formal semantics, parser
39	Zhigang Yin, Yinghua Min, Xiaowei Li 0001	An Approach to RTL Fault Extraction and Test Generation.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	ATPG (Automatic Test Pattern Generation), RTL (Register Transfer Level), Fault
39	Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara	Single-control testability of RTL data paths for BIST.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test
39	Yiorgos Makris, Alex Orailoglu	RTL Test Justification and Propagation Analysis for Modular Designs.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	RTL testability analysis, test justification, test propagation, DFT, modular design
39	K. J. Singh, P. A. Subrahmanyam	Extracting RTL models from transistor netlists.	ICCAD	1995	DBLP DOI BibTeX RDF	Switch-level simulation, Formal verification, Extraction, RTL model
39	Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke	Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
39	Nicola Bombieri, Nicola Deganello, Franco Fummi	Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation.	DATE	2008	DBLP DOI BibTeX RDF
39	Tatsuya Koyagi, Masahiro Fukui, Resve A. Saleh	Delay macromodeling and estimation for RTL.	ISCAS	2008	DBLP DOI BibTeX RDF
39	Robert Beers	Pre-RTL formal verification: an intel experience.	DAC	2008	DBLP DOI BibTeX RDF	TLC, explicit state enumeration, microarchitecture verification, formal verification, protocol verification, TLA+
39	Kedarnath J. Balakrishnan, Lei Fang	RTL Test Point Insertion to Reduce Delay Test Volume.	VTS	2007	DBLP DOI BibTeX RDF
39	Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha	Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits.	VLSI Design	2007	DBLP DOI BibTeX RDF
39	Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt Jr.	Automatic insertion of low power annotations in RTL for pipelined microprocessors.	DATE	2006	DBLP DOI BibTeX RDF
39	Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon 0001	Automatic memory reductions for RTL model verification.	ICCAD	2006	DBLP DOI BibTeX RDF
39	Pietro Babighian, Luca Benini, Enrico Macii	A scalable algorithm for RTL insertion of gated clocks based on ODCs computation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
39	Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer	Structural search for RTL with predicate learning.	DAC	2005	DBLP DOI BibTeX RDF	learning, satisfiability, interval arithmetic, predicate abstraction
39	Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu	Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test.	IEEE Trans. Reliab.	2004	DBLP DOI BibTeX RDF
39	Jean-Pierre David, Etienne Bergeron	A Step towards Intelligent Translation from High-Level Design to RTL.	IWSOC	2004	DBLP DOI BibTeX RDF
39	Rohit Jindal, Kshitiz Jain	Verification of Transaction-Level SystemC models using RTL Testbenches.	MEMOCODE	2003	DBLP DOI BibTeX RDF