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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2846 occurrences of 1432 keywords
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Results
Found 14080 publication records. Showing 14080 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
90 | Bassem A. Alhalabi, Magdy A. Bayoumi |
A scalable analog architecture for neural networks with on-chip learning and refreshing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 33-, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
analogue storage, scalable analog architecture, on-chip learning, on-chip refreshing, analog storage, analog functional blocks, analog pass switches, system versatility, learning speed, local analog synaptic updating scheme, unbounded scalability, neural networks, learning (artificial intelligence), neural chips, analogue processing circuits |
79 | Mike Brunoli, Masao Hotta, Felicia James, Rudy Koch, Roy McGuffin, Andrew J. Moore |
Analog intellectual property: now? Or never? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 181-182, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
79 | John Lowell |
Computer aided design for analog applications (panel session): an assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 554, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
77 | Thelma Estrin |
The UCLA Brain Research Institute data processing laboratory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
History of Medical Informatics ![In: Proceedings of the ACM Conference on History of Medical Informatics, Bethesda, Maryland, USA, November 5-6, 1987, pp. 75-83, 1987, ACM, 0-89791-248-9. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
73 | Shekhar Borkar, Robert W. Brodersen, Jue-Hsien Chern, Eric Naviasky, D. Saias, Charles G. Sodini |
Tomorrow's analog: just dead or just different? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 709-710, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
analog CAD tools, analog design methodologies, mixed-signal design, analog design, RF design |
66 | Rajesh Ramadoss, Michael L. Bushnell |
Test generation for mixed-signal devices using signal flow graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 242-248, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
mixed-signal devices, reverse simulation approach, component tolerances, analog input sinusoids, test generation results, analog backtrace method, high-order analog circuits, fault diagnosis, test generation, integrated circuit testing, automatic testing, circuit analysis computing, mixed analogue-digital integrated circuits, signal flow graphs, signal flow graphs, nonlinear circuits |
65 | Janusz Rzeszut, Bozena Kaminska, Yvon Savaria |
A new method for testing mixed analog and digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 127-132, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
charge-coupled device circuits, mixed analog and digital circuits, analog test points, simultaneous observation, analog multiplexer, signal path, analog shift register, input voltage, integrated circuit testing, shift registers, mixed analogue-digital integrated circuits, charge coupled device, analogue processing circuits |
64 | Anirudh Devgan, Bulent Basaran, David Colleran, Mar Hershenson |
Accelerated design of analog, mixed-signal circuits in Titan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 67-72, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
analog circuit layout, analog/digital, custom design, layout, physical design, analog circuits, mixed-signal circuits |
64 | Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi |
Correct-by-construction layout-centric retargeting of large analog designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 139-144, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
analog integrated circuit design, analog layout automation, analog synthesis and optimization, layout symmetry |
59 | Boris Murmann |
Digitally Assisted Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 26(2), pp. 38-47, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
analog signals, digital computing, analog circuits, analog-to-digital converter |
57 | Tathagato Rai Dastidar, P. P. Chakrabarti 0001 |
A verification system for transient response of analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(3), pp. 31:1-31:39, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Ana CTL, model checking, query language, Analog circuits, equivalence checking, transient response |
55 | Eric E. Fabris, Luigi Carro, Sergio Bampi |
A Universal High-Performance Analog Interface for Signal Processing SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, pp. 137-, 2003, IEEE Computer Society, 0-7695-2009-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
54 | Salvador Mir, Marcelo Lubaszewski, Bernard Courtois |
Unified built-in self-test for fully differential analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 9(1-2), pp. 135-151, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
on-line/off-line analog test, unified BIST, fully differential analog circuits, common-mode feedback, analog BIST |
54 | Alexandre R. S. Romariz, P. U. A. Ferreira, J. V. Campêlo Jr., Marcio L. Graciano Jr., José C. da Costa |
Design of a Hybrid Digital-Analog Neural Co-Processor for Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 513-519, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
hybrid digital-analog neural co-processor, digitally-controlled multiplexing, CMOS analog circuits, VLSI, signal processing, VLSI design, multilayer perceptrons, VLSI implementation, hybrid architecture, capacitors, analog multipliers |
54 | Rajesh Ramadoss, Michael L. Bushnell |
Test Generation for Mixed-Signal Devices Using Signal Flow Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(3), pp. 189-205, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
analog test generation, mixed-signal test generation, back tracing, parametric faults, catastrophic faults |
53 | Stephan Ohr, Rob A. Rutenbar, Henry Chang, Georges G. E. Gielen, Rudolf Koch, Roy McGuffin, K. C. Murphy |
Survival strategies for mixed-signal systems-on-chip (panel session). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 579-580, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
52 | Hong Helena Zheng, Ashok Balivada, Jacob A. Abraham |
A novel test generation approach for parametric faults in linear analog circuits . ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 470-475, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
digital test software, time-domain tests, equivalent digital circuit, digital test vectors, test waveform, VLSI, test generation, integrated circuit testing, fault location, stuck-at faults, analogue integrated circuits, parametric faults, linear analog circuits, time-domain analysis, equivalent circuits, analogue processing circuits |
51 | Jorge Luís Machado do Amaral, José Franco Machado do Amaral, Cristina Costa Santini, Ricardo Tanscheit, Marley M. B. R. Vellasco, Marco Aurélio Cavalcanti Pacheco, Antonio Carneiro de Mesquita Filho |
Evolvable Building Blocks for Analog Fuzzy Logic Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 5th NASA / DoD Workshop on Evolvable Hardware (EH 2003), 9-11 July 2002, Chicago, IL, USA, pp. 101-110, 2003, IEEE Computer Society, 0-7695-1977-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
50 | Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin |
Low Cost On-Line Testing Strategy for RF Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(4), pp. 417-427, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
on-line analog testing, DSP-based testing, analog test |
49 | Saied Hemati, Amir H. Banihashemi |
Iterative decoding in analog CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 15-20, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
analog CMOS, analog iterative decoder, asynchronous iterative decoding, min-sum decoding, soft decoding, analog circuit, turbo codes, iterative decoding, low-density parity-check codes |
49 | Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin |
Ultimate low cost analog BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 570-573, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
DSP-based analog test, low cost analog BIST, test of analog circuits |
49 | Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham |
Efficient multisine testing of analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 234-238, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
waveform analysis, biquadratic filters, multisine testing, test waveform generation, test confidence, fault-based automatic test pattern generator, successive gradient method, sinusoidal signals, fault coverage maximization, biquadratic filter, AC testing, analog IC, fault diagnosis, built-in self test, integrated circuit testing, automatic testing, analog circuits, built-in test, analogue integrated circuits, linear analog circuits |
49 | Paul Mueller, Jan Van der Spiegel, David Blackman, Timothy Chiu, Thomas Clare, Christopher Donham, Tzu-pu Hsieh, Marc Loinaz |
Design and Fabrication of VLSI Components for a General Purpose Analog Neural Computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Analog VLSI Implementation of Neural Systems ![In: Analog VLSI Implementation of Neural Systems, pp. 135-169, 1989, Kluwer / Springer US, 978-1-4613-1639-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
49 | Steven Bibyk, Mohammed Ismail 0001 |
Issues in Analog VLSI and MOS Techniques for Neural Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Analog VLSI Implementation of Neural Systems ![In: Analog VLSI Implementation of Neural Systems, pp. 103-133, 1989, Kluwer / Springer US, 978-1-4613-1639-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
49 | John G. Harris, Christof Koch, Jin Luo, John L. Wyatt Jr. |
Resistive Fuses: Analog Hardware for Detecting Discontinuities in Early Vision. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Analog VLSI Implementation of Neural Systems ![In: Analog VLSI Implementation of Neural Systems, pp. 27-55, 1989, Kluwer / Springer US, 978-1-4613-1639-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
48 | Alvernon Walker, Parag K. Lala |
A Transition Based BIST Approach for Passive Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 347-354, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Built-in Self Test, Analog Test, Analog BIST, Mixed-Signal BIST |
48 | Jan Arild Tofte, Chee-Kian Ong, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng |
Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 237-246, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
cross-correlation signature register, CCSR, implicit functional testing, harmonic distortion, THD, classification, synthesis, noise, BIST, convex hull, polygon, discrimination, analog test, cross-correlation, mixed-signal, pseudo-random, pseudo-random, labview, impulse response, performance parameter, analog BIST |
48 | Michel Renovell, Florence Azaïs, Yves Bertrand |
A design-for-test technique for multistage analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 113-119, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
design-for-test technique, multistage analog circuits, DFT approach, op-amp-based modules, testability resources, transparent paths, external I/O, local I/O, test mode, on-chip digital resources, analog response penalty, controllability, controllability, integrated circuit testing, design for testability, observability, observability, mixed-signal circuits, mixed analogue-digital integrated circuits, test management, production testing |
48 | Anirudh Devgan, Ronald A. Rohrer |
Efficient simulation of interconnect and mixed analog-digital circuits in ACES. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 229-233, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
adaptively controlled explicit simulation, mixed analog-digital circuits, analog circuit simulation, interconnect circuit simulation, AWE macromodels, nonlinear terminations, variable accuracy device models, circuit topology constraints removal, timing, circuit analysis computing, transient analysis, analogue integrated circuits, integrated circuit interconnections, mixed analogue-digital integrated circuits, ACES, transient simulation, timing simulation |
47 | I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, Tyson S. Hall, David V. Anderson |
Mapping algorithm for large-scale field programmable analog array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 152-158, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
floating gates, mapping, field programmable analog array |
47 | Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin |
A Statistical Sampler for a New On-Line Analog Test Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(5), pp. 585-595, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
DSP-based testing, on-line testing, analog test |
47 | Jonathan W. Mills, Matt Parker, Bryce Himebaugh, Craig A. Shue, Brian Kopecky, Chris Weilemann |
"Empty space" computes: the evolution of an unconventional supercomputer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006, pp. 115-126, 2006, ACM, 1-59593-302-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Lukasiewicz logic, extended analog computer, general purpose analog computer, hybrid digital-analog architecture |
46 | Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting |
Metrology for analog module testing using analog testability bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 594-599, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
analog module, analog module testing, multiple instantiation, test response analysis, test waveform, testability bus, design for testability |
46 | Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty |
Test infrastructure design for mixed-signal SOCs with wrapped analog cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(3), pp. 292-304, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Anuja Sehgal, Fang Liu 0029, Sule Ozev, Krishnendu Chakrabarty |
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 50-55, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
46 | Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty |
A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 137-142, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
46 | Tathagato Rai Dastidar, P. P. Chakrabarti 0001 |
A Verification System for Transient Response of Analog Circuits Using Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 195-200, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Yvan Maidon, Thomas Zimmer, André Ivanov |
An Analog Circuit Fault Characterization Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(2), pp. 127-134, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
analog circuit testing, analog fault diagnosis, analog fault characterization |
43 | Bo Liu 0003, Francisco V. Fernández 0001, Georges G. E. Gielen, Rafael Castro-López, Elisenda Roca |
A memetic approach to the automatic design of high-performance analog integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(3), pp. 42:1-42:24, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Analog circuit sizing, analog design automation, constrained optimization, memetic algorithm |
43 | Eric E. Fabris, Luigi Carro, Sergio Bampi |
Modeling and designing high performance analog reconfigurable circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 49-54, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
analog programmability, band-pass sigma-delta modulator, analog design, FPAA |
43 | Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell |
TI-BIST: a temperature independent analog BIST for switched-capacitor filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 78-83, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
temperature independent analog BIST, simulation, built-in self test, BIST, analogue circuits, switched capacitor filters, switched-capacitor filters, analog BIST |
43 | Ramakrishna Voorakaranam, Abhijit Chatterjee |
Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA, pp. 342-357, 1999, IEEE Computer Society, 0-7695-0056-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
analog verification, fault diagnosis, test generation, analog testing, Backtrace |
43 | Chanchal Chatterjee, Vwani P. Roychowdhury |
An efficient contrast-enhancement method using the analog to digital converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Mach. Vis. Appl. ![In: Mach. Vis. Appl. 9(3), pp. 97-105, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Analog enhancement, Analog to digital converter |
43 | Hari Vijay Venkatanarayanan, Michael L. Bushnell |
An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 161-168, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Hamid Reza Ghasemi, Zainalabedin Navabi |
An Effective VHDL-AMS Simulation Algorithm with Event Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 762-767, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
42 | Eric Soenen |
Physical design methodology for analog circuitsin a system-on-a-chip environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 73-74, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
analog design automation |
42 | Göran Jerke, Jens Lienig |
Constraint-driven design: the next step towards analog design automation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 75-82, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
constraint-driven design, constraints, layout, physical design, analog design |
42 | Didier Keymeulen, Adrian Stoica, Ricardo Salem Zebulum, Srinivas Katkoori, Pradeep Fernando, Hariharan Sankaran, Mohammad M. Mojarradi, Taher Daud |
Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 8th International Conference, ICES 2008, Prague, Czech Republic, September 21-24, 2008. Proceedings, pp. 225-236, 2008, Springer, 978-3-540-85856-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Self-Healing and Compensation, Self-reconfigurable, Field Programmable Analog Array |
42 | Bassem A. Alhalabi, Qutaibah M. Malluhi, Rafic A. Ayoubi |
Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 168-, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
non-refreshing static storage, on-chip learning neural networks, analog learning |
42 | Mehdi Ehsanian, Bozena Kaminska, Karim Arabi |
A new digital test approach for analog-to-digital converter testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 60-65, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
digital test approach, analog/digital converter testing, BIST circuitry, offset error, gain error, DNL, INL, area overhead reduction, medium resolution ADC, high resolution pipelined ADC, A/D converter testing, differential nonlinearity, integral nonlinearity, 1.5 micron, VLSI, built-in self test, built-in self-test, integrated circuit testing, CMOS integrated circuits, CMOS technology, analogue-digital conversion |
41 | Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou |
Intrinsic response for analog module testing using an analog testability bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(2), pp. 226-243, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
analog testability bus, intrinsic response, design for testability, analog testing, boundary scan |
41 | Chauchin Su, Yue-Tsang Chen |
Crosstalk Effect Removal for Analog Measurement in Analog Test Bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 403-410, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Analog Test Bus, Design for Testability, Analog Test, Mixed Signal Test |
41 | Carver Mead |
Adaptive Retina. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Analog VLSI Implementation of Neural Systems ![In: Analog VLSI Implementation of Neural Systems, pp. 239-246, 1989, Kluwer / Springer US, 978-1-4613-1639-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
41 | Christopher R. Carroll |
A Neural Processor for Maze Solving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Analog VLSI Implementation of Neural Systems ![In: Analog VLSI Implementation of Neural Systems, pp. 1-26, 1989, Kluwer / Springer US, 978-1-4613-1639-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
41 | Jan Van der Spiegel, G. Kreider, C. Claeys, I. Debusschere, Giulio Sandini, Paolo Dario, Fausto Fantini, P. Bellutti, Giovanni Soncini |
A Foveated Retina-Like Sensor Using CCD Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Analog VLSI Implementation of Neural Systems ![In: Analog VLSI Implementation of Neural Systems, pp. 189-211, 1989, Kluwer / Springer US, 978-1-4613-1639-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
41 | John Lazzaro, Carver Mead |
Circuit Models of Sensory Transduction in the Cochlea. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Analog VLSI Implementation of Neural Systems ![In: Analog VLSI Implementation of Neural Systems, pp. 85-101, 1989, Kluwer / Springer US, 978-1-4613-1639-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
41 | Misha A. Mahowald, Tobi Delbrück |
Cooperative Stereo Matching Using Static and Dynamic Image Features. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Analog VLSI Implementation of Neural Systems ![In: Analog VLSI Implementation of Neural Systems, pp. 213-238, 1989, Kluwer / Springer US, 978-1-4613-1639-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
41 | Eric A. Vittoz, Xavier Arreguit |
CMOS Integration of Herault-Jutten Cells for Separation of Sources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Analog VLSI Implementation of Neural Systems ![In: Analog VLSI Implementation of Neural Systems, pp. 57-83, 1989, Kluwer / Springer US, 978-1-4613-1639-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
41 | Tobi Delbrück |
A Chip that Focuses an Image on Itself. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Analog VLSI Implementation of Neural Systems ![In: Analog VLSI Implementation of Neural Systems, pp. 171-188, 1989, Kluwer / Springer US, 978-1-4613-1639-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
41 | Haralabos C. Papadopoulos, Carl-Erik W. Sundberg |
Precoded Modulo-Precanceling Systems for Simulcasting Analog FM and Digital Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 56(8), pp. 1279-1288, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Renée St. Amant, Daniel A. Jiménez, Doug Burger |
Low-power, high-performance analog neural branch prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, pp. 447-458, 2008, IEEE Computer Society, 978-1-4244-2836-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi |
Multilevel symmetry-constraint generation for retargeting large analog layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6), pp. 945-960, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Saied Hemati, Amir H. Banihashemi |
Dynamics and performance analysis of analog iterative decoding for low-density parity-check (LDPC) codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 54(1), pp. 61-70, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Ami Litman, Shiri Moran-Schein |
Smooth scheduling under variable rates or the analog-digital confinement game. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2006: Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Cambridge, Massachusetts, USA, July 30 - August 2, 2006, pp. 74-83, 2006, ACM, 1-59593-452-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
EDF schemes, EDF strategies, concurrent confinement games, confinement games, non-concurrent confinement games, smooth scheduling, variable rates, online scheduling, two players games |
41 | Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal |
Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 375-383, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
41 | Brian A. A. Antao, Arthur J. Brodersen |
ARCHGEN: Automated synthesis of analog systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(2), pp. 231-244, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
41 | Fa-Long Luo, Rolf Unbehauen, Hongqin Xue |
Continuous-time computation of the eigenvectors of a class of positive definite matrices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), January 25-27, 1995, San Remo, Italy, pp. 464-471, 1995, IEEE Computer Society, 0-8186-7031-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
analogue computers, continuous-time computation, analog circuit approach, specialized analog computers, asynchronous parallel processing, continuous-time dynamics, high-speed computational capability, real-time applications fields, parallel processing, neural nets, matrix algebra, eigenvectors, special purpose computers, eigenvalues and eigenfunctions, neural chips, positive definite matrices |
39 | Eric E. Fabris, Luigi Carro, Sergio Bampi |
Analog Signal Processing Reconfiguration for Systems-on-Chip Using a Fixed Analog Cell Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 1136-1138, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
39 | John C. Gallagher |
The Once and Future Analog Alternative: Evolvable Hardware and Analog Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 5th NASA / DoD Workshop on Evolvable Hardware (EH 2003), 9-11 July 2002, Chicago, IL, USA, pp. 43-57, 2003, IEEE Computer Society, 0-7695-1977-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
39 | Adrián Núñez-Aldana, Ranga Vemuri |
An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 406-411, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
39 | Hugo de Lemos Haas, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia |
Viability of analog inner product operations in CMOS imagers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 236-240, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
CMOS analog hardware, analog image processing, vector quantization |
39 | Farzan Aminian, Mehran Aminian |
Fault Diagnosis of Analog Circuits Using Bayesian Neural Networks with Wavelet Transform as Preprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(1), pp. 29-36, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
analog fault diagnosis, Bayesiasn learning, neural networks, analog circuits |
39 | Matthew Worsman, Mike W. T. Wong, Yim-Shu Lee |
Analog circuit equivalent faults in the D.C. domain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 84-89, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
analog circuit faults, fault simulation data, equivalent faults, equivalent fault identification, built-in self test, design for testability, data analysis, fault simulation, fault location, fault location, analogue circuits, linear analog circuits |
39 | Anna Maria Brosa, Joan Figueras |
Characterization of Floating Gate Defects in Analog Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(1-2), pp. 23-31, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
floating gate defect, low-power/low-voltage analog circuits, analog testing |
39 | Guido Dröge, Manfred Thole, Ernst-Helmut Horneber |
EASY - a System for Computer-Aided Examination of Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 644-648, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
analog design system, computer-aided design, analog circuits, symbolic analysis, qualitative analysis |
39 | Salvador Mir, Marcelo Lubaszewski, Bernard Courtois |
Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 9(1-2), pp. 43-57, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
analog ATPG, fault diagnosis, fault-based testing, analog BIST |
39 | Bogdan G. Arsintescu |
A Method for Analog Circuits Visualization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 454-459, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Analog circuits visualization, Design verification tools, Computer aided design for analog circuits |
38 | Salem Abdennadher, Saghir A. Shaikh |
Practices in Testing of Mixed-Signal and RF SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 467, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Rakesh Chadha, Chandramouli Visweswariah, Chin-Fu Chen |
M3-a multilevel mixed-mode mixed A/D simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(5), pp. 575-585, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
37 | Mark Horowitz, Metha Jeeradit, Frances Lau, Sabrina Liao, ByongChan Lim, James Mao |
Fortifying analog models with equivalence checking and coverage analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 425-430, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
analog validation, model-first design, design methodology, fault coverage, equivalence checking, formal validation |
37 | Zhihong Feng, Zhigui Lin, Wei Fang, Wei Wang, Zhitao Xiao |
Analog Circuit Fault Fusion Diagnosis Method Based on Support Vector Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (2) ![In: Advances in Neural Networks - ISNN 2009, 6th International Symposium on Neural Networks, ISNN 2009, Wuhan, China, May 26-29, 2009, Proceedings, Part II, pp. 225-234, 2009, Springer, 978-3-642-01509-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Multi- classification, Support Vector Machine, Fault diagnosis, Analog circuit |
37 | Meng-Hui Wang, Yu-Kuo Chung, Wen-Tsai Sung |
The Fault Diagnosis of Analog Circuits Based on Extension Theory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIC (1) ![In: Emerging Intelligent Computing Technology and Applications, 5th International Conference on Intelligent Computing, ICIC 2009, Ulsan, South Korea, September 16-19, 2009. Proceedings, pp. 735-744, 2009, Springer, 978-3-642-04069-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Extension theory (ET), Fault diagnosis, Analog circuit |
37 | Corneliu Rusu, Lacrimioara Grama, Jarmo Takala |
SPICE Simulation of Analog Filters: A Method for Designing Digital Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCAST ![In: Computer Aided Systems Theory - EUROCAST 2009, 12th International Conference, Las Palmas de Gran Canaria, Spain, February 15-20, 2009, Revised Selected Papers, pp. 534-539, 2009, Springer, 978-3-642-04771-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
analog filter, SPICE, digital filter |
37 | Mark Po-Hung Lin, Hongbo Zhang 0001, Martin D. F. Wong, Yao-Wen Chang |
Thermal-driven analog placement considering device matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 593-598, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
analog placement, thermal matching |
37 | Mark Po-Hung Lin, Shyh-Chang Lin |
Analog placement based on hierarchical module clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 50-55, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
analog placement, floorplanning |
37 | A. A. Mariano, B. Boumballa, Dominique Dallet, Yann Deval, Jean-Baptiste Bégueret |
High-speed CMOS analog-to-digital converter for front-end receiver applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 27-30, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
flash structure, analog-to-digital converter, data-conversion |
37 | Raffaella Gentilini, Klaus Schneider 0001, Alexander Dreyer |
Three-valued automated reasoning on analog properties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 485-488, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
(multi valued) temporal logics & model checking, interval arithmetic, analog circuits |
37 | Lei Feng, Won Namgoong |
An Analog/Digital Baseband Processor Design of a UWB Channelized Receiver for Transmitted Reference Signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 43(1), pp. 59-71, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
transmitted reference, channelized receiver, coarse acquisition, synchronization, Ultra-wideband, analog-to-digital converter |
37 | Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri |
A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 9(2), pp. 238-271, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
genetic algorithms, branch-and-bound, performance estimation, VHDL-AMS, Analog synthesis |
37 | Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi |
Hierarchical approach to exact symbolic analysis of large analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 860-863, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
MEMS and/or RF design tools, behavioral modeling, analog, circuit simulation, symbolic analysis, mixed-signal |
37 | Walter Hartong, Lars Hedrich, Erich Barke |
Model checking algorithms for analog verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 542-547, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
nonlinear analog systems, model checking, formal methods |
37 | Sasikumar Cherubal, Abhijit Chatterjee |
Test generation for fault isolation in analog circuits using behavioral models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 19-24, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
multiple parameter variations, manufacturing tolerances, test generation, fault location, behavioral models, analog circuits, analogue integrated circuits, fault isolation, circuit testing, behavioral descriptions, parametric failures, measurement noise |
37 | Sudip Chakrabarti, Abhijit Chatterjee |
Compact Fault Dictionary Construction for Efficient Isolation of Faults in Analog and Mixed-Signal Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA, pp. 327-341, 1999, IEEE Computer Society, 0-7695-0056-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
fault diagnosis, analog, Design automation, mixed-signal, fault isolation |
37 | Christian Dufaza, Hassan Ihs |
A BIST-DFT technique for DC test of analog modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 9(1-2), pp. 117-133, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
current and voltage self-testing, Built-In Voltage Sensor, Built-In Self Test, Design For Testability, analog BIST |
37 | Samiran Halder, Swapna Banerjee, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Sanjoy Kumar Dey |
A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm2 Segmented Current Steering CMOS DAC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 319-322, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
MOS Analog Circuits, Digital to Analog Conversion, Mixed Analog -Digital Integrated Circuits, Low Power |
36 | Diego Pedro Morales, Antonio García 0001, Alberto J. Palma, Miguel A. Carvajal, Encarnación Castillo, Luis F. Capitán-Vallvey |
Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 635-638, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
36 | Saied Hemati, Amir H. Banihashemi |
Convergence Speed and Throughput of Analog Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 55(5), pp. 833-836, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Adrian Stoica, Didier Keymeulen, Ricardo Salem Zebulum, Mohammad M. Mojarradi, Srinivas Katkoori, Taher Daud |
Adaptive and Evolvable Analog Electronics for Space Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007, Proceedings, pp. 379-390, 2007, Springer, 978-3-540-74625-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Adaptive Hardware, Field Programmable Arrays |
36 | Ricardo Salem Zebulum, Mohammad M. Mojarradi, Adrian Stoica, Didier Keymeulen, Taher Daud |
Self-Reconfigurable Analog Arrays: Off-The Shelf Adaptive Electronics for Space Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), August 5-8, 2007, University of Edinburgh, Scotland, United Kingdom, pp. 529-536, 2007, IEEE Computer Society, 0-7695-2866-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp |
DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 387-392, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
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