Search results for "field-programmable-gate-array"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
109	Zhuo Gao, Ji Luo 0003, Hu Huang 0001, Wei Zhang, Joseph B. Bernstein	Reliable Laser Programmable Gate Array Technology.	ISQED	2002	DBLP DOI BibTeX RDF	Laser Programmable Gate Array (LPGA), Laser Field-Programmable Gate Array (LFPGA), MakeLink technology, laser-induced/laser programmable anti-fuse, digital ASIC design, low electrical resistance anti-fuse, Field-Programmable Gate Array (FPGA)
67	Hardy J. Pottinger, Chien-Yuh Lin	Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education
65	Yen-Tai Lai, Ping-Tsung Wang	Hierarchical interconnection structures for field programmable gate arrays.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
57	Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto	Universal test complexity of field-programmable gate arrays.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	universal test complexity, arbitrary logic circuits, sequential loading, random access loading, programming schemes, block-sliced loading, configuration memory cells, field programmable gate arrays, field-programmable gate array, computational complexity, fault diagnosis, logic testing, design for testability, fault model, logic CAD, table lookup, look-up tables, automatic test software, C-testable
56	Viviane Lucy Santos de Souza, Victor Wanderley Costa de Medeiros, Manoel Eusébio de Lima	Architecture for dense matrix multiplication on a high-performance reconfigurable system.	SBCCI	2009	DBLP DOI BibTeX RDF	BRAMs (RAM blocks), MAC (multiplier unit), RASC (reconfigurable application-specific computing), performance, FPGA (field programmable gate array), parallelism, matrix multiplication, data reuse
56	Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton	A synthesizable datapath-oriented embedded FPGA fabric.	FPGA	2007	DBLP DOI BibTeX RDF	embedded block, field programmable gate array, system-on-chip, synthesis, integrated circuit, datapath
56	Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici	Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!).	VTS	1996	DBLP DOI BibTeX RDF	BIST architecture, programmable logic blocks, field programmable gate arrays, VLSI, logic testing, built-in self test, built-in self-test, integrated circuit testing, automatic testing, FPGA testing, field programmable gate array testing
55	Nalini K. Ratha, Kalle Karu, Shaoyun Chen, Anil K. Jain 0001	A Real-Time Matching System for Large Fingerprint Databases.	IEEE Trans. Pattern Anal. Mach. Intell.	1996	DBLP DOI BibTeX RDF	minutiae points, field programmable gate array, indexing, image registration, Image database, fingerprint matching
54	Tim Good, Mohammed Benaissa	AES on FPGA from the Fastest to the Smallest.	CHES	2005	DBLP DOI BibTeX RDF	low area, Application Specific Instruction Processor (ASIP), Field Programmable Gate Array (FPGA), pipelined, Advanced Encryption Standard (AES), finite field, high throughput, design exploration
52	Behzad Mahdavikhah, Ramin Mafi, Shahin Sirouspour, Nicola Nicolici	Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture.	FPGA	2010	DBLP DOI BibTeX RDF	conjugate gradient (CG), finite-element modeling (FEM), field-programmable gate array (FPGA)
52	Ali El Kateeb, Lubna Al Azzawi	Low Cost HIV Testing System for Tele-Health Applications.	AINA Workshops (2)	2007	DBLP DOI BibTeX RDF	HIV kits, HIV screening, Field programmable gate array (FPGA), System-on-chip (SOC)
52	Slawomir Cichon, Marek Gorgon, Miroslaw Pac	Handel-C Design Enhancement for FPGA-Based DV Decoder.	ARC	2006	DBLP DOI BibTeX RDF	video decompression, field programmable gate array, Parallel algorithm, high level languages
52	Hima B. Damecharla, Kamal K. Varma, Joan Carletta, Amy E. Bell	FPGA implementation of a parallel EBCOT tier-1 encoder that preserves coding efficiency.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	EBCOT, JPEG 2000 image compression, arithmetic encoder, field programmable gate array
52	Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers	IEEE-Compliant IDCT on FPGA-Augmented TriMedia.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	inverse discrete cosine transform, field-programmable gate array, configurable computing, VLIW processor
52	Phillip A. Laplante, William Gilreath	One Instruction Set Computers for Image Processing.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	OISC, one-instruction computing, FPGA, field programmable gate array, image processing, reconfigurable computing
52	Paul Berube, Ashley Zinyk, José Nelson Amaral, Mike H. MacGregor	The Bank Nth Chance Replacement Policy for FPGA-Based CAMs.	FPL	2003	DBLP DOI BibTeX RDF	multizone cache, field programmable gate array, cache memories, memory systems, content addressable memories, replacement policy, digital design, Internet routing
52	Neil W. Bergmann, Yuk Ying Chung	Video Compression on FPGA-Based Custom Computers.	ICIP (1)	1997	DBLP DOI BibTeX RDF	FPGA-based custom computers, 2D DCT algorithms, Scalable Parallel Architecture for Concurrency Experiments, field programmable gate arrays, field programmable gate array, video compression, experimental result, SPACE, workstation, distributed arithmetic, super-computer, processing speed
52	T. Raju Damarla, Moon J. Chung, Wei Su, Gerald T. Michael	Faulty chip identification in a multi chip module system.	VTS	1996	DBLP DOI BibTeX RDF	faulty chip identification, multi chip module, linear space compressor, field programmable gate array, fault diagnosis, data compression, data compression, built-in self test, built-in self test, integrated circuit testing, fault detection, comparator, multichip modules
52	Shriram Kulkarni, Pinaki Mazumder, George I. Haddad	A high-speed 32-bit parallel correlator for spread spectrum communication.	VLSI Design	1996	DBLP DOI BibTeX RDF	pseudonoise codes, radio equipment, high speed pipelined digital parallel correlator, lattice field programmable gate array, 87 MHz, 11.5 ns, field programmable gate arrays, parallel processing, data stream, correlators, CDMA, pipeline processing, CMOS integrated circuit, CMOS digital integrated circuits, transceiver, spread spectrum communication, spread spectrum communication, digital radio, 32 bit, PN sequence
52	H. A. Xie, Kevin E. Forward, K. M. Adams, Suthikshn Kumar	An SBus Multi-Tracer and its applications.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	SBus Multi Tracer, SBus monitoring board, logic analyzer, bus analyzer, trace length, board memory, multi occurrences, trigger patterns, multiple partitions, tracing memory, systematic timing information, pattern occurrences, triggering patterns, SUN SPARC station, field programmable gate arrays, Field Programmable Gate Array, FPGA, logic testing, automatic test equipment, system buses, timing diagrams, computerised monitoring
52	Akihiro Tsutsui, Toshiaki Miyazaki, Kazuhisa Yamada, Naohisa Ohta	Special purpose FPGA for high-speed digital telecommunication systems.	ICCD	1995	DBLP DOI BibTeX RDF	special purpose FPGA, high-speed digital telecommunication systems, high-speed transport data processing, inter-chip connection mechanism, dedicated CAD system, field programmable gate arrays, field programmable gate array, programmable logic arrays, digital communication
52	Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose	Logic synthesis for a single large look-up table.	ICCD	1995	DBLP DOI BibTeX RDF	single large look-up table, LUT-based field-programmable gate array architectures, simulation time minimisation, compile-code, software simulation, field programmable gate arrays, Boolean function, logic design, logic synthesis, hardware accelerator, programmable logic arrays, table lookup, logic simulation, FPGA architectures, logic functions, on-chip memory, memory constraint
52	Jean-Francois Guillaud, Max Roger Pokam, Gérard Michel	An ATM-Based Multimedia Integrated Manufacturing System .	HPDC	1995	DBLP DOI BibTeX RDF	ATM-based multimedia integrated manufacturing system, high-speed communication technologies, intelligent network interface board, field programmable gate array component, high speed communication links, field programmable gate arrays, protocols, protocols, asynchronous transfer mode, multimedia systems, multimedia applications, computer integrated manufacturing, real time distributed systems
52	Max Roger Pokam, Jean-Francois Guillaud, Gérard Michel	Integrated multimedia in manufacturing networks using ATM.	LCN	1995	DBLP DOI BibTeX RDF	manufacturing networks, continuous media data flows, process control plants, multimedia application service element, intelligent communication board, high level communication functions, multimedia load, field programmable gate array, multimedia, asynchronous transfer mode, ATM, local area networks, multimedia computing, manufacturing processes, real-time distributed systems, factory automation, TCP/IP protocol
51	Didier Keymeulen, Ricardo Salem Zebulum, Rajeshuni Ramesham, Adrian Stoica, Srinivas Katkoori, Sharon Graves, Frank Novak, Charles Antill	Self-Adaptive System Based on Field Programmable Gate Array for Extreme Temperature Electronics.	AHS	2006	DBLP DOI BibTeX RDF
50	Minoru Watanabe, Fuminori Kobayashi	An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration Circuit.	IPDPS	2005	DBLP DOI BibTeX RDF
46	Kouhi Shinohara, Minoru Watanabe	Defect tolerance of holographic configurations in ORGAs.	IPDPS	2008	DBLP DOI BibTeX RDF
43	Jzau-Sheng Lin, Shao-Han Liu, Wu-Chih Hsieh, Yu-Yi Liao, HongChao Wang, QingHua Lan	Facial Expression Recognition Based on Field Programmable Gate Array.	IAS	2009	DBLP DOI BibTeX RDF
43	Peter J. Green, Desmond P. Taylor	Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmable Gate Array.	DELTA	2006	DBLP DOI BibTeX RDF
43	Peter J. Green, Desmond P. Taylor	Implementation of a High Speed Four Transmitter Space-Time Encoder using Field Programmable Gate Array and Parallel Digital Signal Processors.	DELTA	2006	DBLP DOI BibTeX RDF
43	Tyler J. Moeller, David R. Martinez	Field Programmable Gate Array Based Radar Front-End Digital Signal Processing.	FCCM	1999	DBLP DOI BibTeX RDF
43	Martine D. F. Schlag, Pak K. Chan, Jackson Kong	Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
41	W. Shi, K. Kumar, Fabrizio Lombardi	On the Complexity of Switch Programming in Fault-Tolerant-Configurable Chips.	DFT	2000	DBLP DOI BibTeX RDF
40	Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu 0001	Routing for symmetric FPGAs and FPICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
38	Minoru Watanabe, Fuminori Kobayashi	Optically Reconfigurable Gate Arrays vs. ASICs.	APCCAS	2006	DBLP DOI BibTeX RDF
38	Erik R. Altman	CPUs and GPUs: Who Owns the Future?	IEEE Micro	2011	DBLP DOI BibTeX RDF	performance, field-programmable gate array, GPU, productivity, application-specific integrated circuit, programming model, CPU
38	Christos Kyrkou, Christos Ttofis, Theocharis Theocharides	FPGA-Accelerated Object Detection Using Edge Information.	FPL	2011	DBLP DOI BibTeX RDF	Field Programmable Gate Array, Object Detection
38	Marc-André Daigneault, Jean-Pierre David	Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	time-to-digital converter, vernier method, field programmable gate array, dynamic reconfiguration
38	Muhammad Ali Siddiqi, Nabeel Samad, Shahid Masud, Faheem Sheikh	FPGA-based Implementation of Efficient Sample Rate Conversion for Software Defined Radios.	CIT	2010	DBLP DOI BibTeX RDF	Sample Rate Conversion, CIC filter, Farrow Interpolator, Field Programmable Gate Array (FPGA), Software Radio
38	Yuan Ruan, Weibing Yang, Mingyu Chen 0001, Xiaofang Zhao, Jianping Fan 0002	Robust TCP Reassembly with a Hardware-Based Solution for Backbone Traffic.	NAS	2010	DBLP DOI BibTeX RDF	TCP reassembly, Field-programmable gate array, backbone network
38	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne	Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	Field Programmable Compressor Tree (FPCT), compressor tree, Field Programmable Gate Array (FPGA)
38	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj	3D configuration caching for 2D FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	field programmable gate array (fpga), reconfigurable computing, 3d integration, configuration caching
38	Jason Helge Anderson	Emerging application domains: research challenges and opportunities for FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	performance, field-programmable gate array, fpga, applications, high-performance computing, power, reconfigurable computing
38	Wu Qiang, Chen He	The Design of a Large Point Reconfigured FFT Based on FPGA.	IITSI	2009	DBLP DOI BibTeX RDF	two dimension process, trigonometric function interpolation, Field Programmable Gate Array (FPGA), reconfiguration, Fast Fourier Transform (FFT), miniaturization
38	Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk	A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	Field programmable gate array, system-on-chip, integrated circuit, silicon debug
38	Peter R. Cappello	Application-specific Processor Architecture: Then and Now.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	field-programmable gate array, FPGA, computer architecture, taxonomy, systolic array, processor array, application-specific processor, general-purpose processor
38	Knut Wold, Chik How Tan	Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings.	ReConFig	2008	DBLP DOI BibTeX RDF	Field Programmable Gate Array, Ring Oscillator, True Random Number Generator
38	Tian Lan, Jinlin Zhang	FPGA Implementation of an Adaptive Noise Canceller.	ISIP	2008	DBLP DOI BibTeX RDF	least mean square (LMS) filtering, field programmable gate array (FPGA), hardware implementation
38	Somnath Paul, Swarup Bhunia	Reconfigurable computing using content addressable memory for improved performance and resource usage.	DAC	2008	DBLP DOI BibTeX RDF	field programmable gate array (FPGA), content addressable memory, resource utilization
38	Ali Ahmadinia	Optimal Free-Space Management and Routing-Conscious Dynamic Placement for Reconfigurable Devices.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	free-space manager, routing-conscious placement, line-sweep technique, optimal runtime, field-programmable gate array (FPGA), lower bounds, Reconfigurable hardware, geometric optimization, module placement
38	Thomas Eisenbarth 0001, Tim Güneysu, Christof Paar, Ahmad-Reza Sadeghi, Dries Schellekens, Marko Wolf	Reconfigurable trusted computing in hardware.	STC	2007	DBLP DOI BibTeX RDF	field programmable gate array (FPGA), trusted computing, trusted platform module (TPM)
38	Scott C. Smith	Design of a logic element for implementing an asynchronous FPGA.	FPGA	2007	DBLP DOI BibTeX RDF	NULL convention logic (NCL), asynchronous logic design, field programmable gate array (FPGA), reconfigurable logic, delay-insensitive circuits
38	Ying Huang, Chunyuan Zhang, Dong Liu 0022, Yi Li, Sheng-xin Weng	The Design on SEU-Tolerant Information Processing System of the On-Board-Computer.	APPT	2007	DBLP DOI BibTeX RDF	Dual Fault-Tolerant, Triple Module Redundancy, Cost-Off-The-Shelf, Field Programmable Gate Array, Single-Event-Upsets
38	Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang	Post-placement leakage optimization for partially dynamically reconfigurable FPGAs.	ISLPED	2007	DBLP DOI BibTeX RDF	post-placement optimization, scheduling, field-programmable gate array, leakage
38	Wilfried Kubinger, Franz Rinnerthaler, Christoph Sulzbachner, Josef Langer, Martin Humenberger	An Embedded Vision Sensor for Robot Soccer.	EUROCAST	2007	DBLP DOI BibTeX RDF	Embedded Vision System, Field-programmable Gate Array (FPGA), Digital Signal Processor (DSP), Robot Soccer
38	Stefan Lemsitzer, Johannes Wolkerstorfer, Norbert Felber, Matthias Braendli	Multi-gigabit GCM-AES Architecture Optimized for FPGAs.	CHES	2007	DBLP DOI BibTeX RDF	Galois/Counter Mode (GCM), hybrid multiplier, Field Programmable Gate Array (FPGA), Very Large Scale Integration (VLSI), Advanced Encryption Standard (AES), high throughput, digit-serial multiplier, bit-parallel multiplier
38	John McAllister, Roger F. Woods, Richard L. Walke, Darren Gerard Reilly	Multidimensional DSP Core Synthesis for FPGA.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	rapid implementation, field programmable gate array, heterogeneous system, system level design, dataflow graph, Architectural synthesis
38	Wai Shing Lau, Kin-Hong Lee, Kwong-Sak Leung	A hybridized genetic parallel programming based logic circuit synthesizer.	GECCO	2006	DBLP DOI BibTeX RDF	FlowMap, a hybridized genetic parallel programming logic circuit synthesizer, genetic parallel programming, field programmable gate array, technology mapping, LookUp table
38	Andrés David García García, Luis Fernando González Pérez, Reynaldo Félix Acuña	Power Consumption Management on FPGAs.	CONIELECOMP	2005	DBLP DOI BibTeX RDF	Genetic Algorithms, Field Programmable Gate Array, Power Consumption, Partial Reconfiguration, Circuit Design
38	Choudhury A. Rahman, Wael M. Badawy	A quarter pel full search block motion estimation architecture for H.264/AVC.	ICME	2005	DBLP DOI BibTeX RDF	CIF frame sequence, quarter pel full search, block motion estimation architecture, H.264-AVC encoder, Xilinx Virtex2 FPGA, field programmable gate array, hardware description language, Verilog HDL
38	Hamid Fadishei, Morteza Saheb Zamani, Masoud Sabaei	A novel reconfigurable hardware architecture for IP address lookup.	ANCS	2005	DBLP DOI BibTeX RDF	field-programmable gate array (FPGA), application specific integrated circuit (ASIC), hashing, reconfigurable hardware, longest prefix matching, IP address lookup
38	Mehdi Baradaran Tahoori	Application-Specific Bridging Fault Testing of FPGAs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	field-programmable gate array, interconnect, satisfiability, bridging fault
38	Philip Brisk, Adam Kaplan, Majid Sarrafzadeh	Area-efficient instruction set synthesis for reconfigurable system-on-chip designs.	DAC	2004	DBLP DOI BibTeX RDF	field-programmable gate array (FPGA), compiler, resource sharing, integer linear programming (ILP)
38	John W. Lockwood, Christopher E. Neely, Christopher K. Zuver, David Lim	Automated tools to implement and test Internet systems in reconfigurable hardware.	Comput. Commun. Rev.	2003	DBLP DOI BibTeX RDF	network intrusion detection and prevention, Internet, Field Programmable Gate Array (FPGA), networks, tools, firewall, reconfigurable hardware
38	Wai-Kei Mak	I/O placement for FPGAs with multiple I/O standards.	FPGA	2003	DBLP DOI BibTeX RDF	I/O placement, I/O standards, field-programmable gate array, placement
38	Tao Lin, Zhou Zhengou	The Implementation of 100MHz Data Acquisition Based on FPGA.	IWSOC	2003	DBLP DOI BibTeX RDF	Compression Sampling, flag, field programmable gate array (FPGA), memory, VHDL, Top-Down
38	Byoungro So, Pedro C. Diniz, Mary W. Hall	Using estimates from behavioral synthesis tools in compiler-directed design space exploration.	DAC	2003	DBLP DOI BibTeX RDF	synthesis techniques for reconfigurable computing, field-programmable-gate-array, high-level synthesis, rapid prototyping, design space exploration
38	Mehdi Baradaran Tahoori	Using satisfiability in application-dependent testing of FPGA interconnects.	DAC	2003	DBLP DOI BibTeX RDF	field-programmable gate array, interconnect
38	Joan Carletta, Robert J. Veillette, Frederick W. Krach, Zhengwei Fang	Determining appropriate precisions for signals in fixed-point IIR filters.	DAC	2003	DBLP DOI BibTeX RDF	finite word length effects, infinite impulse response filter, field programmable gate array, design methodology
38	Hongbing Fan, Yu-Liang Wu, Yao-Wen Chang	Comment on Generic Universal Switch Blocks.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	universal switch block design, Field programmable gate array, FPGA routing
38	Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang	Performance-driven placement for dynamically reconfigurable FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	field-programmable gate array, placement, dynamically reconfigurable, layout, Computer-aided design of VLSI
38	Uwe Meyer-Bäse, Antonio García 0001, Fred J. Taylor	Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	field-programmable logic (FPL), complex programmable logic devices (CPLD), zero-IF filter, field programmable gate array (FPGA), digital signal processing (DSP), residue number system (RNS), channelizer
38	Wei-Je Huang, Subhasish Mitra, Edward J. McCluskey	Fast Run-Time Fault Location in Dependable FPGA-Based Applications.	DFT	2001	DBLP DOI BibTeX RDF	Run-time fault location, Field-Programmable Gate Array (FPGA), concurrent error detection, on-line testing
38	Seok-Bum Ko, Tian Xia, Jien-Chung Lo	Efficient Parity Prediction in FPGA.	DFT	2001	DBLP DOI BibTeX RDF	Fault tolerance, Field Programmable Gate Array, Space Application
38	Yao-Wen Chang, Kai Zhu 0001, D. F. Wong 0001	Timing-driven routing for symmetrical array-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	field-programmable gate array, synthesis, layout, computer-aided design of VLSI
38	Douglas Chang, Malgorzata Marek-Sadowska	Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Dynamically reconfigurable FPGAs, time-mulitplexed FPGA, Dharma, DPGA, field programmable gate array, partitioning, reconfigurable computing, sequential circuit, force directed scheduling
38	Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Jignesh Shah, Robert Cook	Dynamic Reconfiguration to Support Concurrent Applications.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	scheduling, field programmable gate array (FPGA), resource management, reconfiguration, Configurable computing
38	Jack S. N. Jean, Xuejun Liang, Brian Drozd, Karen A. Tomko	Accelerating an IR Automatic Target Recognition Application with FPGAs.	FCCM	1999	DBLP DOI BibTeX RDF	Field Programmable Gate Array (FPGA), Reconfigurable Computing, Automatic Target Recognition, Adaptive Computing
38	Gerardo Orlando, Christof Paar	A Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms.	FCCM	1999	DBLP DOI BibTeX RDF	Galois Fields multiplier, field programmable gate array application, cryptography, elliptic curve cryptography
38	Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra	Transient and Permanent Fault Diagnosis for FPGA-Based TMR Systems.	DFT	1999	DBLP DOI BibTeX RDF	transient fault detection, Field Programmable Gate Array, TMR systems
38	John C. Lach, William H. Mangione-Smith, Miodrag Potkonjak	Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures.	DFT	1999	DBLP DOI BibTeX RDF	fault-tolerance, Field programmable gate array (FPGA)
38	John C. Lach, William H. Mangione-Smith, Miodrag Potkonjak	Robust FPGA Intellectual Property Protection Through Multiple Small Watermarks.	DAC	1999	DBLP DOI BibTeX RDF	field programmable gate array (FPGA), watermarking, intellectual property protection
38	Fran Hanchek, Shantanu Dutt	Methodologies for Tolerating Cell and Interconnect Faults in FPGAs.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	cell faults, wiring faults, Fault tolerance, Field Programmable Gate Array (FPGA), reconfiguration, yield improvement
38	James R. Anderson 0001, Siddharth Sheth, Kaushik Roy 0001	A Coarse-Grained FPGA Architecture for High-Performance FIR Filtering.	FPGA	1998	DBLP DOI BibTeX RDF	finite impluse response filtering, field programmable gate array, architecture, digital signal processing
38	Dimitrios Stiliadis, Anujan Varma	A Reconfigurable Hardware Approach to Network Simulation.	ACM Trans. Model. Comput. Simul.	1997	DBLP DOI BibTeX RDF	ATM switch scheduling, hardware simulation, field-programmable gate array
38	Dane Kottke, Paul D. Fiore	Systolic Array for Acceleration of Template Based ATR.	ICIP (1)	1997	DBLP DOI BibTeX RDF	radar clutter, template-based ATR, Hausdorff distance-based clutter/target discrimination, detection thresholds, pre-processing parameters, radar detection, binary raster image, performance, field programmable gate array, systolic array, automatic target recognition, detection probability, detection performance
38	Fran Hanchek, Shantanu Dutt	Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs.	VLSI Design	1996	DBLP DOI BibTeX RDF	circuit reconfiguration, node covering, fault tolerance, field programmable gate array (FPGA), yield improvement
35	Sheng Wang, Shiwei Feng 0001, Yuxuan Xiao, Chaoxu Hu, Shijie Pan	Build-in compact and efficient temperature sensor array on field programmable gate array.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
35	Kejie Huang, Rong Zhao, Wei He, Yong Lian 0001	High-Density and High-Reliability Nonvolatile Field-Programmable Gate Array With Stacked 1D2R RRAM Array.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
35	Paul Beckett	A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
35	David Marple	An MPGA-Like FPGA.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
34	Sayed Ali Seif Kashani, Hossein Karimiyan Alidash, Sandeep Miryala	Schottky-barrier graphene nanoribbon field-effect transistors-based field-programmable gate array's configurable logic block and routing switch.	IET Circuits Devices Syst.	2017	DBLP DOI BibTeX RDF
33	Daniel Mange, Eduardo Sanchez, André Stauffer, Gianluca Tempesti, Pierre Marchal, Christian Piguet	Embryonics: a new methodology for designing field-programmable gate arrays with self-repair and self-replicating properties.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
32	Gerald Tripp	Regular expression matching with input compression: a hardware design for use within network intrusion detection systems.	J. Comput. Virol.	2007	DBLP DOI BibTeX RDF
31	Minoru Watanabe, Fuminori Kobayashi	Power consumption advantage of a dynamic optically reconfigurable gate array.	IPDPS	2006	DBLP DOI BibTeX RDF
31	Minoru Watanabe, Fuminori Kobayashi	A High-Density Optically Reconfigurable Gate Array Using Dynamic Method.	FPL	2004	DBLP DOI BibTeX RDF
30	Panagiotis D. Michailidis, Konstantinos G. Margaritis	Implementation of a programmable array processor architecture for approximate string matching algorithms on FPGAs.	IPDPS	2006	DBLP DOI BibTeX RDF
29	Jun Dong, Tongfei Wang, Yueming Deng, Runmin Wang	Adaptive wavelet transform defogging scheme for real-time video restoration with field programmable gate array implementation.	J. Electronic Imaging	2024	DBLP DOI BibTeX RDF
29	Yadongyang Zhu, Shuguang Zhao, Fudong Zhang, Wei Wei, Fa Zhao	Edge-Intelligence-Based Seismic Event Detection Using a Hardware-Efficient Neural Network With Field-Programmable Gate Array.	IEEE Internet Things J.	2024	DBLP DOI BibTeX RDF
29	Marc Majoral, Javier Arribas, Carles Fernández-Prades	Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform.	Sensors	2024	DBLP DOI BibTeX RDF