Search results for "layout"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
94	Louis Monier, Ramsey W. Haddad, Jeremy Dion	Recursive layout generation.	ARVLSI	1995	DBLP DOI BibTeX RDF	BiCMOS digital integrated circuits, recursive layout generation, layout directives, netlist description, hand-drawn layout, synthesized layout, overall layout, dense VLSI, VLSI, logic CAD, circuit layout CAD, microprocessor chips, microprocessor chips, VLSI chips, seamless integration
82	Ken Kennedy, Ulrich Kremer	Automatic Data Layout for Distributed-Memory Machines.	ACM Trans. Program. Lang. Syst.	1998	DBLP DOI BibTeX RDF	high performance Fortran
81	Neff Walker, John B. Smelcer	A comparison of selection time from walking and pull-down menus.	CHI	1990	DBLP DOI BibTeX RDF
81	Terry Winograd	What can we teach about human-computer interaction? (plenary address).	CHI	1990	DBLP DOI BibTeX RDF
81	Hans Brunner	A snapshot of natural language interfaces (panel).	CHI	1990	DBLP DOI BibTeX RDF
81	Jakob Nielsen	Designing for international use (panel).	CHI	1990	DBLP DOI BibTeX RDF
81	S. Joy Mountford	Designers: meet your users (panel).	CHI	1990	DBLP DOI BibTeX RDF	Apple Computer, HyperCard, Inc
81	Marcy Telles	Updating an older interface.	CHI	1990	DBLP DOI BibTeX RDF	WordStar
74	Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri	A high level language for pre-layout extraction in parasite-aware analog circuit synthesis.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	MSL, pre-layout extraction, parasitics, analog VLSI
74	Andrew Sears	Layout Appropriateness: A Metric for Evaluating User Interface Widget Layout.	IEEE Trans. Software Eng.	1993	DBLP DOI BibTeX RDF	layout appropriateness, user interface widget layout, simple task descriptions, Layout Appropriateness, simplified task analysis, LA-optimal layout, performance evaluation, user interfaces, human factors, software metrics, weighting
70	Neungsoo Park, Bo Hong, Viktor K. Prasanna	Tiling, Block Data Layout, and Memory Hierarchy Performance.	IEEE Trans. Parallel Distributed Syst.	2003	DBLP DOI BibTeX RDF	Block data layout, TLB misses, memory hierarchy, tiling, cache misses
70	Peter Lüders, Rolf Ernst	Research report: improving browsing in information by the automatic display layout.	INFOVIS	1995	DBLP DOI BibTeX RDF	automatic display layout, graph structured information, automatic layout system, time consuming, manual layout, user requests, display layouts, information retrieval, graphical user interfaces, user modelling, user model, human factors, computer animation, information network, graphical representations, information browsing, layout algorithms
70	Sanjay Rekhi, J. Donald Trotter	HAL: heuristic algorithms for layout synthesis.	ARVLSI	1995	DBLP DOI BibTeX RDF	layout synthesis, graph theory based algorithms, leaf cells, common poly gates, 1-1/2-d layout style, common circuit nodes, transistor sets, symbolic layouts, static dual type, static CMOS circuitry, pullup network, pulldown network, dynamic logic styles, graph theory, network topology, logic CAD, heuristic algorithms, circuit layout CAD, CMOS logic circuits, CMOS circuits, GENIE, run time efficient, layout area
67	Akira Matsubayashi	VLSI layout of trees into grids of minimum width.	SPAA	2003	DBLP DOI BibTeX RDF	cutwidth, grid, tree, graph embedding, VLSI layout, graph layout, aspect ratio
64	Hart Anway, Greg Farnham, Rebecca Reid	PLINT layout system for VLSI chips.	DAC	1985	DBLP DOI BibTeX RDF	IC placement, IC routing, macrocell layout, standard cell layout, VLSI, computer-aided design, IC layout
62	Syed M. Alam, Donald E. Troxel, Carl V. Thompson	A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated Circuits.	ISQED	2002	DBLP DOI BibTeX RDF	3D integrated circuit, 3D IC layout, inter-wafer via, reliability CAD tool, FPGA, performance analysis, reliability analysis
60	Shuo Zhang, Wayne Wei-Ming Dai	TEG: a new post-layout optimization method.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
59	Toyohide Watanabe, Qin Luo, Noboru Sugie	Layout Recognition of Multi-Kinds of Table-Form Documents.	IEEE Trans. Pattern Anal. Mach. Intell.	1995	DBLP DOI BibTeX RDF	Recognition paradigm for multi-kinds of table-form documents, automatic acquisition of layout knowledge, recognition of document classes, recognition of layout structures, structure description tree, classification tree
57	Oguzhan Ozmen, Kenneth Salem, Jiri Schindler, Steve Daniel	Workload-aware storage layout for database systems.	SIGMOD Conference	2010	DBLP DOI BibTeX RDF	layout, physical design, storage systems
56	Tim Dwyer, Kim Marriott, Falk Schreiber, Peter J. Stuckey, Michael Woodward, Michael Wybrow	Exploration of Networks using overview+detail with Constraint-based cooperative layout.	IEEE Trans. Vis. Comput. Graph.	2008	DBLP DOI BibTeX RDF
55	Frederik Beeftink, Arjan J. van Genderen, N. P. van der Meijs	Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits.	ICCD	1995	DBLP DOI BibTeX RDF	MOS integrated circuits, bipolar integrated circuits, BiCMOS integrated circuits, layout-to-circuit extraction, high-speed MOS integrated circuits, bipolar/BiCMOS integrated circuits, device recognition, equivalent network, layout parasitics, interconnects, circuit analysis computing, circuit layout CAD, Space, Spice, device modeling
54	Tiziana Calamoneri, Annalisa Massini	Nearly Optimal Three Dimensional Layout of Hypercube Networks.	GD	2003	DBLP DOI BibTeX RDF	Three Dimensional Layout, VLSI layout volume, Hypercube Network
54	Mohamed Dessouky, Marie-Minerve Louërat	A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits.	ISQED	2000	DBLP DOI BibTeX RDF	Analog layout, layout generation
54	Joni Dambre, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout	On rent's rule for rectangular regions.	SLIP	2001	DBLP DOI BibTeX RDF	layout Rent parameters, rectangular layout region, wirelength distribution, Rent's rule
52	Masahiro Nagamatu, Shakeel Ismail, Torao Yanaru	Lagrangian method for wire routing of layout design.	ANNES	1995	DBLP DOI BibTeX RDF	wire routing, layout design, LSI layout design, continuous valued constrained optimization problem, continuous valued wires, dynamic equations, small switchbox routing problems, rip-up reroute maze router, neural nets, network routing, circuit layout CAD, circuit optimisation, integrated circuit layout, large scale integration, neurocomputing, Lagrangian method
52	Chengliang Zhang, Martin Hirzel	Online Phase-Adaptive Data Layout Selection.	ECOOP	2008	DBLP DOI BibTeX RDF
52	Takayoshi Noguchi, Jiro Tanaka	Interactive Layout Method for Object Diagrams of OMT.	APSEC	1999	DBLP DOI BibTeX RDF	software development tool, object-oriented methodology
51	Jin-Tai Yan	A simple yet effective genetic approach for the orientation assignment on cell-based layout.	VLSI Design	1996	DBLP DOI BibTeX RDF	genetic approach, orientation assignment, cell-based layout, total wire length minimisation, placement phase, routing area reduction, orientation states, vertical orientation bit, horizontal orientation bit, genetic algorithms, VLSI, VLSI design, network routing, circuit layout CAD, integrated circuit layout
51	Winfried Graf, Stefan Neurohr	Constraint-Based Layout in Visual Program Design.	VL	1995	DBLP DOI BibTeX RDF	visual program design, constraint-based layout, visual program layout, graphical editing tasks, InLay constraint-based graphical editor, animated chart diagram layout, presentation part abstraction, active display object focussing, graphical history editing, hierarchical information structure visualisation, multimedia, data structures, knowledge based systems, interaction techniques, programming environments, visual programming, computer animation, intelligent system, data visualisation, multimedia computing, program visualization, constraint handling, visual programming environments, dynamic displays, communication media
51	Nikolaos G. Bourbakis, Mohammad Mortazavi	An efficient building block layout methodology for compact placement.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	building block layout methodology, compact placement, synthesis placement, GEOMETRIA, geometric reshapings, VLSI regulation, functional performance, connection lines, occupied chip area, neighboring relations, dead space, open holes, channels merging process, legal overlapping, VLSI, formal languages, formal language, network routing, circuit layout CAD, compaction, global routing, integrated circuit layout, integrated circuit interconnections, local routing
50	Tim Dwyer, Kim Marriott, Michael Wybrow	Integrating Edge Routing into Force-Directed Layout.	GD	2006	DBLP DOI BibTeX RDF	constrained optimisation, edge routing, graph layout, force-directed layout
50	Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi	Correct-by-construction layout-centric retargeting of large analog designs.	DAC	2004	DBLP DOI BibTeX RDF	analog integrated circuit design, analog layout automation, analog synthesis and optimization, layout symmetry
50	Hyunmo Kang, Ben Shneiderman, Gregory J. Wolff	Dynamic Layout Management in a Multimedia Bulletin Board.	HCC	2002	DBLP DOI BibTeX RDF	Multimedia Bulletin Board (MBB), layout management, dynamic layout template (DLT), collaboration, asynchronous communication
50	Toshiyuki Masui	Evolutionary Learning of Graph Layout Constraints from Examples.	ACM Symposium on User Interface Software and Technology	1994	DBLP DOI BibTeX RDF	graphic object layout, genetic algorithms, genetic programming, adaptive user interface, programming by example, graph layout, TeX
49	Edmund K. Burke, Karen M. Daniels, Graham Kendall	07112 Abstracts Collection - Cutting, Packing, Layout and Space Allocation.	Cutting, Packing, Layout and Space Allocation	2007	DBLP BibTeX RDF
49	Edmund K. Burke, Karen M. Daniels, Graham Kendall	07112 Summary - Cutting, Packing, Layout and Space Allocation.	Cutting, Packing, Layout and Space Allocation	2007	DBLP BibTeX RDF
49	Malgorzata Marek-Sadowska	Issues in Timing Driven Layout.	Algorithmic Aspects of VLSI Layout	1993	DBLP DOI BibTeX RDF
49	Teofilo F. Gonzalez, Sing-Ling Lee	Routing around two Rectangles to minimize the Layout Area.	Algorithmic Aspects of VLSI Layout	1993	DBLP DOI BibTeX RDF
49	Christof Lutteroth, Gerald Weber	Modular Specification of GUI Layout Using Constraints.	Australian Software Engineering Conference	2008	DBLP DOI BibTeX RDF	user interfaces, constraints, modularity, layout
49	Ian Kuon, Aaron Egier, Jonathan Rose	Design, layout and verification of an FPGA using automated tools.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA, programmable logic, PLD, automatic layout
49	Zhan Chen, Fook-Luen Heng	A Fast Minimum Layout Perturbation Algorithm for Electromigration Reliability Enhancement.	DFT	1998	DBLP DOI BibTeX RDF	layout compaction, design for reliability, electromigration
47	Akif Sultan, John Faricelli, Sushant Suryagandh, Hans vanMeer, Kaveri Mathur, James Pattison, Sean Hannon, Greg Constant, Kalyana Kumar, Kevin Carrejo, Joe Meier, Rasit Onur Topaloglu, Darin Chan, Uwe Hahn, Thorsten Knopp, Victor Andrade, Bill Gardiol, Steve Hejl, David Wu, James Buller, Larry Bair, Ali Icel, Yuri Apanovich	CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design.	ISQED	2009	DBLP DOI BibTeX RDF
47	Hiroaki Yoshida, Kaushik De, Vamsi Boppana	Accurate pre-layout estimation of standard cell characteristics.	DAC	2004	DBLP DOI BibTeX RDF	cell characterization, transistor-level optimization, standard cell
47	Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky	Filling algorithms and analyses for layout density control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
47	Kazuo Sugihara, Kazunari Yamamoto, Isao Miyamoto	Automatic Layout of Diagrams for Software Specification.	SEKE	1992	DBLP DOI BibTeX RDF
47	David Eppstein, Elena Mumford, Bettina Speckmann, Kevin Verbeek	Area-universal rectangular layouts.	SCG	2009	DBLP DOI BibTeX RDF	rectangular layouts
47	Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi	Multilevel symmetry-constraint generation for retargeting large analog layouts.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
46	Floriana Esposito, Donato Malerba, Giovanni Semeraro	A knowledge-based approach to the layout analysis.	ICDAR	1995	DBLP DOI BibTeX RDF	top-down technique, typesetting conventions, generic knowledge, processed documents, Layout EXpert, knowledge based systems, document image processing, document image, layout analysis, knowledge-based approach, LEX
44	Christof Lutteroth, Robert Strandh, Gerald Weber	Domain Specific High-Level Constraints for User Interface Layout.	Constraints An Int. J.	2008	DBLP DOI BibTeX RDF	Auckland Layout Model, Constraint, GUI
44	Sambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy	On Efficient and Robust Constraint Generation for Practical Layout Legalization.	ISQED	2008	DBLP DOI BibTeX RDF	Layout legalization, constraint reduction, compaction, constraint generation
44	Payman Zarkesh-Ha, Ken Doniger	Stochastic interconnect layout sensitivity model.	SLIP	2007	DBLP DOI BibTeX RDF	critical area analysis, layout sensitivity, reliability, stochastic model, yield, design for manufacturability, defect density
44	Yuying Wang, Xingshe Zhou 0001	Mutual Effect of Instruction Layout Optimization and Instruction Memory Hierarchy.	ICPP Workshops	2007	DBLP DOI BibTeX RDF	Instruction Layout Optimization, Instruction Cache Miss Rate, Cache Memory Hierarchy
44	Tim Dwyer, Yehuda Koren, Kim Marriott	IPSep-CoLa: An Incremental Procedure for Separation Constraint Layout of Graphs.	IEEE Trans. Vis. Comput. Graph.	2006	DBLP DOI BibTeX RDF	stress majorization, force directed algorithms, constraints, layout, Graph drawing, multidimensional scaling
44	Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose	Automatic transistor and physical design of FPGA tiles from an architectural specification.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA, programmable logic, PLD, automatic layout
44	Carlton Bickford, Marie S. Teo, Gary Wallace, John A. Stankovic, Krithi Ramamritham	A robotic assembly application on the Spring real-time system.	IEEE Real Time Technology and Applications Symposium	1996	DBLP DOI BibTeX RDF	printed circuit manufacture, printed circuit layout, robotic assembly application, Spring real-time system, run-time system support, predictability demands, robotic work-cell, circuit board assembly, user understanding, target hardware properties, process layout, resource layout, shared resource usage, process suspension, efficient run-time representation, real-time systems, robots, timing, completeness, flexibility, reengineering, timing analysis, circuit layout CAD, assembling, systems re-engineering, interprocess communication, program representation, porting, ease of use, industrial robots, software development tools
44	Sandip Das 0001, Bhargab B. Bhattacharya	Channel routing in Manhattan-diagonal model.	VLSI Design	1996	DBLP DOI BibTeX RDF	Manhattan-diagonal model, layout grid, cyclic vertical constraints, low via count, reduced wire length, VLSI, network routing, circuit layout CAD, VLSI layout, integrated circuit layout, channel routing, output-sensitive algorithm
44	Saibal Das, Sanjeev Saxena	Parallel algorithms for single row routing in narrow streets.	VLSI Design	1995	DBLP DOI BibTeX RDF	narrow streets, optimal layout, parallel algorithms, parallel algorithms, VLSI, network routing, circuit layout CAD, VLSI layout, integrated circuit layout, single row routing, IC design, CREW PRAM, tree machine
43	Yuji Shigehiro, Takashi Nagata, Isao Shirakawa, Itthichai Arungsrisangchai, Hiromitsu Takahashi	Automatic layout recycling based on layout description and linear programming.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
43	Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala	Efficient Analog/RF Layout Closure with Compaction Based Legalization.	VLSI Design	2009	DBLP DOI BibTeX RDF
43	Tim Dwyer, Kim Marriott, Michael Wybrow	Topology Preserving Constrained Graph Layout.	GD	2008	DBLP DOI BibTeX RDF
43	Xiaofan Lin	Active Document Layout Synthesis.	ICDAR	2005	DBLP DOI BibTeX RDF
43	Ismail Kadayif, Mahmut T. Kandemir	Quasidynamic Layout Optimizations for Improving Data Locality.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	array-intensive computations, dynamic optimization, Optimizing compilers, data locality
43	Pierluigi Daglio, David Iezzi, Danilo Rimondi, Carlo Roma, Salvatore Santapa	Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components.	DATE	2004	DBLP DOI BibTeX RDF
43	Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, C.-J. Richard Shi	CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects.	ASP-DAC	2004	DBLP DOI BibTeX RDF
43	Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng	Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis.	FPL	2004	DBLP DOI BibTeX RDF
43	Sanjay Khanna, Shaodi Gao, Krishnaiyan Thulasiraman	Parallel hierarchical global routing for general cell layout.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	parallel hierarchical global routing, general cell layout, hierarchical decomposition strategy, network flow optimization, parallel algorithms, parallel processing, VLSI, integer programming, integer programming, routing algorithm, network routing, circuit layout CAD, integrated circuit layout, shared-memory machine
42	Manjit Borah, Robert Michael Owens, Mary Jane Irwin	Fast algorithm for performance-oriented Steiner routing.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	performance-oriented Steiner routing, fast routing algorithm, Elmore delay minimisation, layout generators, computational complexity, VLSI, data structures, data structures, delays, iterative methods, network routing, circuit layout CAD, integrated circuit layout, iterative techniques
41	Saeedeh Bakhshi, Hamid Sarbazi-Azad	Efficient VLSI Layout of Edge Product Networks.	DELTA	2008	DBLP DOI BibTeX RDF	Edge graph product, Collinear layout, Interconnection networks, Networks on chip, VLSI layout
41	Derek Hoiem, Alexei A. Efros, Martial Hebert	Recovering Surface Layout from an Image.	Int. J. Comput. Vis.	2007	DBLP DOI BibTeX RDF	surface layout, spatial layout, geometric context, model-driven segmentation, multiple segmentations, context, object recognition, object detection, image understanding, scene understanding
41	Ben L. Titzer, Jens Palsberg	Vertical object layout and compression for fixed heaps.	CASES	2007	DBLP DOI BibTeX RDF	heap optimization, object layout, pointer compression, program data compression, reference compression, vertical object layout, microcontrollers
41	Yasuto Ishitani	Document Layout Analysis Based on Emergent Computation.	ICDAR	1997	DBLP DOI BibTeX RDF	Structural Layout Analysis, Bottom Up Strategy, Document Image Analysis, Document Layout Analysis
41	Anikó Simon, Jean-Christophe Pret, A. Peter Johnson	(Chem)DeTE/X automatic generation of a markup language description of (chemical) documents from bitmap images.	ICDAR	1995	DBLP DOI BibTeX RDF	markup language description, bitmap images, style file, layout recognition, Kruskal's algorithm, physical page structure, chemical documents, recursive parsing algorithm, document style description language, DSDL, document processing, layout analysis, document handling, scientific publications, page description languages
40	Joseph H. Goldberg, Jonathan I. Helfman, Lynne Martin	Information distance and orientation in liquid layout.	CHI	2008	DBLP DOI BibTeX RDF	browser width, liquid layout, widescreen design, usability evaluation
40	Huijun Zhu, Peng Gu, Jun Wang 0001	Shifted declustering: a placement-ideal layout scheme for multi-way replication storage architecture.	ICS	2008	DBLP DOI BibTeX RDF	multi-way replication, optimal parallelism, data layout
40	Christof Lutteroth, Gerald Weber	User interface layout with ordinal and linear constraints.	AUIC	2006	DBLP BibTeX RDF	2D layout, formal constraints, user interface design, tables
40	Simon Lok, Steven Feiner, Gary Ngai	Evaluation of visual balance for automated layout.	IUI	2004	DBLP DOI BibTeX RDF	automated layout, visual balance
40	Seong-Whan Lee, Dae-Seok Ryu	Parameter-Free Geometric Document Layout Analysis.	IEEE Trans. Pattern Anal. Mach. Intell.	2001	DBLP DOI BibTeX RDF	Geometric document layout analysis, parameter-free method, periodicity estimation, page segmentation, multiscale analysis
40	Chau-Shen Chen, TingTing Hwang	Layout Driven Selection and Chaining of Partial Scan Flip-Flops.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	design for testability, matching, placement, global routing, partial scan, digital testing, layout optimization
40	Edmund K. Burke, Karen M. Daniels, Graham Kendall (eds.)	Cutting, Packing, Layout and Space Allocation, 13.03. - 16.03.2007	Cutting, Packing, Layout and Space Allocation	2007	DBLP BibTeX RDF
40	S. M. Kang, M. Sriram	Binary formulations for Placement and Routing Problems.	Algorithmic Aspects of VLSI Layout	1993	DBLP DOI BibTeX RDF
40	Toshihiko Takahashi, Yoji Kajitani	The Virtual Dimensions of a Straight Line Embedding of a plane Graph.	Algorithmic Aspects of VLSI Layout	1993	DBLP DOI BibTeX RDF
40	D. Zhou, Franco P. Preparata	On the Manhattan and knock-knee Routing Models.	Algorithmic Aspects of VLSI Layout	1993	DBLP DOI BibTeX RDF
40	Prithviraj Banerjee	A Survey of Parallel Algorithms for VLSI cell Placement.	Algorithmic Aspects of VLSI Layout	1993	DBLP DOI BibTeX RDF
40	Shuji Tsukiyama, Keiichi Koike, Isao Shirakawa	An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI floorplan.	Algorithmic Aspects of VLSI Layout	1993	DBLP DOI BibTeX RDF
40	Tetsuo Asano, Takeshi Tokuyama	Circuit Partitioning Algorithms based on Geometry Model.	Algorithmic Aspects of VLSI Layout	1993	DBLP DOI BibTeX RDF
40	Martin L. Brady, Donna J. Brown, Patrick J. McGuiness	The three-dimensional channel Routing Problem.	Algorithmic Aspects of VLSI Layout	1993	DBLP DOI BibTeX RDF
40	Teofilo F. Gonzalez, Shashishekhar Kurki-Gowdara, Si-Qing Zheng	Switch-Box Routing under the two-Overlap wiring Model.	Algorithmic Aspects of VLSI Layout	1993	DBLP DOI BibTeX RDF
40	Chuan-Jin Shi	Constrained via Minimization and Signed Hypergraph Partitioning.	Algorithmic Aspects of VLSI Layout	1993	DBLP DOI BibTeX RDF
40	Thomas Lengauer, Martin Lügering	Integer Program formulations of Global Routing and Placement Problems.	Algorithmic Aspects of VLSI Layout	1993	DBLP DOI BibTeX RDF
40	Ting-Chi Wang, D. F. Wong 0001	A note on the Complexity of Stockmeyer's floorplan Optimization Technique.	Algorithmic Aspects of VLSI Layout	1993	DBLP DOI BibTeX RDF
40	Fillia Makedon, Spyros Tragoudas	Approximate solutions for Graph and Hypergraph Partitioning.	Algorithmic Aspects of VLSI Layout	1993	DBLP DOI BibTeX RDF
40	Nathan Hurst, Kim Marriott, Peter Moulder	Toward tighter tables.	ACM Symposium on Document Engineering	2005	DBLP DOI BibTeX RDF	table layout, optimisation techniques, conic programming
39	Andrew Lim 0001, Sartaj K. Sahni, Venkat Thanvantri	A fast algorithm to test planar topological routability.	VLSI Design	1995	DBLP DOI BibTeX RDF	planar topological routability testing, pin nets, single layer routing, IC layout design, VLSI, network topology, network routing, circuit layout CAD, fast algorithm, VLSI layout, integrated circuit layout, linear time algorithm
39	Roy Hartono, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi	Automatic Device Layout Generation for Analog Layout Retargeting.	VLSI Design	2005	DBLP DOI BibTeX RDF
39	J. Apte, Gershon Kedem	Strip Layout: A New Layout Methodology for Standard Circuit Modules.	DAC	1987	DBLP DOI BibTeX RDF
39	Vivek Joshi, Valeriy Sukharev, Andres Torres, Kanak Agarwal, Dennis Sylvester, David T. Blaauw	Closed-form modeling of layout-dependent mechanical stress.	DAC	2010	DBLP DOI BibTeX RDF	mechanical stress, modeling, mobility
39	Ming-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang	An MILP-based wire spreading algorithm for PSM-aware layout modification.	ASP-DAC	2008	DBLP DOI BibTeX RDF
39	Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi	Hierarchical extraction and verification of symmetry constraints for analog layout automation.	ASP-DAC	2004	DBLP DOI BibTeX RDF
39	Shuo Zhang, Wayne Wei-Ming Dai	TEG: a new post-layout optimization method.	ISPD	2002	DBLP DOI BibTeX RDF
39	Bernd Meyer 0001	Self-Organizing Graphs - A Neural Network Perspective of Graph Layout.	GD	1998	DBLP DOI BibTeX RDF