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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6705 occurrences of 3042 keywords
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Results
Found 11076 publication records. Showing 11076 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
94 | Louis Monier, Ramsey W. Haddad, Jeremy Dion |
Recursive layout generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 172-184, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
BiCMOS digital integrated circuits, recursive layout generation, layout directives, netlist description, hand-drawn layout, synthesized layout, overall layout, dense VLSI, VLSI, logic CAD, circuit layout CAD, microprocessor chips, microprocessor chips, VLSI chips, seamless integration |
82 | Ken Kennedy, Ulrich Kremer |
Automatic Data Layout for Distributed-Memory Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 20(4), pp. 869-916, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
high performance Fortran |
81 | Neff Walker, John B. Smelcer |
A comparison of selection time from walking and pull-down menus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHI ![In: Conference on Human Factors in Computing Systems, CHI 1990, Seattle, WA, USA, April 1-5, 1990, Proceedings, pp. 221-226, 1990, ACM, 0-201-50932-6. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
81 | Terry Winograd |
What can we teach about human-computer interaction? (plenary address). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHI ![In: Conference on Human Factors in Computing Systems, CHI 1990, Seattle, WA, USA, April 1-5, 1990, Proceedings, pp. 443-448, 1990, ACM, 0-201-50932-6. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
81 | Hans Brunner |
A snapshot of natural language interfaces (panel). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHI ![In: Conference on Human Factors in Computing Systems, CHI 1990, Seattle, WA, USA, April 1-5, 1990, Proceedings, pp. 53-55, 1990, ACM, 0-201-50932-6. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
81 | Jakob Nielsen |
Designing for international use (panel). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHI ![In: Conference on Human Factors in Computing Systems, CHI 1990, Seattle, WA, USA, April 1-5, 1990, Proceedings, pp. 291-294, 1990, ACM, 0-201-50932-6. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
81 | S. Joy Mountford |
Designers: meet your users (panel). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHI ![In: Conference on Human Factors in Computing Systems, CHI 1990, Seattle, WA, USA, April 1-5, 1990, Proceedings, pp. 439-442, 1990, ACM, 0-201-50932-6. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
Apple Computer, HyperCard, Inc |
81 | Marcy Telles |
Updating an older interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHI ![In: Conference on Human Factors in Computing Systems, CHI 1990, Seattle, WA, USA, April 1-5, 1990, Proceedings, pp. 243-248, 1990, ACM, 0-201-50932-6. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
WordStar |
74 | Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri |
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 271-276, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
MSL, pre-layout extraction, parasitics, analog VLSI |
74 | Andrew Sears |
Layout Appropriateness: A Metric for Evaluating User Interface Widget Layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 19(7), pp. 707-719, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
layout appropriateness, user interface widget layout, simple task descriptions, Layout Appropriateness, simplified task analysis, LA-optimal layout, performance evaluation, user interfaces, human factors, software metrics, weighting |
70 | Neungsoo Park, Bo Hong, Viktor K. Prasanna |
Tiling, Block Data Layout, and Memory Hierarchy Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 14(7), pp. 640-654, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Block data layout, TLB misses, memory hierarchy, tiling, cache misses |
70 | Peter Lüders, Rolf Ernst |
Research report: improving browsing in information by the automatic display layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INFOVIS ![In: IEEE Symposium On Information Visualization 1995, InfoVis 1995, 30-31 October 1995, Atlanta, Georgia, USA, pp. 26-33, 1995, IEEE Computer Society, 0-8186-7201-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
automatic display layout, graph structured information, automatic layout system, time consuming, manual layout, user requests, display layouts, information retrieval, graphical user interfaces, user modelling, user model, human factors, computer animation, information network, graphical representations, information browsing, layout algorithms |
70 | Sanjay Rekhi, J. Donald Trotter |
HAL: heuristic algorithms for layout synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 185-199, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
layout synthesis, graph theory based algorithms, leaf cells, common poly gates, 1-1/2-d layout style, common circuit nodes, transistor sets, symbolic layouts, static dual type, static CMOS circuitry, pullup network, pulldown network, dynamic logic styles, graph theory, network topology, logic CAD, heuristic algorithms, circuit layout CAD, CMOS logic circuits, CMOS circuits, GENIE, run time efficient, layout area |
67 | Akira Matsubayashi |
VLSI layout of trees into grids of minimum width. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2003: Proceedings of the Fifteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, June 7-9, 2003, San Diego, California, USA (part of FCRC 2003), pp. 75-84, 2003, ACM, 1-58113-661-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
cutwidth, grid, tree, graph embedding, VLSI layout, graph layout, aspect ratio |
64 | Hart Anway, Greg Farnham, Rebecca Reid |
PLINT layout system for VLSI chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 449-452, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
IC placement, IC routing, macrocell layout, standard cell layout, VLSI, computer-aided design, IC layout |
62 | Syed M. Alam, Donald E. Troxel, Carl V. Thompson |
A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 246-251, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
3D integrated circuit, 3D IC layout, inter-wafer via, reliability CAD tool, FPGA, performance analysis, reliability analysis |
60 | Shuo Zhang, Wayne Wei-Ming Dai |
TEG: a new post-layout optimization method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4), pp. 446-456, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
59 | Toyohide Watanabe, Qin Luo, Noboru Sugie |
Layout Recognition of Multi-Kinds of Table-Form Documents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 17(4), pp. 432-445, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Recognition paradigm for multi-kinds of table-form documents, automatic acquisition of layout knowledge, recognition of document classes, recognition of layout structures, structure description tree, classification tree |
57 | Oguzhan Ozmen, Kenneth Salem, Jiri Schindler, Steve Daniel |
Workload-aware storage layout for database systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Conference ![In: Proceedings of the ACM SIGMOD International Conference on Management of Data, SIGMOD 2010, Indianapolis, Indiana, USA, June 6-10, 2010, pp. 939-950, 2010, ACM, 978-1-4503-0032-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
layout, physical design, storage systems |
56 | Tim Dwyer, Kim Marriott, Falk Schreiber, Peter J. Stuckey, Michael Woodward, Michael Wybrow |
Exploration of Networks using overview+detail with Constraint-based cooperative layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Vis. Comput. Graph. ![In: IEEE Trans. Vis. Comput. Graph. 14(6), pp. 1293-1300, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
55 | Frederik Beeftink, Arjan J. van Genderen, N. P. van der Meijs |
Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 360-365, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
MOS integrated circuits, bipolar integrated circuits, BiCMOS integrated circuits, layout-to-circuit extraction, high-speed MOS integrated circuits, bipolar/BiCMOS integrated circuits, device recognition, equivalent network, layout parasitics, interconnects, circuit analysis computing, circuit layout CAD, Space, Spice, device modeling |
54 | Tiziana Calamoneri, Annalisa Massini |
Nearly Optimal Three Dimensional Layout of Hypercube Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GD ![In: Graph Drawing, 11th International Symposium, GD 2003, Perugia, Italy, September 21-24, 2003, Revised Papers, pp. 247-258, 2003, Springer, 3-540-20831-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Three Dimensional Layout, VLSI layout volume, Hypercube Network |
54 | Mohamed Dessouky, Marie-Minerve Louërat |
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 291-298, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Analog layout, layout generation |
54 | Joni Dambre, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout |
On rent's rule for rectangular regions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 49-56, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
layout Rent parameters, rectangular layout region, wirelength distribution, Rent's rule |
52 | Masahiro Nagamatu, Shakeel Ismail, Torao Yanaru |
Lagrangian method for wire routing of layout design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANNES ![In: 2nd New Zealand Two-Stream International Conference on Artificial Neural Networks and Expert Systems (ANNES '95), November 20-23, 1995, Dunedin, New Zealand, pp. 350-354, 1995, IEEE Computer Society, 0-8186-7174-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
wire routing, layout design, LSI layout design, continuous valued constrained optimization problem, continuous valued wires, dynamic equations, small switchbox routing problems, rip-up reroute maze router, neural nets, network routing, circuit layout CAD, circuit optimisation, integrated circuit layout, large scale integration, neurocomputing, Lagrangian method |
52 | Chengliang Zhang, Martin Hirzel |
Online Phase-Adaptive Data Layout Selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECOOP ![In: ECOOP 2008 - Object-Oriented Programming, 22nd European Conference, Paphos, Cyprus, July 7-11, 2008, Proceedings, pp. 309-334, 2008, Springer, 978-3-540-70591-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
52 | Takayoshi Noguchi, Jiro Tanaka |
Interactive Layout Method for Object Diagrams of OMT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APSEC ![In: 6th Asia-Pacific Software Engineering Conference (APSEC '99), 7-10 December 1999, Takamatsu, Japan, pp. 110-117, 1999, IEEE Computer Society, 0-7695-0509-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
software development tool, object-oriented methodology |
51 | Jin-Tai Yan |
A simple yet effective genetic approach for the orientation assignment on cell-based layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 33-36, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
genetic approach, orientation assignment, cell-based layout, total wire length minimisation, placement phase, routing area reduction, orientation states, vertical orientation bit, horizontal orientation bit, genetic algorithms, VLSI, VLSI design, network routing, circuit layout CAD, integrated circuit layout |
51 | Winfried Graf, Stefan Neurohr |
Constraint-Based Layout in Visual Program Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VL ![In: Proceedings 11th International IEEE Symposium on Visual Languages, Darmstadt, Germany, September 5-9, 1995, pp. 116-117, 1995, IEEE Computer Society, 0-8186-7045-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
visual program design, constraint-based layout, visual program layout, graphical editing tasks, InLay constraint-based graphical editor, animated chart diagram layout, presentation part abstraction, active display object focussing, graphical history editing, hierarchical information structure visualisation, multimedia, data structures, knowledge based systems, interaction techniques, programming environments, visual programming, computer animation, intelligent system, data visualisation, multimedia computing, program visualization, constraint handling, visual programming environments, dynamic displays, communication media |
51 | Nikolaos G. Bourbakis, Mohammad Mortazavi |
An efficient building block layout methodology for compact placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 118-123, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
building block layout methodology, compact placement, synthesis placement, GEOMETRIA, geometric reshapings, VLSI regulation, functional performance, connection lines, occupied chip area, neighboring relations, dead space, open holes, channels merging process, legal overlapping, VLSI, formal languages, formal language, network routing, circuit layout CAD, compaction, global routing, integrated circuit layout, integrated circuit interconnections, local routing |
50 | Tim Dwyer, Kim Marriott, Michael Wybrow |
Integrating Edge Routing into Force-Directed Layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GD ![In: Graph Drawing, 14th International Symposium, GD 2006, Karlsruhe, Germany, September 18-20, 2006. Revised Papers, pp. 8-19, 2006, Springer, 978-3-540-70903-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
constrained optimisation, edge routing, graph layout, force-directed layout |
50 | Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi |
Correct-by-construction layout-centric retargeting of large analog designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 139-144, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
analog integrated circuit design, analog layout automation, analog synthesis and optimization, layout symmetry |
50 | Hyunmo Kang, Ben Shneiderman, Gregory J. Wolff |
Dynamic Layout Management in a Multimedia Bulletin Board. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HCC ![In: 2002 IEEE CS International Symposium on Human-Centric Computing Languages and Environments (HCC 2002), 3-6 September 2002, Arlington, VA, USA, pp. 51-53, 2002, IEEE Computer Society, 0-7695-1644-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Multimedia Bulletin Board (MBB), layout management, dynamic layout template (DLT), collaboration, asynchronous communication |
50 | Toshiyuki Masui |
Evolutionary Learning of Graph Layout Constraints from Examples. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Symposium on User Interface Software and Technology ![In: Proceedings of the 7th Annual ACM Symposium on User Interface Software and Technology, UIST 1994, Marina del Rey, CA, USA, November 2-4, 1994, pp. 103-108, 1994, ACM, 0-89791-657-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
graphic object layout, genetic algorithms, genetic programming, adaptive user interface, programming by example, graph layout, TeX |
49 | Edmund K. Burke, Karen M. Daniels, Graham Kendall |
07112 Abstracts Collection - Cutting, Packing, Layout and Space Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Cutting, Packing, Layout and Space Allocation ![In: Cutting, Packing, Layout and Space Allocation, 13.03. - 16.03.2007, 2007, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
49 | Edmund K. Burke, Karen M. Daniels, Graham Kendall |
07112 Summary - Cutting, Packing, Layout and Space Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Cutting, Packing, Layout and Space Allocation ![In: Cutting, Packing, Layout and Space Allocation, 13.03. - 16.03.2007, 2007, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
49 | Malgorzata Marek-Sadowska |
Issues in Timing Driven Layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmic Aspects of VLSI Layout ![In: Algorithmic Aspects of VLSI Layout, pp. 1-24, 1993, World Scientific, 978-981-02-1488-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
49 | Teofilo F. Gonzalez, Sing-Ling Lee |
Routing around two Rectangles to minimize the Layout Area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmic Aspects of VLSI Layout ![In: Algorithmic Aspects of VLSI Layout, pp. 365-397, 1993, World Scientific, 978-981-02-1488-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
49 | Christof Lutteroth, Gerald Weber |
Modular Specification of GUI Layout Using Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Australian Software Engineering Conference ![In: 19th Australian Software Engineering Conference (ASWEC 2008), March 25-28, 2008, Perth, Australia, pp. 300-309, 2008, IEEE Computer Society, 978-0-7695-3100-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
user interfaces, constraints, modularity, layout |
49 | Ian Kuon, Aaron Egier, Jonathan Rose |
Design, layout and verification of an FPGA using automated tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 215-226, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
FPGA, programmable logic, PLD, automatic layout |
49 | Zhan Chen, Fook-Luen Heng |
A Fast Minimum Layout Perturbation Algorithm for Electromigration Reliability Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 56-63, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
layout compaction, design for reliability, electromigration |
47 | Akif Sultan, John Faricelli, Sushant Suryagandh, Hans vanMeer, Kaveri Mathur, James Pattison, Sean Hannon, Greg Constant, Kalyana Kumar, Kevin Carrejo, Joe Meier, Rasit Onur Topaloglu, Darin Chan, Uwe Hahn, Thorsten Knopp, Victor Andrade, Bill Gardiol, Steve Hejl, David Wu, James Buller, Larry Bair, Ali Icel, Yuri Apanovich |
CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 442-446, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
47 | Hiroaki Yoshida, Kaushik De, Vamsi Boppana |
Accurate pre-layout estimation of standard cell characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 208-211, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
cell characterization, transistor-level optimization, standard cell |
47 | Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky |
Filling algorithms and analyses for layout density control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4), pp. 445-462, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
47 | Kazuo Sugihara, Kazunari Yamamoto, Isao Miyamoto |
Automatic Layout of Diagrams for Software Specification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEKE ![In: SEKE'92, The 4th International Conference on Software Engineering and Knowledge Engineering, June, 15-20 1992, Capri, Italy, pp. 245-252, 1992, IEEE Computer Society, 0-8186-2830-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
47 | David Eppstein, Elena Mumford, Bettina Speckmann, Kevin Verbeek |
Area-universal rectangular layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCG ![In: Proceedings of the 25th ACM Symposium on Computational Geometry, Aarhus, Denmark, June 8-10, 2009, pp. 267-276, 2009, ACM, 978-1-60558-501-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
rectangular layouts |
47 | Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi |
Multilevel symmetry-constraint generation for retargeting large analog layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6), pp. 945-960, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Floriana Esposito, Donato Malerba, Giovanni Semeraro |
A knowledge-based approach to the layout analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDAR ![In: Third International Conference on Document Analysis and Recognition, ICDAR 1995, August 14 - 15, 1995, Montreal, Canada. Volume I, pp. 466-471, 1995, IEEE Computer Society, 0-8186-7128-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
top-down technique, typesetting conventions, generic knowledge, processed documents, Layout EXpert, knowledge based systems, document image processing, document image, layout analysis, knowledge-based approach, LEX |
44 | Christof Lutteroth, Robert Strandh, Gerald Weber |
Domain Specific High-Level Constraints for User Interface Layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Constraints An Int. J. ![In: Constraints An Int. J. 13(3), pp. 307-342, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Auckland Layout Model, Constraint, GUI |
44 | Sambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy |
On Efficient and Robust Constraint Generation for Practical Layout Legalization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 379-384, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Layout legalization, constraint reduction, compaction, constraint generation |
44 | Payman Zarkesh-Ha, Ken Doniger |
Stochastic interconnect layout sensitivity model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 9-14, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
critical area analysis, layout sensitivity, reliability, stochastic model, yield, design for manufacturability, defect density |
44 | Yuying Wang, Xingshe Zhou 0001 |
Mutual Effect of Instruction Layout Optimization and Instruction Memory Hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: 2007 International Conference on Parallel Processing Workshops (ICPP Workshops 2007), 10-14 September 2007, Xi-An, China, pp. 22, 2007, IEEE Computer Society, 978-0-7695-2934-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Instruction Layout Optimization, Instruction Cache Miss Rate, Cache Memory Hierarchy |
44 | Tim Dwyer, Yehuda Koren, Kim Marriott |
IPSep-CoLa: An Incremental Procedure for Separation Constraint Layout of Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Vis. Comput. Graph. ![In: IEEE Trans. Vis. Comput. Graph. 12(5), pp. 821-828, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
stress majorization, force directed algorithms, constraints, layout, Graph drawing, multidimensional scaling |
44 | Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose |
Automatic transistor and physical design of FPGA tiles from an architectural specification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 164-172, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
FPGA, programmable logic, PLD, automatic layout |
44 | Carlton Bickford, Marie S. Teo, Gary Wallace, John A. Stankovic, Krithi Ramamritham |
A robotic assembly application on the Spring real-time system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real Time Technology and Applications Symposium ![In: 2nd IEEE Real-Time Technology and Applications Symposium, RTAS '96, Boston, MA, USA, June 10-12, 1996, pp. 19-28, 1996, IEEE Computer Society, 0-8186-7448-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
printed circuit manufacture, printed circuit layout, robotic assembly application, Spring real-time system, run-time system support, predictability demands, robotic work-cell, circuit board assembly, user understanding, target hardware properties, process layout, resource layout, shared resource usage, process suspension, efficient run-time representation, real-time systems, robots, timing, completeness, flexibility, reengineering, timing analysis, circuit layout CAD, assembling, systems re-engineering, interprocess communication, program representation, porting, ease of use, industrial robots, software development tools |
44 | Sandip Das 0001, Bhargab B. Bhattacharya |
Channel routing in Manhattan-diagonal model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 43-48, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Manhattan-diagonal model, layout grid, cyclic vertical constraints, low via count, reduced wire length, VLSI, network routing, circuit layout CAD, VLSI layout, integrated circuit layout, channel routing, output-sensitive algorithm |
44 | Saibal Das, Sanjeev Saxena |
Parallel algorithms for single row routing in narrow streets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 13-18, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
narrow streets, optimal layout, parallel algorithms, parallel algorithms, VLSI, network routing, circuit layout CAD, VLSI layout, integrated circuit layout, single row routing, IC design, CREW PRAM, tree machine |
43 | Yuji Shigehiro, Takashi Nagata, Isao Shirakawa, Itthichai Arungsrisangchai, Hiromitsu Takahashi |
Automatic layout recycling based on layout description and linear programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(8), pp. 959-967, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
43 | Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala |
Efficient Analog/RF Layout Closure with Compaction Based Legalization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 137-142, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
43 | Tim Dwyer, Kim Marriott, Michael Wybrow |
Topology Preserving Constrained Graph Layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GD ![In: Graph Drawing, 16th International Symposium, GD 2008, Heraklion, Crete, Greece, September 21-24, 2008. Revised Papers, pp. 230-241, 2008, Springer, 978-3-642-00218-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Xiaofan Lin |
Active Document Layout Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDAR ![In: Eighth International Conference on Document Analysis and Recognition (ICDAR 2005), 29 August - 1 September 2005, Seoul, Korea, pp. 86-90, 2005, IEEE Computer Society, 0-7695-2420-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Ismail Kadayif, Mahmut T. Kandemir |
Quasidynamic Layout Optimizations for Improving Data Locality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 15(11), pp. 996-1011, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
array-intensive computations, dynamic optimization, Optimizing compilers, data locality |
43 | Pierluigi Daglio, David Iezzi, Danilo Rimondi, Carlo Roma, Salvatore Santapa |
Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 336-337, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
43 | Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, C.-J. Richard Shi |
CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 163-168, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
43 | Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng |
Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 168-178, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
43 | Sanjay Khanna, Shaodi Gao, Krishnaiyan Thulasiraman |
Parallel hierarchical global routing for general cell layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 212-, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
parallel hierarchical global routing, general cell layout, hierarchical decomposition strategy, network flow optimization, parallel algorithms, parallel processing, VLSI, integer programming, integer programming, routing algorithm, network routing, circuit layout CAD, integrated circuit layout, shared-memory machine |
42 | Manjit Borah, Robert Michael Owens, Mary Jane Irwin |
Fast algorithm for performance-oriented Steiner routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 198-203, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
performance-oriented Steiner routing, fast routing algorithm, Elmore delay minimisation, layout generators, computational complexity, VLSI, data structures, data structures, delays, iterative methods, network routing, circuit layout CAD, integrated circuit layout, iterative techniques |
41 | Saeedeh Bakhshi, Hamid Sarbazi-Azad |
Efficient VLSI Layout of Edge Product Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 555-560, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Edge graph product, Collinear layout, Interconnection networks, Networks on chip, VLSI layout |
41 | Derek Hoiem, Alexei A. Efros, Martial Hebert |
Recovering Surface Layout from an Image. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Comput. Vis. ![In: Int. J. Comput. Vis. 75(1), pp. 151-172, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
surface layout, spatial layout, geometric context, model-driven segmentation, multiple segmentations, context, object recognition, object detection, image understanding, scene understanding |
41 | Ben L. Titzer, Jens Palsberg |
Vertical object layout and compression for fixed heaps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 170-178, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
heap optimization, object layout, pointer compression, program data compression, reference compression, vertical object layout, microcontrollers |
41 | Yasuto Ishitani |
Document Layout Analysis Based on Emergent Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDAR ![In: 4th International Conference Document Analysis and Recognition (ICDAR '97), 2-Volume Set, August 18-20, 1997, Ulm, Germany, Proceedings, pp. 45-50, 1997, IEEE Computer Society, 0-8186-7898-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Structural Layout Analysis, Bottom Up Strategy, Document Image Analysis, Document Layout Analysis |
41 | Anikó Simon, Jean-Christophe Pret, A. Peter Johnson |
(Chem)DeTE/X automatic generation of a markup language description of (chemical) documents from bitmap images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDAR ![In: Third International Conference on Document Analysis and Recognition, ICDAR 1995, August 14 - 15, 1995, Montreal, Canada. Volume I, pp. 458-461, 1995, IEEE Computer Society, 0-8186-7128-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
markup language description, bitmap images, style file, layout recognition, Kruskal's algorithm, physical page structure, chemical documents, recursive parsing algorithm, document style description language, DSDL, document processing, layout analysis, document handling, scientific publications, page description languages |
40 | Joseph H. Goldberg, Jonathan I. Helfman, Lynne Martin |
Information distance and orientation in liquid layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHI ![In: Proceedings of the 2008 Conference on Human Factors in Computing Systems, CHI 2008, 2008, Florence, Italy, April 5-10, 2008, pp. 1153-1156, 2008, ACM, 978-1-60558-011-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
browser width, liquid layout, widescreen design, usability evaluation |
40 | Huijun Zhu, Peng Gu, Jun Wang 0001 |
Shifted declustering: a placement-ideal layout scheme for multi-way replication storage architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 22nd Annual International Conference on Supercomputing, ICS 2008, Island of Kos, Greece, June 7-12, 2008, pp. 134-144, 2008, ACM, 978-1-60558-158-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
multi-way replication, optimal parallelism, data layout |
40 | Christof Lutteroth, Gerald Weber |
User interface layout with ordinal and linear constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AUIC ![In: User Interfaces 2006, 7th Australasian User Interface Conference (AUIC 2006), Hobart, Tasmania, Australia, January 16-19 2005, pp. 53-60, 2006, Australian Computer Society, 1-920682-32-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
2D layout, formal constraints, user interface design, tables |
40 | Simon Lok, Steven Feiner, Gary Ngai |
Evaluation of visual balance for automated layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IUI ![In: Proceedings of the 9th International Conference on Intelligent User Interfaces, IUI 2004, Funchal, Madeira, Portugal, January 13-16, 2004, pp. 101-108, 2004, ACM, 1-58113-815-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
automated layout, visual balance |
40 | Seong-Whan Lee, Dae-Seok Ryu |
Parameter-Free Geometric Document Layout Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 23(11), pp. 1240-1256, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Geometric document layout analysis, parameter-free method, periodicity estimation, page segmentation, multiscale analysis |
40 | Chau-Shen Chen, TingTing Hwang |
Layout Driven Selection and Chaining of Partial Scan Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 13(1), pp. 19-27, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
design for testability, matching, placement, global routing, partial scan, digital testing, layout optimization |
40 | Edmund K. Burke, Karen M. Daniels, Graham Kendall (eds.) |
Cutting, Packing, Layout and Space Allocation, 13.03. - 16.03.2007 ![Search on Bibsonomy](Pics/bibsonomy.png) |
Cutting, Packing, Layout and Space Allocation ![Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
40 | S. M. Kang, M. Sriram |
Binary formulations for Placement and Routing Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmic Aspects of VLSI Layout ![In: Algorithmic Aspects of VLSI Layout, pp. 25-68, 1993, World Scientific, 978-981-02-1488-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
40 | Toshihiko Takahashi, Yoji Kajitani |
The Virtual Dimensions of a Straight Line Embedding of a plane Graph. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmic Aspects of VLSI Layout ![In: Algorithmic Aspects of VLSI Layout, pp. 357-363, 1993, World Scientific, 978-981-02-1488-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
40 | D. Zhou, Franco P. Preparata |
On the Manhattan and knock-knee Routing Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmic Aspects of VLSI Layout ![In: Algorithmic Aspects of VLSI Layout, pp. 245-264, 1993, World Scientific, 978-981-02-1488-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
40 | Prithviraj Banerjee |
A Survey of Parallel Algorithms for VLSI cell Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmic Aspects of VLSI Layout ![In: Algorithmic Aspects of VLSI Layout, pp. 69-131, 1993, World Scientific, 978-981-02-1488-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
40 | Shuji Tsukiyama, Keiichi Koike, Isao Shirakawa |
An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI floorplan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmic Aspects of VLSI Layout ![In: Algorithmic Aspects of VLSI Layout, pp. 321-335, 1993, World Scientific, 978-981-02-1488-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
40 | Tetsuo Asano, Takeshi Tokuyama |
Circuit Partitioning Algorithms based on Geometry Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmic Aspects of VLSI Layout ![In: Algorithmic Aspects of VLSI Layout, pp. 199-212, 1993, World Scientific, 978-981-02-1488-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
40 | Martin L. Brady, Donna J. Brown, Patrick J. McGuiness |
The three-dimensional channel Routing Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmic Aspects of VLSI Layout ![In: Algorithmic Aspects of VLSI Layout, pp. 213-244, 1993, World Scientific, 978-981-02-1488-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
40 | Teofilo F. Gonzalez, Shashishekhar Kurki-Gowdara, Si-Qing Zheng |
Switch-Box Routing under the two-Overlap wiring Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmic Aspects of VLSI Layout ![In: Algorithmic Aspects of VLSI Layout, pp. 265-308, 1993, World Scientific, 978-981-02-1488-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
40 | Chuan-Jin Shi |
Constrained via Minimization and Signed Hypergraph Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmic Aspects of VLSI Layout ![In: Algorithmic Aspects of VLSI Layout, pp. 337-356, 1993, World Scientific, 978-981-02-1488-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
40 | Thomas Lengauer, Martin Lügering |
Integer Program formulations of Global Routing and Placement Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmic Aspects of VLSI Layout ![In: Algorithmic Aspects of VLSI Layout, pp. 167-197, 1993, World Scientific, 978-981-02-1488-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
40 | Ting-Chi Wang, D. F. Wong 0001 |
A note on the Complexity of Stockmeyer's floorplan Optimization Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmic Aspects of VLSI Layout ![In: Algorithmic Aspects of VLSI Layout, pp. 309-320, 1993, World Scientific, 978-981-02-1488-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
40 | Fillia Makedon, Spyros Tragoudas |
Approximate solutions for Graph and Hypergraph Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmic Aspects of VLSI Layout ![In: Algorithmic Aspects of VLSI Layout, pp. 133-166, 1993, World Scientific, 978-981-02-1488-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
40 | Nathan Hurst, Kim Marriott, Peter Moulder |
Toward tighter tables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Symposium on Document Engineering ![In: Proceedings of the 2005 ACM Symposium on Document Engineering, Bristol, UK, November 2-4, 2005, pp. 74-83, 2005, ACM, 1-59593-240-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
table layout, optimisation techniques, conic programming |
39 | Andrew Lim 0001, Sartaj K. Sahni, Venkat Thanvantri |
A fast algorithm to test planar topological routability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 8-12, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
planar topological routability testing, pin nets, single layer routing, IC layout design, VLSI, network topology, network routing, circuit layout CAD, fast algorithm, VLSI layout, integrated circuit layout, linear time algorithm |
39 | Roy Hartono, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi |
Automatic Device Layout Generation for Analog Layout Retargeting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 457-462, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
39 | J. Apte, Gershon Kedem |
Strip Layout: A New Layout Methodology for Standard Circuit Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 363-369, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
39 | Vivek Joshi, Valeriy Sukharev, Andres Torres, Kanak Agarwal, Dennis Sylvester, David T. Blaauw |
Closed-form modeling of layout-dependent mechanical stress. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 673-678, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
mechanical stress, modeling, mobility |
39 | Ming-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang |
An MILP-based wire spreading algorithm for PSM-aware layout modification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 364-369, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi |
Hierarchical extraction and verification of symmetry constraints for analog layout automation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 400-405, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
39 | Shuo Zhang, Wayne Wei-Ming Dai |
TEG: a new post-layout optimization method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 62-67, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
39 | Bernd Meyer 0001 |
Self-Organizing Graphs - A Neural Network Perspective of Graph Layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GD ![In: Graph Drawing, 6th International Symposium, GD'98, Montréal, Canada, August 1998, Proceedings, pp. 246-262, 1998, Springer, 3-540-65473-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
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