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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6589 occurrences of 2604 keywords
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Results
Found 18593 publication records. Showing 18593 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
68 | Zhuo Gao, Ji Luo 0003, Hu Huang 0001, Wei Zhang, Joseph B. Bernstein |
Reliable Laser Programmable Gate Array Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 252-256, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Laser Programmable Gate Array (LPGA), Laser Field-Programmable Gate Array (LFPGA), MakeLink technology, laser-induced/laser programmable anti-fuse, digital ASIC design, low electrical resistance anti-fuse, Field-Programmable Gate Array (FPGA) |
56 | André DeHon |
Design of programmable interconnect for sublithographic programmable logic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 127-137, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Manhattan mesh, sublithographic architecture, programmable logic arrays, nanowires, programmable interconnect |
53 | Bradly K. Fawcett, J. Watson |
Reconfigurable Processing With Field Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 293-302, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
reconfigurable processing, internal architecture, computationally-intensive tasks, programmable solution, XC6200 FPGA architecture, SRAM control store, on-chip memory capability, field programmable gate arrays, interconnections, reconfigurable architectures, processors, coprocessors, coprocessors, SRAM chips, SRAM-based field programmable gate arrays |
50 | Noha Kafafi, Kimberly A. Bozman, Steven J. E. Wilton |
Architectures and algorithms for synthesizable embedded programmable logic cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 3-11, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
programmable logic cores, FPGA, standard cells, system-on-chip design |
49 | Stuart W. Daniel, Jennifer Rexford, James W. Dolter, Kang G. Shin |
A programmable routing controller for flexible communications in point-to-point networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 320-331, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
programmable routing controller, flexible communications, communication characteristics, custom ASIC, programmable processor, multiple routing-switching microcode routines, multiprocessor interconnection networks, packet switching, packet switching, application specific integrated circuits, wormhole switching, programmable controllers, firmware, performance requirements, virtual cut-through switching, point-to-point networks |
48 | Alban Verdenal, Didier Combes, Abraham Escobar-Gutiérrez |
Programmable and Self-Organised Processes in Plant Morphogenesis: The Architectural Development of Ryegrass. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Morphogenetic Engineering, Toward Programmable Complex Systems ![In: Morphogenetic Engineering, Toward Programmable Complex Systems, pp. 501-517, 2012, Springer, 978-3-642-33901-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
47 | Wei-Kang Huang, Fabrizio Lombardi |
An approach for testing programmable/configurable field programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 450-455, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
behavioral characterization, single fault detection, disjoint one-dimensional arrays, unilateral horizontal connections, common vertical input lines, array testing, logic blocks, field programmable gate arrays, field programmable gate arrays, VLSI, logic testing, integrated circuit testing, stuck-at fault, FPGA testing, functional fault, hybrid fault model |
46 | Narendra V. Shenoy, Jamil Kawa, Raul Camposano |
Design automation for mask programmable fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 192-197, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
mask programmable fabrics, integrated circuits |
45 | Uwe Meyer-Bäse, Antonio García 0001, Fred J. Taylor |
Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 28(1-2), pp. 115-128, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
field-programmable logic (FPL), complex programmable logic devices (CPLD), zero-IF filter, field programmable gate array (FPGA), digital signal processing (DSP), residue number system (RNS), channelizer |
44 | Jiri Stehlik, Daniel Becvar |
Field Programmable Mixed-Signal Arrays (FPMA) Using Versatile Current/Voltage Conveyor Structures. (PDF / PS) ![Search on Bibsonomy](Pics/bibsonomy.png) |
PWC ![In: Personal Wireless Communications, The 12th IFIP International Conference on Personal Wireless Communications (PWC 2007), Prague, Czech Republic, September 2007, pp. 628-636, 2007, Springer, 978-0-387-74158-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Field Programmable Mixed-Signals Array, Programmable Universal Current Conveyor, Field Programmable Analog Array |
44 | Bin Liu, Fabrizio Lombardi, Wei-Kang Huang |
Testing programmable interconnect systems: an algorithmic approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 311-316, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
programmable circuits, interconnected systems, programmable interconnect systems testing, algorithmic approach, programmable wiring networks, comprehensive fault model, network faults, open faults, switch faults, stuck-off faults, programming faults, minimal configuration number, node-disjoint path-sets, network adjacencies, post-processing algorithm, fault diagnosis, graphs, interconnections, fault detection, fault coverage, circuit analysis computing, stuck-at faults, switching, bridge faults, automatic test software, circuit testing, figure of merit, programming phases, stuck-on faults, short circuits |
44 | T. Utsumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato |
Multiple-Valued Programmable Logic Arrays with Universal Literals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 27th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1997, Antigonish, Nova Scotia, Canada, May 28-30, 1997, Proceedings, pp. 163-168, 1997, IEEE Computer Society, 0-8186-7910-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
universal literals, multiple-valued programmable logic, universal literal generators, operator structures, programmable logic arrays, programmable logic arrays |
43 | Ilija Hadzic, Jonathan M. Smith |
Balancing performance and flexibility with hardware support for network architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 21(4), pp. 375-411, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
P4, performance, FPGA, computer networking, hardware, flexibility, programmable networks, programmable logic devices, protocol processing |
43 | Amit Laknaur, Sai Raghuram Durbha, Haibo Wang 0005 |
Built-In-Self-Testing Techniques for Programmable Capacitor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(4-6), pp. 449-462, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
programmable capacitor array, built-in-self-testing, analog testing, field programmable analog array |
42 | Daniela Rus |
Programmable matter with self-reconfiguring robots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 51-52, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
programmable matter, robotics |
42 | Michael Conrad, Thomas Fuhrmann, Marcus Schöller, Martina Zitterbart |
Secure Service Signaling and Fast Authorization in Programmable Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWAN ![In: Active Networks, IFIP TC6 6th International Working Conference, IWAN 2004, Lawrence, KS, USA, October 27-29, 2004. Revised Papers, pp. 66-77, 2004, Springer, 978-3-540-71499-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Flexible Service Platforms, Secure Signaling, Programmable Networks |
41 | Yao-Wen Chang, D. F. Wong 0001, C. K. Wong |
Design and analysis of FPGA/FPIC switch modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 394-401, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
FPGA/FPIC switch modules, routing resources, FPIC, network-flow techniques, field programmable interconnect chip, field programmable gate arrays, FPGA, field programmable gate arrays, logic design, heuristic algorithm, programmable logic arrays, routability |
41 | André DeHon, Michael J. Wilson |
Nanowire-based sublithographic programmable logic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 123-132, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
sublithographic architecture, programmable logic arrays, nanowires |
41 | Peter Hallschmid, Steven J. E. Wilton |
Detailed routing architectures for embedded programmable logic IP cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 69-74, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
FPGA, programmable logic, detailed routing, SoC design, embedded cores |
40 | JoAnn M. Paul, Donald E. Thomas, Andrew S. Cassidy |
High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(3), pp. 431-461, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
schedulers, Computer-aided design, performance modeling, system modeling, heterogeneous multiprocessors |
40 | Kamran Zarrineh, Shambhu J. Upadhyaya |
On Programmable Memory Built-In Self Test Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 708-713, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
40 | Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici |
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!). ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 387-392, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
BIST architecture, programmable logic blocks, field programmable gate arrays, VLSI, logic testing, built-in self test, built-in self-test, integrated circuit testing, automatic testing, FPGA testing, field programmable gate array testing |
40 | Lizy Kurian John |
VaWiRAM: a variable width random access memory module. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 219-224, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
VaWiRAM, variable width random access memory, flexible memory systems, configuration pins, pass gates, reconfigurability, reconfigurable architectures, memory architecture, programmable logic, random-access storage, integrated circuit interconnections, programmable logic devices, programmable interconnect |
40 | Santonu Sarkar, Anupam Basu, Arun K. Majumdar |
Representation and Synthesis of Interface of a Circuit for its Reuse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 140-145, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
VaWiRAM, variable width random access memory, flexible memory systems, configuration pins, pass gates, reconfigurability, reconfigurable architectures, memory architecture, programmable logic, random-access storage, integrated circuit interconnections, programmable logic devices, programmable interconnect |
39 | Yaochu Jin, Yan Meng |
Morphogenetic Robotics: A New Paradigm for Designing Self-Organizing, Self-Reconfigurable and Self-Adaptive Robots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Morphogenetic Engineering, Toward Programmable Complex Systems ![In: Morphogenetic Engineering, Toward Programmable Complex Systems, pp. 61-87, 2012, Springer, 978-3-642-33901-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
39 | Daniel Lobo, Jose D. Fernández, Francisco J. Vico |
Behavior-Finding: Morphogenetic Designs Shaped by Function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Morphogenetic Engineering, Toward Programmable Complex Systems ![In: Morphogenetic Engineering, Toward Programmable Complex Systems, pp. 441-472, 2012, Springer, 978-3-642-33901-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
39 | Sylvain Cussat-Blanc, Jonathan Pascalie, Sébastien Mazac, Hervé Luga, Yves Duthen |
A Synthesis of the Cell2Organ Developmental Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Morphogenetic Engineering, Toward Programmable Complex Systems ![In: Morphogenetic Engineering, Toward Programmable Complex Systems, pp. 353-381, 2012, Springer, 978-3-642-33901-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
39 | Navneet Bhalla, Peter J. Bentley |
Programming Self-Assembling Systems via Physically Encoded Information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Morphogenetic Engineering, Toward Programmable Complex Systems ![In: Morphogenetic Engineering, Toward Programmable Complex Systems, pp. 157-188, 2012, Springer, 978-3-642-33901-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
39 | Wenguo Liu 0001, Alan F. T. Winfield |
Distributed Autonomous Morphogenesis in a Self-Assembling Robotic System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Morphogenetic Engineering, Toward Programmable Complex Systems ![In: Morphogenetic Engineering, Toward Programmable Complex Systems, pp. 89-113, 2012, Springer, 978-3-642-33901-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
39 | René Doursat, Carlos Sánchez, Razvan Dordea, David Fourquet, Taras Kowaliw |
Embryomorphic Engineering: Emergent Innovation Through Evolutionary Development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Morphogenetic Engineering, Toward Programmable Complex Systems ![In: Morphogenetic Engineering, Toward Programmable Complex Systems, pp. 275-311, 2012, Springer, 978-3-642-33901-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
39 | Sara Montagna, Mirko Viroli |
A Computational Framework for Multilevel Morphologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Morphogenetic Engineering, Toward Programmable Complex Systems ![In: Morphogenetic Engineering, Toward Programmable Complex Systems, pp. 383-405, 2012, Springer, 978-3-642-33901-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
39 | Rehan O'Grady, Anders Lyhne Christensen, Marco Dorigo |
SWARMORPH: Morphogenesis with Self-Assembling Robots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Morphogenetic Engineering, Toward Programmable Complex Systems ![In: Morphogenetic Engineering, Toward Programmable Complex Systems, pp. 27-60, 2012, Springer, 978-3-642-33901-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
39 | Sebastian von Mammen, David Phillips, Timothy Davison, Heather A. Jamniczky, Benedikt Hallgrímsson, Christian Jacob 0001 |
Swarm-Based Computational Development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Morphogenetic Engineering, Toward Programmable Complex Systems ![In: Morphogenetic Engineering, Toward Programmable Complex Systems, pp. 473-499, 2012, Springer, 978-3-642-33901-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
39 | Hiroki Sayama |
Swarm-Based Morphogenetic Artificial Life. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Morphogenetic Engineering, Toward Programmable Complex Systems ![In: Morphogenetic Engineering, Toward Programmable Complex Systems, pp. 191-208, 2012, Springer, 978-3-642-33901-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
39 | Daniel J. Arbuckle, Aristides A. G. Requicha |
Issues in Self-Repairing Robotic Self-Assembly. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Morphogenetic Engineering, Toward Programmable Complex Systems ![In: Morphogenetic Engineering, Toward Programmable Complex Systems, pp. 141-155, 2012, Springer, 978-3-642-33901-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
39 | Antoine Spicher, Olivier Michel 0001, Jean-Louis Giavitto |
Interaction-Based Modeling of Morphogenesis in MGS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Morphogenetic Engineering, Toward Programmable Complex Systems ![In: Morphogenetic Engineering, Toward Programmable Complex Systems, pp. 409-440, 2012, Springer, 978-3-642-33901-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
39 | Linge Bai, David E. Breen |
Chemotaxis-Inspired Cellular Primitives for Self-Organizing Shape Formation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Morphogenetic Engineering, Toward Programmable Complex Systems ![In: Morphogenetic Engineering, Toward Programmable Complex Systems, pp. 209-237, 2012, Springer, 978-3-642-33901-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
39 | René Doursat, Hiroki Sayama, Olivier Michel 0001 |
Morphogenetic Engineering: Reconciling Self-Organization and Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Morphogenetic Engineering, Toward Programmable Complex Systems ![In: Morphogenetic Engineering, Toward Programmable Complex Systems, pp. 1-24, 2012, Springer, 978-3-642-33901-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
39 | Alan F. T. Winfield, Julien Nembrini |
Emergent Swarm Morphology Control of Wireless Networked Mobile Robots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Morphogenetic Engineering, Toward Programmable Complex Systems ![In: Morphogenetic Engineering, Toward Programmable Complex Systems, pp. 239-271, 2012, Springer, 978-3-642-33901-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
39 | Taras Kowaliw, Wolfgang Banzhaf |
Mechanisms for Complex Systems Engineering Through Artificial Development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Morphogenetic Engineering, Toward Programmable Complex Systems ![In: Morphogenetic Engineering, Toward Programmable Complex Systems, pp. 331-351, 2012, Springer, 978-3-642-33901-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
39 | Jacob Beal |
Functional Blueprints: An Approach to Modularity in Grown Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Morphogenetic Engineering, Toward Programmable Complex Systems ![In: Morphogenetic Engineering, Toward Programmable Complex Systems, pp. 313-329, 2012, Springer, 978-3-642-33901-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
39 | Justin Werfel |
Collective Construction with Robot Swarms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Morphogenetic Engineering, Toward Programmable Complex Systems ![In: Morphogenetic Engineering, Toward Programmable Complex Systems, pp. 115-140, 2012, Springer, 978-3-642-33901-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
38 | André DeHon |
Nanowire-based programmable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 1(2), pp. 109-162, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Manhattan mesh, stochastic construction, sublithographic architecture, programmable logic arrays, Defect tolerance, nanowires, programmable interconnect |
38 | Vi Chi Chan, David Lewis |
Hierarchical partitioning for field-programmable systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 428-435, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
FPGA partitioning problems, circuit structures, field-programmable systems, partitioning tree, recursive bipartitioning algorithm, field programmable gate arrays, VLSI, quality, logic CAD, hierarchical partitioning |
38 | Wei-Kang Huang, Xiao-Tao Chen, Fabrizio Lombardi |
On the diagnosis of programmable interconnect systems: Theory and application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 204-211, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
field programmable interconnect system, switch grid, FPIS, Xilinx 3000, field programmable gate arrays, FPGA, fault diagnosis, logic testing, diagnosis, integrated circuit interconnections |
38 | Dinesh Bhatia, James Haralambides |
Resource requirements for field programmable interconnection chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 376-380, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
field programmable interconnection chips, n-permutation graph, network property, routing delays, programmable switches, routing paths, specific I/O permutations, user-configured interconnection, VLSI, VLSI, graph theory, network routing, permutation networks, integrated circuit interconnections, Benes network |
37 | Jason Helge Anderson |
Emerging application domains: research challenges and opportunities for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 1-2, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
performance, field-programmable gate array, fpga, applications, high-performance computing, power, reconfigurable computing |
37 | Nikolas Kroupis, Nikolaos D. Zervas, Minas Dasygenis, Konstantinos Tatas, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis |
Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 44(1-2), pp. 153-171, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Programmable platforms, estimation methodology, instruction complexity, memory transfers |
37 | Shree K. Nayar, Vlad Branzoi, Terrance E. Boult |
Programmable Imaging: Towards a Flexible Camera. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Comput. Vis. ![In: Int. J. Comput. Vis. 70(1), pp. 7-22, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
programmable imaging, flexible imaging, micro-mirror array, digital micro-mirror device, adaptive optics, optical processing, multi-viewpoint imaging, catadioptric imaging, wide-angle imaging, purposive camera, object recognition, stereo, resolution, MEMS, feature detection, high dynamic range imaging, field of view |
37 | Gonçalo Nuno Moutinho de Carvalho, Tony Gill, Tony Parisi |
X3D programmable shaders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Web3D ![In: Proceeding of the Ninth International Conference on 3D Web Technology, Web3D 2004, Monterey, California, USA, April 5-8, 2004, pp. 99-108, 2004, ACM, 1-58113-845-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
real-time shading, GPU, VRML, X3D, stream processors, programmable shading |
37 | Paul Willmann, Michael Brogioli, Vijay S. Pai |
Spinach: a liberty-based simulator for programmable network interface architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), Washington, DC, USA, June 11-13, 2004, pp. 20-29, 2004, ACM, 1-58113-806-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
programmable network interfaces, simulation, embedded systems |
37 | Luca Macchiarulo, Consolato F. Caccamo, Davide Pandini |
A comparison between mask- and field-programmable routing structures on industrial FPGA architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 436-439, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
mask-programmable, FPGA, routing, interconnect architectures |
37 | Nico Janssens, Lieven Desmet, Sam Michiels, Pierre Verbaeten |
NeCoMan: middleware for safe distributed service deployment in programmable networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Adaptive and Reflective Middleware ![In: Proceedings of the 3rd Workshop on Adaptive and Reflective Middleware, ARM 2003, Toronto, Ontario, Canada, October 19, 2004, pp. 256-261, 2004, ACM, 1-58113-949-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
network consistency, safe runtime deployment of distributed services, programmable networks |
37 | Timothy J. Purcell, Ian Buck, William R. Mark, Pat Hanrahan |
Ray tracing on programmable graphics hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Graph. ![In: ACM Trans. Graph. 21(3), pp. 703-712, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
ray tracing, programmable graphics hardware |
37 | Charles E. Stroud, James R. Bailey, Johan R. Emmert |
A New Method for Testing Re-Programmable PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(6), pp. 635-640, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
electrically erasable programmable logic array testing, manufacturing test development, bridging faults |
37 | Rahul Razdan, Michael D. Smith 0001 |
A high-performance microarchitecture with hardware-programmable functional units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 172-180, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
automatic instruction set design, compile-time optimization, general-purpose microarchitectures, logic synthesis, programmable logic |
37 | Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang |
A comparison of via-programmable gate array logic cell circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 53-62, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
logic cell, via-programmable gate arrays |
37 | Petr Pfeifer |
Multifunctional Programmable Single-Board CAN Monitoring Module. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 163-168, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Student Papers, FPL2000, programmable device, ALTERA, FLEX6000, EPF6016, SJA1000, PC/104, CAN |
36 | Dinesh Bhatia, James Haralambides |
Resource requirements and layouts for field programmable interconnection chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(3), pp. 346-355, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
36 | John Schewel, Michael Thornburg, Steve Casselman |
Transformable computers & hardware object technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 518-522, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
transformable computers, hardware object technology, reconfigurable aspects, computationally intensive software algorithms, on-the-fly use, field programmable gate arrays, field programmable gate arrays, programming, reconfigurable architectures, programmable logic arrays, hardware design, performance gain |
36 | Akihiro Tsutsui, Toshiaki Miyazaki, Kazuhisa Yamada, Naohisa Ohta |
Special purpose FPGA for high-speed digital telecommunication systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 486-491, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
special purpose FPGA, high-speed digital telecommunication systems, high-speed transport data processing, inter-chip connection mechanism, dedicated CAD system, field programmable gate arrays, field programmable gate array, programmable logic arrays, digital communication |
36 | Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose |
Logic synthesis for a single large look-up table. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 415-424, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
single large look-up table, LUT-based field-programmable gate array architectures, simulation time minimisation, compile-code, software simulation, field programmable gate arrays, Boolean function, logic design, logic synthesis, hardware accelerator, programmable logic arrays, table lookup, logic simulation, FPGA architectures, logic functions, on-chip memory, memory constraint |
35 | Richard B. Kujoth, Chi-Wei Wang, Derek B. Gottlieb, Jeffrey J. Cook, Nicholas P. Carter |
A reconfigurable unit for a clustered programmable-reconfigurable processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 200-209, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, technology scaling, reconfigurable processor |
34 | David Blythe |
The Direct3D 10 system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Graph. ![In: ACM Trans. Graph. 25(3), pp. 724-734, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
programmable graphics hardware, graphics systems, programmable shading |
34 | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne |
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 2(2), pp. 13:1-13:36, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Field Programmable Compressor Tree (FPCT), compressor tree, Field Programmable Gate Array (FPGA) |
34 | Tim Tuan, Sean Kao, Arifur Rahman, Satyaki Das, Steven Trimberger |
A 90nm low-power FPGA for battery-powered applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 3-11, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FPGAs, field-programmable gate arrays, low-power design, programmable logic |
34 | Seungkweon Jeong, Young Shin Kim, Wook Hyun Kwon |
Scheduling algorithm for programmable logic controllers with remote I/Os. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 4th International Workshop on Real-Time Computing Systems and Applications (RTCSA '97), 27-29 October 1997, Taipei, Taiwan, pp. 87-, 1997, IEEE Computer Society, 0-8186-8073-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
remote I/O, remote input output, sequence programs, application processor, bounded response time, scheduling algorithm, network processor, computer simulation, multitasking, data transmission, programmable logic controllers, PLC, programmable controllers |
34 | David Ashen, Fred J. Meyer, Nohpill Park, Fabrizio Lombardi |
Testing of programmable logic devices (PLD) with faulty resources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 76-84, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
faulty resources, routing resources, built-in self-test schemes, parity chain, one-dimensional arrays, active routing devices, interconnection channels, input/output lines, logic testing, fault model, fault coverage, multiple faults, programmable logic devices, programmable logic devices |
34 | Dieter Spath, Ulf Osmers |
Virtual Reality - An Approach to Improve the Generation of Fault-Free Software for Programmable Logic Controllers (PLC). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECCS ![In: 2nd IEEE International Conference on Engineering of Complex Computer Systems (ICECCS '96), 21-25 October 1996, Montreal, Canada, pp. 43-46, 1996, IEEE Computer Society, 0-8186-7614-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
fault free software, instruction list, ladder diagram, virtual reality, programmable logic controllers, programmable controllers, low-level languages |
34 | Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto |
Universal test complexity of field-programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 259-265, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
universal test complexity, arbitrary logic circuits, sequential loading, random access loading, programming schemes, block-sliced loading, configuration memory cells, field programmable gate arrays, field-programmable gate array, computational complexity, fault diagnosis, logic testing, design for testability, fault model, logic CAD, table lookup, look-up tables, automatic test software, C-testable |
34 | Hardy J. Pottinger, Chien-Yuh Lin |
Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 242-245, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education |
33 | Nan Wu 0003, Mei Wen, Wei Wu, Ju Ren 0002, Huayou Su, Changqing Xun, Chunyuan Zhang |
Streaming HD H.264 encoder on programmable processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Multimedia ![In: Proceedings of the 17th International Conference on Multimedia 2009, Vancouver, British Columbia, Canada, October 19-24, 2009, pp. 371-380, 2009, ACM, 978-1-60558-608-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
1080P HD, H.264 encoder, real-time, stream, programmable |
33 | Haiyan Li, Chunyuan Zhang, Li Li 0005, Ju Ren 0002 |
Transform coding on programmable stream processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 45(1), pp. 66-87, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Programmable stream processor, Imagine stream architecture, Graphics processing unit (GPU), H.264, Transform coding |
33 | Sven Woop, Jörg Schmittler, Philipp Slusallek |
RPU: a programmable ray processing unit for realtime ray tracing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Graph. ![In: ACM Trans. Graph. 24(3), pp. 434-444, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
ray processing unit, ray tracing, hardware architecture, programmable shading |
33 | Geoff Coulson, Gordon S. Blair, David Hutchison 0001, Ackbar Joolia, Kevin Lee, Jo Ueyama, Antônio Tadeu A. Gomes, Yimin Ye |
NETKIT: a software component-based approach to programmable networking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Commun. Rev. ![In: Comput. Commun. Rev. 33(5), pp. 55-66, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
middleware, components, reflection, programmable networking |
33 | Henry Selvaraj, Mariusz Rawski, Tadeusz Luba |
FSM Implementation in Embedded Memory Blocks of Programmable Logic Devices Using Functional Decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCC ![In: 2002 International Symposium on Information Technology (ITCC 2002), 8-10 April 2002, Las Vegas, NV, USA, pp. 355-360, 2002, IEEE Computer Society, 0-7695-1506-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
programmable read only memory, Boolean functions, implementation, digital circuits, sequential machines, logic minimization |
33 | Mark S. Peercy, Marc Olano, John Airey, P. Jeffrey Ungar |
Interactive multi-pass programmable shading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGGRAPH ![In: Proceedings of the 27th Annual Conference on Computer Graphics and Interactive Techniques, SIGGRAPH 2000, New Orleans, LA, USA, July 23-28, 2000, pp. 425-432, 2000, ACM, 1-58113-208-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
multi-pass rendering, rendering, texture mapping, languages, texture synthesis, graphics hardware, illumination, OpenGL, interactive rendering, graphics systems, non-realistic rendering, programmable shading, procedural shading |
33 | Jim Gindling, Andri Ioannidou, Jennifer Loh, Olav Lokkebo, Alexander Repenning |
LEGOsheets: A Rule-Based Programming, Simulation and Manipulation Environment for the LEG0 Programmable Brick. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VL ![In: Proceedings 11th International IEEE Symposium on Visual Languages, Darmstadt, Germany, September 5-9, 1995, pp. 172-179, 1995, IEEE Computer Society, 0-8186-7045-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
LEGO Programmable Brick, LEGOsheets, adult learning mechanisms, mechanical artifact design, simulation, robots, logic programming, software tools, computer science education, programming environments, programming environment, visual programming, visual programming, vehicles, computer aided instruction, programming education, rule-based programming, authoring systems, educational environment |
32 | Joel Sommers, Paul Barford, Mark Crovella |
Router primitives for programmable active measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRESTO ![In: Proceedings of the ACM SIGCOMM 2009 Workshop on Programmable Routers for Extensible Services of Tomorrow, PRESTO 2009, Barcelona, Spain, August 21, 2009, pp. 13-18, 2009, ACM, 978-1-60558-446-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
programmable measurement, router programmability, active measurement |
32 | Ran Giladi, Niv Yemini |
A programmable, generic forwarding element approach for dynamic network functionality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRESTO ![In: Proceedings of the ACM SIGCOMM 2009 Workshop on Programmable Routers for Extensible Services of Tomorrow, PRESTO 2009, Barcelona, Spain, August 21, 2009, pp. 19-24, 2009, ACM, 978-1-60558-446-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
forwarding element, programmable netwroks, network systems |
32 | Bruce S. Davie, Jan Medved |
A programmable overlay router for service provider innovation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRESTO ![In: Proceedings of the ACM SIGCOMM 2009 Workshop on Programmable Routers for Extensible Services of Tomorrow, PRESTO 2009, Barcelona, Spain, August 21, 2009, pp. 1-6, 2009, ACM, 978-1-60558-446-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
end-to-end argument, overlays, programmable routers |
32 | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne |
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 181-190, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
field programmable counter array (FPCA), FPGA |
32 | Frank-Michael Renner, Jürgen Becker 0001, Manfred Glesner |
Field Programmable Communication Emulation and Optimization for Embedded System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 58-67, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
architecture-precise rapid prototyping, field programmable emulation, Hardware/software codesign, real-time embedded systems |
32 | Vikram Pasham, Wilfrido Alejandro Moreno, Fernando J. Falquez |
Field Programmable Multi Chip Modules Using Programmable Laser Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), Clearwater, Florida, USA, June 16-18, 1999, pp. 210-, 1999, IEEE Computer Society, 0-7695-0246-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Multi-FPGAs, Laser Vertical Links, LPIC, MCM, Programmable interconnects |
31 | Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo |
The design of dynamically reconfigurable datapath coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 3(2), pp. 361-384, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
coarse-grain reconfigurable fabric, reconfigurable datapath, Loop pipelining, interconnection design, datapath synthesis |
31 | Zhining Huang, Sharad Malik |
Exploiting operation level parallelism through dynamically reconfigurable datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 337-342, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Scott A. Mahlke |
Bridging the computation gap between programmable processors and hardwired accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 313-322, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
31 | André Ribeiro Cardoso, Ahmed Serhrouchni, Joaquim Celestino Jr., Mikaël Salaün |
Convergence among Peer-to-Peer and Programmable Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECUMN ![In: Fourth European Conference on Universal Multiservice Networks (ECUMN 2007), 14-16 February 2007, Toulouse, France, pp. 45-51, 2007, IEEE Computer Society, 978-0-7695-2768-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Angel M. Gómez Argüello, João Navarro Jr., Wilhelmus A. M. Van Noije |
A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 144-148, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
high speed digital circuit, low power, prescaler, frequency synthesizer |
31 | Paul E. Hasler |
Low-Power Programmable Signal Processing, invited. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 413-418, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | S. A. Rahim, Laurence E. Turner |
A Field Programmable Bit-Serial Digital Signal Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 19-21 July 2004, Banff, Alberta, Canada, pp. 295-298, 2004, IEEE Computer Society, 0-7695-2182-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Matt Kucic, Paul E. Hasler, Jeff Dugger, David V. Anderson |
Programmable and Adaptive Analog Filters using Arrays of Floating-Gate Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 14-16 March 2001, Salt Lake City, UT, USA, pp. 148-162, 2001, IEEE Computer Society, 0-7695-1037-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Sushil Chandra Jain, Anshul Kumar, Shashi Kumar |
Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 201-210, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
31 | Yasuaki Sumi, Shigeki Obote, Naoki Kitai, Ryousuke Furuhashi, Yoshitaka Matsuda, Yutaka Fukui |
PLL frequency synthesizer with an auxiliary programmable divider. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 532-536, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Yen-Tai Lai, Ping-Tsung Wang |
Hierarchical interconnection structures for field programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 5(2), pp. 186-196, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
31 | Eric Lemoine, Laurent Maillet-Contoz, David Merceron, Jean Sallantin |
High speed intelligent machine through programmable hardware: application to genomic systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (2) ![In: Knowledge-Based Intelligent Electronic Systems, 1st International Conference, KES 1997, Adelaide, South Australia, 21-23 May, 1997, Proceedings, Part II, pp. 625-632, 1997, IEEE. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
31 | Anselmo Lastra, Steven Molnar, Marc Olano, Yulan Wang |
Real-Time Programmable Shading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SI3D ![In: Proceedings of the 1995 Symposium on Interactive 3D Graphics, SI3D '95, Monterey, CA, USA, April 9-12, 1995, pp. 59-66, 207, 1995, ACM, 0-89791-736-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
31 | Philip James-Roxby, Gordon J. Brebner |
Multithreading in a Hyper-programmable Platform for Networked Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 1017-1021, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | John Y. Oliver, Venkatesh Akella |
Improving DSP Performance with a Small Amount of Field Programmable Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 520-532, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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31 | Aneesh Koorapaty, Lawrence T. Pileggi |
Modular, Fabric-Specific Synthesis for Programmable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 132-141, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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