Search results for "programmable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
68	Zhuo Gao, Ji Luo 0003, Hu Huang 0001, Wei Zhang, Joseph B. Bernstein	Reliable Laser Programmable Gate Array Technology.	ISQED	2002	DBLP DOI BibTeX RDF	Laser Programmable Gate Array (LPGA), Laser Field-Programmable Gate Array (LFPGA), MakeLink technology, laser-induced/laser programmable anti-fuse, digital ASIC design, low electrical resistance anti-fuse, Field-Programmable Gate Array (FPGA)
56	André DeHon	Design of programmable interconnect for sublithographic programmable logic arrays.	FPGA	2005	DBLP DOI BibTeX RDF	Manhattan mesh, sublithographic architecture, programmable logic arrays, nanowires, programmable interconnect
53	Bradly K. Fawcett, J. Watson	Reconfigurable Processing With Field Programmable Gate Arrays.	ASAP	1996	DBLP DOI BibTeX RDF	reconfigurable processing, internal architecture, computationally-intensive tasks, programmable solution, XC6200 FPGA architecture, SRAM control store, on-chip memory capability, field programmable gate arrays, interconnections, reconfigurable architectures, processors, coprocessors, coprocessors, SRAM chips, SRAM-based field programmable gate arrays
50	Noha Kafafi, Kimberly A. Bozman, Steven J. E. Wilton	Architectures and algorithms for synthesizable embedded programmable logic cores.	FPGA	2003	DBLP DOI BibTeX RDF	programmable logic cores, FPGA, standard cells, system-on-chip design
49	Stuart W. Daniel, Jennifer Rexford, James W. Dolter, Kang G. Shin	A programmable routing controller for flexible communications in point-to-point networks.	ICCD	1995	DBLP DOI BibTeX RDF	programmable routing controller, flexible communications, communication characteristics, custom ASIC, programmable processor, multiple routing-switching microcode routines, multiprocessor interconnection networks, packet switching, packet switching, application specific integrated circuits, wormhole switching, programmable controllers, firmware, performance requirements, virtual cut-through switching, point-to-point networks
48	Alban Verdenal, Didier Combes, Abraham Escobar-Gutiérrez	Programmable and Self-Organised Processes in Plant Morphogenesis: The Architectural Development of Ryegrass.	Morphogenetic Engineering, Toward Programmable Complex Systems	2012	DBLP DOI BibTeX RDF
47	Wei-Kang Huang, Fabrizio Lombardi	An approach for testing programmable/configurable field programmable gate arrays.	VTS	1996	DBLP DOI BibTeX RDF	behavioral characterization, single fault detection, disjoint one-dimensional arrays, unilateral horizontal connections, common vertical input lines, array testing, logic blocks, field programmable gate arrays, field programmable gate arrays, VLSI, logic testing, integrated circuit testing, stuck-at fault, FPGA testing, functional fault, hybrid fault model
46	Narendra V. Shenoy, Jamil Kawa, Raul Camposano	Design automation for mask programmable fabrics.	DAC	2004	DBLP DOI BibTeX RDF	mask programmable fabrics, integrated circuits
45	Uwe Meyer-Bäse, Antonio García 0001, Fred J. Taylor	Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	field-programmable logic (FPL), complex programmable logic devices (CPLD), zero-IF filter, field programmable gate array (FPGA), digital signal processing (DSP), residue number system (RNS), channelizer
44	Jiri Stehlik, Daniel Becvar	Field Programmable Mixed-Signal Arrays (FPMA) Using Versatile Current/Voltage Conveyor Structures. (PDF / PS)	PWC	2007	DBLP DOI BibTeX RDF	Field Programmable Mixed-Signals Array, Programmable Universal Current Conveyor, Field Programmable Analog Array
44	Bin Liu, Fabrizio Lombardi, Wei-Kang Huang	Testing programmable interconnect systems: an algorithmic approach.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	programmable circuits, interconnected systems, programmable interconnect systems testing, algorithmic approach, programmable wiring networks, comprehensive fault model, network faults, open faults, switch faults, stuck-off faults, programming faults, minimal configuration number, node-disjoint path-sets, network adjacencies, post-processing algorithm, fault diagnosis, graphs, interconnections, fault detection, fault coverage, circuit analysis computing, stuck-at faults, switching, bridge faults, automatic test software, circuit testing, figure of merit, programming phases, stuck-on faults, short circuits
44	T. Utsumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	Multiple-Valued Programmable Logic Arrays with Universal Literals.	ISMVL	1997	DBLP DOI BibTeX RDF	universal literals, multiple-valued programmable logic, universal literal generators, operator structures, programmable logic arrays, programmable logic arrays
43	Ilija Hadzic, Jonathan M. Smith	Balancing performance and flexibility with hardware support for network architectures.	ACM Trans. Comput. Syst.	2003	DBLP DOI BibTeX RDF	P4, performance, FPGA, computer networking, hardware, flexibility, programmable networks, programmable logic devices, protocol processing
43	Amit Laknaur, Sai Raghuram Durbha, Haibo Wang 0005	Built-In-Self-Testing Techniques for Programmable Capacitor Arrays.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	programmable capacitor array, built-in-self-testing, analog testing, field programmable analog array
42	Daniela Rus	Programmable matter with self-reconfiguring robots.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	programmable matter, robotics
42	Michael Conrad, Thomas Fuhrmann, Marcus Schöller, Martina Zitterbart	Secure Service Signaling and Fast Authorization in Programmable Networks.	IWAN	2004	DBLP DOI BibTeX RDF	Flexible Service Platforms, Secure Signaling, Programmable Networks
41	Yao-Wen Chang, D. F. Wong 0001, C. K. Wong	Design and analysis of FPGA/FPIC switch modules.	ICCD	1995	DBLP DOI BibTeX RDF	FPGA/FPIC switch modules, routing resources, FPIC, network-flow techniques, field programmable interconnect chip, field programmable gate arrays, FPGA, field programmable gate arrays, logic design, heuristic algorithm, programmable logic arrays, routability
41	André DeHon, Michael J. Wilson	Nanowire-based sublithographic programmable logic arrays.	FPGA	2004	DBLP DOI BibTeX RDF	sublithographic architecture, programmable logic arrays, nanowires
41	Peter Hallschmid, Steven J. E. Wilton	Detailed routing architectures for embedded programmable logic IP cores.	FPGA	2001	DBLP DOI BibTeX RDF	FPGA, programmable logic, detailed routing, SoC design, embedded cores
40	JoAnn M. Paul, Donald E. Thomas, Andrew S. Cassidy	High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	schedulers, Computer-aided design, performance modeling, system modeling, heterogeneous multiprocessors
40	Kamran Zarrineh, Shambhu J. Upadhyaya	On Programmable Memory Built-In Self Test Architectures.	DATE	1999	DBLP DOI BibTeX RDF
40	Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici	Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!).	VTS	1996	DBLP DOI BibTeX RDF	BIST architecture, programmable logic blocks, field programmable gate arrays, VLSI, logic testing, built-in self test, built-in self-test, integrated circuit testing, automatic testing, FPGA testing, field programmable gate array testing
40	Lizy Kurian John	VaWiRAM: a variable width random access memory module.	VLSI Design	1996	DBLP DOI BibTeX RDF	VaWiRAM, variable width random access memory, flexible memory systems, configuration pins, pass gates, reconfigurability, reconfigurable architectures, memory architecture, programmable logic, random-access storage, integrated circuit interconnections, programmable logic devices, programmable interconnect
40	Santonu Sarkar, Anupam Basu, Arun K. Majumdar	Representation and Synthesis of Interface of a Circuit for its Reuse.	VLSI Design	1996	DBLP DOI BibTeX RDF	VaWiRAM, variable width random access memory, flexible memory systems, configuration pins, pass gates, reconfigurability, reconfigurable architectures, memory architecture, programmable logic, random-access storage, integrated circuit interconnections, programmable logic devices, programmable interconnect
39	Yaochu Jin, Yan Meng	Morphogenetic Robotics: A New Paradigm for Designing Self-Organizing, Self-Reconfigurable and Self-Adaptive Robots.	Morphogenetic Engineering, Toward Programmable Complex Systems	2012	DBLP DOI BibTeX RDF
39	Daniel Lobo, Jose D. Fernández, Francisco J. Vico	Behavior-Finding: Morphogenetic Designs Shaped by Function.	Morphogenetic Engineering, Toward Programmable Complex Systems	2012	DBLP DOI BibTeX RDF
39	Sylvain Cussat-Blanc, Jonathan Pascalie, Sébastien Mazac, Hervé Luga, Yves Duthen	A Synthesis of the Cell2Organ Developmental Model.	Morphogenetic Engineering, Toward Programmable Complex Systems	2012	DBLP DOI BibTeX RDF
39	Navneet Bhalla, Peter J. Bentley	Programming Self-Assembling Systems via Physically Encoded Information.	Morphogenetic Engineering, Toward Programmable Complex Systems	2012	DBLP DOI BibTeX RDF
39	Wenguo Liu 0001, Alan F. T. Winfield	Distributed Autonomous Morphogenesis in a Self-Assembling Robotic System.	Morphogenetic Engineering, Toward Programmable Complex Systems	2012	DBLP DOI BibTeX RDF
39	René Doursat, Carlos Sánchez, Razvan Dordea, David Fourquet, Taras Kowaliw	Embryomorphic Engineering: Emergent Innovation Through Evolutionary Development.	Morphogenetic Engineering, Toward Programmable Complex Systems	2012	DBLP DOI BibTeX RDF
39	Sara Montagna, Mirko Viroli	A Computational Framework for Multilevel Morphologies.	Morphogenetic Engineering, Toward Programmable Complex Systems	2012	DBLP DOI BibTeX RDF
39	Rehan O'Grady, Anders Lyhne Christensen, Marco Dorigo	SWARMORPH: Morphogenesis with Self-Assembling Robots.	Morphogenetic Engineering, Toward Programmable Complex Systems	2012	DBLP DOI BibTeX RDF
39	Sebastian von Mammen, David Phillips, Timothy Davison, Heather A. Jamniczky, Benedikt Hallgrímsson, Christian Jacob 0001	Swarm-Based Computational Development.	Morphogenetic Engineering, Toward Programmable Complex Systems	2012	DBLP DOI BibTeX RDF
39	Hiroki Sayama	Swarm-Based Morphogenetic Artificial Life.	Morphogenetic Engineering, Toward Programmable Complex Systems	2012	DBLP DOI BibTeX RDF
39	Daniel J. Arbuckle, Aristides A. G. Requicha	Issues in Self-Repairing Robotic Self-Assembly.	Morphogenetic Engineering, Toward Programmable Complex Systems	2012	DBLP DOI BibTeX RDF
39	Antoine Spicher, Olivier Michel 0001, Jean-Louis Giavitto	Interaction-Based Modeling of Morphogenesis in MGS.	Morphogenetic Engineering, Toward Programmable Complex Systems	2012	DBLP DOI BibTeX RDF
39	Linge Bai, David E. Breen	Chemotaxis-Inspired Cellular Primitives for Self-Organizing Shape Formation.	Morphogenetic Engineering, Toward Programmable Complex Systems	2012	DBLP DOI BibTeX RDF
39	René Doursat, Hiroki Sayama, Olivier Michel 0001	Morphogenetic Engineering: Reconciling Self-Organization and Architecture.	Morphogenetic Engineering, Toward Programmable Complex Systems	2012	DBLP DOI BibTeX RDF
39	Alan F. T. Winfield, Julien Nembrini	Emergent Swarm Morphology Control of Wireless Networked Mobile Robots.	Morphogenetic Engineering, Toward Programmable Complex Systems	2012	DBLP DOI BibTeX RDF
39	Taras Kowaliw, Wolfgang Banzhaf	Mechanisms for Complex Systems Engineering Through Artificial Development.	Morphogenetic Engineering, Toward Programmable Complex Systems	2012	DBLP DOI BibTeX RDF
39	Jacob Beal	Functional Blueprints: An Approach to Modularity in Grown Systems.	Morphogenetic Engineering, Toward Programmable Complex Systems	2012	DBLP DOI BibTeX RDF
39	Justin Werfel	Collective Construction with Robot Swarms.	Morphogenetic Engineering, Toward Programmable Complex Systems	2012	DBLP DOI BibTeX RDF
38	André DeHon	Nanowire-based programmable architectures.	ACM J. Emerg. Technol. Comput. Syst.	2005	DBLP DOI BibTeX RDF	Manhattan mesh, stochastic construction, sublithographic architecture, programmable logic arrays, Defect tolerance, nanowires, programmable interconnect
38	Vi Chi Chan, David Lewis	Hierarchical partitioning for field-programmable systems.	ICCAD	1997	DBLP DOI BibTeX RDF	FPGA partitioning problems, circuit structures, field-programmable systems, partitioning tree, recursive bipartitioning algorithm, field programmable gate arrays, VLSI, quality, logic CAD, hierarchical partitioning
38	Wei-Kang Huang, Xiao-Tao Chen, Fabrizio Lombardi	On the diagnosis of programmable interconnect systems: Theory and application.	VTS	1996	DBLP DOI BibTeX RDF	field programmable interconnect system, switch grid, FPIS, Xilinx 3000, field programmable gate arrays, FPGA, fault diagnosis, logic testing, diagnosis, integrated circuit interconnections
38	Dinesh Bhatia, James Haralambides	Resource requirements for field programmable interconnection chips.	VLSI Design	1995	DBLP DOI BibTeX RDF	field programmable interconnection chips, n-permutation graph, network property, routing delays, programmable switches, routing paths, specific I/O permutations, user-configured interconnection, VLSI, VLSI, graph theory, network routing, permutation networks, integrated circuit interconnections, Benes network
37	Jason Helge Anderson	Emerging application domains: research challenges and opportunities for FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	performance, field-programmable gate array, fpga, applications, high-performance computing, power, reconfigurable computing
37	Nikolas Kroupis, Nikolaos D. Zervas, Minas Dasygenis, Konstantinos Tatas, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis	Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	Programmable platforms, estimation methodology, instruction complexity, memory transfers
37	Shree K. Nayar, Vlad Branzoi, Terrance E. Boult	Programmable Imaging: Towards a Flexible Camera.	Int. J. Comput. Vis.	2006	DBLP DOI BibTeX RDF	programmable imaging, flexible imaging, micro-mirror array, digital micro-mirror device, adaptive optics, optical processing, multi-viewpoint imaging, catadioptric imaging, wide-angle imaging, purposive camera, object recognition, stereo, resolution, MEMS, feature detection, high dynamic range imaging, field of view
37	Gonçalo Nuno Moutinho de Carvalho, Tony Gill, Tony Parisi	X3D programmable shaders.	Web3D	2004	DBLP DOI BibTeX RDF	real-time shading, GPU, VRML, X3D, stream processors, programmable shading
37	Paul Willmann, Michael Brogioli, Vijay S. Pai	Spinach: a liberty-based simulator for programmable network interface architectures.	LCTES	2004	DBLP DOI BibTeX RDF	programmable network interfaces, simulation, embedded systems
37	Luca Macchiarulo, Consolato F. Caccamo, Davide Pandini	A comparison between mask- and field-programmable routing structures on industrial FPGA architectures.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	mask-programmable, FPGA, routing, interconnect architectures
37	Nico Janssens, Lieven Desmet, Sam Michiels, Pierre Verbaeten	NeCoMan: middleware for safe distributed service deployment in programmable networks.	Adaptive and Reflective Middleware	2004	DBLP DOI BibTeX RDF	network consistency, safe runtime deployment of distributed services, programmable networks
37	Timothy J. Purcell, Ian Buck, William R. Mark, Pat Hanrahan	Ray tracing on programmable graphics hardware.	ACM Trans. Graph.	2002	DBLP DOI BibTeX RDF	ray tracing, programmable graphics hardware
37	Charles E. Stroud, James R. Bailey, Johan R. Emmert	A New Method for Testing Re-Programmable PLAs.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	electrically erasable programmable logic array testing, manufacturing test development, bridging faults
37	Rahul Razdan, Michael D. Smith 0001	A high-performance microarchitecture with hardware-programmable functional units.	MICRO	1994	DBLP DOI BibTeX RDF	automatic instruction set design, compile-time optimization, general-purpose microarchitectures, logic synthesis, programmable logic
37	Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang	A comparison of via-programmable gate array logic cell circuits.	FPGA	2009	DBLP DOI BibTeX RDF	logic cell, via-programmable gate arrays
37	Petr Pfeifer	Multifunctional Programmable Single-Board CAN Monitoring Module.	FPL	2000	DBLP DOI BibTeX RDF	Student Papers, FPL2000, programmable device, ALTERA, FLEX6000, EPF6016, SJA1000, PC/104, CAN
36	Dinesh Bhatia, James Haralambides	Resource requirements and layouts for field programmable interconnection chips.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
36	John Schewel, Michael Thornburg, Steve Casselman	Transformable computers & hardware object technology.	IPPS	1995	DBLP DOI BibTeX RDF	transformable computers, hardware object technology, reconfigurable aspects, computationally intensive software algorithms, on-the-fly use, field programmable gate arrays, field programmable gate arrays, programming, reconfigurable architectures, programmable logic arrays, hardware design, performance gain
36	Akihiro Tsutsui, Toshiaki Miyazaki, Kazuhisa Yamada, Naohisa Ohta	Special purpose FPGA for high-speed digital telecommunication systems.	ICCD	1995	DBLP DOI BibTeX RDF	special purpose FPGA, high-speed digital telecommunication systems, high-speed transport data processing, inter-chip connection mechanism, dedicated CAD system, field programmable gate arrays, field programmable gate array, programmable logic arrays, digital communication
36	Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose	Logic synthesis for a single large look-up table.	ICCD	1995	DBLP DOI BibTeX RDF	single large look-up table, LUT-based field-programmable gate array architectures, simulation time minimisation, compile-code, software simulation, field programmable gate arrays, Boolean function, logic design, logic synthesis, hardware accelerator, programmable logic arrays, table lookup, logic simulation, FPGA architectures, logic functions, on-chip memory, memory constraint
35	Richard B. Kujoth, Chi-Wei Wang, Derek B. Gottlieb, Jeffrey J. Cook, Nicholas P. Carter	A reconfigurable unit for a clustered programmable-reconfigurable processor.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, technology scaling, reconfigurable processor
34	David Blythe	The Direct3D 10 system.	ACM Trans. Graph.	2006	DBLP DOI BibTeX RDF	programmable graphics hardware, graphics systems, programmable shading
34	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne	Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	Field Programmable Compressor Tree (FPCT), compressor tree, Field Programmable Gate Array (FPGA)
34	Tim Tuan, Sean Kao, Arifur Rahman, Satyaki Das, Steven Trimberger	A 90nm low-power FPGA for battery-powered applications.	FPGA	2006	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, low-power design, programmable logic
34	Seungkweon Jeong, Young Shin Kim, Wook Hyun Kwon	Scheduling algorithm for programmable logic controllers with remote I/Os.	RTCSA	1997	DBLP DOI BibTeX RDF	remote I/O, remote input output, sequence programs, application processor, bounded response time, scheduling algorithm, network processor, computer simulation, multitasking, data transmission, programmable logic controllers, PLC, programmable controllers
34	David Ashen, Fred J. Meyer, Nohpill Park, Fabrizio Lombardi	Testing of programmable logic devices (PLD) with faulty resources.	DFT	1997	DBLP DOI BibTeX RDF	faulty resources, routing resources, built-in self-test schemes, parity chain, one-dimensional arrays, active routing devices, interconnection channels, input/output lines, logic testing, fault model, fault coverage, multiple faults, programmable logic devices, programmable logic devices
34	Dieter Spath, Ulf Osmers	Virtual Reality - An Approach to Improve the Generation of Fault-Free Software for Programmable Logic Controllers (PLC).	ICECCS	1996	DBLP DOI BibTeX RDF	fault free software, instruction list, ladder diagram, virtual reality, programmable logic controllers, programmable controllers, low-level languages
34	Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto	Universal test complexity of field-programmable gate arrays.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	universal test complexity, arbitrary logic circuits, sequential loading, random access loading, programming schemes, block-sliced loading, configuration memory cells, field programmable gate arrays, field-programmable gate array, computational complexity, fault diagnosis, logic testing, design for testability, fault model, logic CAD, table lookup, look-up tables, automatic test software, C-testable
34	Hardy J. Pottinger, Chien-Yuh Lin	Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education
33	Nan Wu 0003, Mei Wen, Wei Wu, Ju Ren 0002, Huayou Su, Changqing Xun, Chunyuan Zhang	Streaming HD H.264 encoder on programmable processors.	ACM Multimedia	2009	DBLP DOI BibTeX RDF	1080P HD, H.264 encoder, real-time, stream, programmable
33	Haiyan Li, Chunyuan Zhang, Li Li 0005, Ju Ren 0002	Transform coding on programmable stream processors.	J. Supercomput.	2008	DBLP DOI BibTeX RDF	Programmable stream processor, Imagine stream architecture, Graphics processing unit (GPU), H.264, Transform coding
33	Sven Woop, Jörg Schmittler, Philipp Slusallek	RPU: a programmable ray processing unit for realtime ray tracing.	ACM Trans. Graph.	2005	DBLP DOI BibTeX RDF	ray processing unit, ray tracing, hardware architecture, programmable shading
33	Geoff Coulson, Gordon S. Blair, David Hutchison 0001, Ackbar Joolia, Kevin Lee, Jo Ueyama, Antônio Tadeu A. Gomes, Yimin Ye	NETKIT: a software component-based approach to programmable networking.	Comput. Commun. Rev.	2003	DBLP DOI BibTeX RDF	middleware, components, reflection, programmable networking
33	Henry Selvaraj, Mariusz Rawski, Tadeusz Luba	FSM Implementation in Embedded Memory Blocks of Programmable Logic Devices Using Functional Decomposition.	ITCC	2002	DBLP DOI BibTeX RDF	programmable read only memory, Boolean functions, implementation, digital circuits, sequential machines, logic minimization
33	Mark S. Peercy, Marc Olano, John Airey, P. Jeffrey Ungar	Interactive multi-pass programmable shading.	SIGGRAPH	2000	DBLP DOI BibTeX RDF	multi-pass rendering, rendering, texture mapping, languages, texture synthesis, graphics hardware, illumination, OpenGL, interactive rendering, graphics systems, non-realistic rendering, programmable shading, procedural shading
33	Jim Gindling, Andri Ioannidou, Jennifer Loh, Olav Lokkebo, Alexander Repenning	LEGOsheets: A Rule-Based Programming, Simulation and Manipulation Environment for the LEG0 Programmable Brick.	VL	1995	DBLP DOI BibTeX RDF	LEGO Programmable Brick, LEGOsheets, adult learning mechanisms, mechanical artifact design, simulation, robots, logic programming, software tools, computer science education, programming environments, programming environment, visual programming, visual programming, vehicles, computer aided instruction, programming education, rule-based programming, authoring systems, educational environment
32	Joel Sommers, Paul Barford, Mark Crovella	Router primitives for programmable active measurement.	PRESTO	2009	DBLP DOI BibTeX RDF	programmable measurement, router programmability, active measurement
32	Ran Giladi, Niv Yemini	A programmable, generic forwarding element approach for dynamic network functionality.	PRESTO	2009	DBLP DOI BibTeX RDF	forwarding element, programmable netwroks, network systems
32	Bruce S. Davie, Jan Medved	A programmable overlay router for service provider innovation.	PRESTO	2009	DBLP DOI BibTeX RDF	end-to-end argument, overlays, programmable routers
32	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne	Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	field programmable counter array (FPCA), FPGA
32	Frank-Michael Renner, Jürgen Becker 0001, Manfred Glesner	Field Programmable Communication Emulation and Optimization for Embedded System Design.	FPL	2000	DBLP DOI BibTeX RDF	architecture-precise rapid prototyping, field programmable emulation, Hardware/software codesign, real-time embedded systems
32	Vikram Pasham, Wilfrido Alejandro Moreno, Fernando J. Falquez	Field Programmable Multi Chip Modules Using Programmable Laser Interconnects.	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	Multi-FPGAs, Laser Vertical Links, LPIC, MCM, Programmable interconnects
31	Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo	The design of dynamically reconfigurable datapath coprocessors.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	coarse-grain reconfigurable fabric, reconfigurable datapath, Loop pipelining, interconnection design, datapath synthesis
31	Zhining Huang, Sharad Malik	Exploiting operation level parallelism through dynamically reconfigurable datapaths.	DAC	2002	DBLP DOI BibTeX RDF
31	Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Scott A. Mahlke	Bridging the computation gap between programmable processors and hardwired accelerators.	HPCA	2009	DBLP DOI BibTeX RDF
31	André Ribeiro Cardoso, Ahmed Serhrouchni, Joaquim Celestino Jr., Mikaël Salaün	Convergence among Peer-to-Peer and Programmable Networks.	ECUMN	2007	DBLP DOI BibTeX RDF
31	Angel M. Gómez Argüello, João Navarro Jr., Wilhelmus A. M. Van Noije	A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer.	SBCCI	2005	DBLP DOI BibTeX RDF	high speed digital circuit, low power, prescaler, frequency synthesizer
31	Paul E. Hasler	Low-Power Programmable Signal Processing, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
31	S. A. Rahim, Laurence E. Turner	A Field Programmable Bit-Serial Digital Signal Processor.	IWSOC	2004	DBLP DOI BibTeX RDF
31	Matt Kucic, Paul E. Hasler, Jeff Dugger, David V. Anderson	Programmable and Adaptive Analog Filters using Arrays of Floating-Gate Circuits.	ARVLSI	2001	DBLP DOI BibTeX RDF
31	Sushil Chandra Jain, Anshul Kumar, Shashi Kumar	Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards.	FPL	2000	DBLP DOI BibTeX RDF
31	Yasuaki Sumi, Shigeki Obote, Naoki Kitai, Ryousuke Furuhashi, Yoshitaka Matsuda, Yutaka Fukui	PLL frequency synthesizer with an auxiliary programmable divider.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
31	Yen-Tai Lai, Ping-Tsung Wang	Hierarchical interconnection structures for field programmable gate arrays.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
31	Eric Lemoine, Laurent Maillet-Contoz, David Merceron, Jean Sallantin	High speed intelligent machine through programmable hardware: application to genomic systems.	KES (2)	1997	DBLP DOI BibTeX RDF
31	Anselmo Lastra, Steven Molnar, Marc Olano, Yulan Wang	Real-Time Programmable Shading.	SI3D	1995	DBLP DOI BibTeX RDF
31	Philip James-Roxby, Gordon J. Brebner	Multithreading in a Hyper-programmable Platform for Networked Systems.	FPL	2004	DBLP DOI BibTeX RDF
31	John Y. Oliver, Venkatesh Akella	Improving DSP Performance with a Small Amount of Field Programmable Logic.	FPL	2003	DBLP DOI BibTeX RDF
31	Aneesh Koorapaty, Lawrence T. Pileggi	Modular, Fabric-Specific Synthesis for Programmable Architectures.	FPL	2002	DBLP DOI BibTeX RDF