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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 244 occurrences of 152 keywords
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Results
Found 1965 publication records. Showing 1965 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
88 | Shweta Chary, Michael L. Bushnell |
Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
75 | Stuart E. Schechter, Gabriel H. Loh, Karin Strauss, Doug Burger |
Use ECP, not ECC, for hard failures in resistive memories. |
ISCA |
2010 |
DBLP DOI BibTeX RDF |
hard failures, resistive memories, memory, error correction, phase change memory |
75 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian |
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. |
J. Electron. Test. |
2007 |
DBLP DOI BibTeX RDF |
Resistive-open defects, Pre-charge circuits, Memory testing, Dynamic faults |
75 | Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker 0001 |
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
Temperature testing, Resistive defects, Early-life failures, Low-voltage testing |
75 | Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001 |
Simulating Resistive Bridging and Stuck-At Faults. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
Resistive stuck-at faults, probabilistic fault coverage, Resistive bridging faults, bridging fault simulation |
67 | Shweta Chary, Michael L. Bushnell |
Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
64 | Piet Engelke, Bernd Becker 0001, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian |
SUPERB: Simulator utilizing parallel evaluation of resistive bridges. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
PPSFP, SPPFP, fault mapping, Resistive bridging faults, bridging fault simulation |
64 | Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001 |
Automatic Test Pattern Generation for Resistive Bridging Faults. |
J. Electron. Test. |
2006 |
DBLP DOI BibTeX RDF |
resistive short defects, ATPG, SAT, bridging faults |
54 | Haihua Yan, Adit D. Singh |
A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
54 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian |
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
SRAM memories, VDSM technologies, core-cell, test, march test, dynamic faults, defect analysis |
54 | Antonio Zenteno, Víctor H. Champac |
Resistive Opens in a Class of CMOS Latches: Analysis and DFT. |
VTS |
2001 |
DBLP DOI BibTeX RDF |
|
54 | Ilia Polian, Sandip Kundu, Jean-Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker 0001 |
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
Deep submicron technology modeling, Resistive bridging faults |
54 | Chul Young Lee, D. M. H. Walker |
PROBE: A PPSFP Simulator for Resistive Bridging Faults. |
VTS |
2000 |
DBLP DOI BibTeX RDF |
PPSFP, fault model, fault simulation, bridging fault, resistive bridging faults |
52 | Quming Zhou, Kartik Mohanram |
Analysis of delay caused by bridging faults in RLC interconnects. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
52 | Chang-Han Yi, Robert Schlabbach, Holger Kroth, Heinrich Klar |
A New Bio-inspired Algorithm for Early Vision Edge Detection and Image Segmentation. |
IWANN |
1997 |
DBLP DOI BibTeX RDF |
|
52 | John G. Harris, Christof Koch, Erik Staats, Jin Luo |
Analog hardware for detecting discontinuities in early vision. |
Int. J. Comput. Vis. |
1990 |
DBLP DOI BibTeX RDF |
|
44 | Jae-Sung Kong, Sang-Heon Kim, Jang-Kyoo Shin, Minho Lee 0001 |
An Artificial Retina Chip Using Switch-Selective Resistive Network for Intelligent Sensor Systems. |
ICIC (3) |
2006 |
DBLP DOI BibTeX RDF |
|
44 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan |
Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
44 | Uday Dasgupta, Yong Ping Xu |
Effects of resistive loading on unity gain frequency of two-stage CMOS operational amplifiers. |
ISCAS (1) |
2003 |
DBLP DOI BibTeX RDF |
|
44 | Marco S. Dragic, Martin Margala |
Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits. |
DFT |
2003 |
DBLP DOI BibTeX RDF |
|
44 | Mohsen Taherian, Morteza Amini, Rasool Jalili |
Trust Inference in Web-Based Social Networks Using Resistive Networks. |
ICIW |
2008 |
DBLP DOI BibTeX RDF |
Trust Inference, Web-based Social Networks, Resistive Circuits |
44 | Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker 0001 |
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. |
VTS |
2004 |
DBLP DOI BibTeX RDF |
Very-Low-Voltage testing, Resistive short defects |
44 | Arun Krishnamachary, Jacob A. Abraham |
Test generation for resistive opens in CMOS. |
ACM Great Lakes Symposium on VLSI |
2002 |
DBLP DOI BibTeX RDF |
resistive opens, delay testing, defect detection |
44 | Ad J. van de Goor, J. E. Simonse |
Defining SRAM Resistive Defects and Their Simulation Stimuli. |
Asian Test Symposium |
1999 |
DBLP DOI BibTeX RDF |
Resistive defects, simulation stimuli, SRAM functional faults, SPICE simulation |
44 | Vijay R. Sar-Dessai, D. M. H. Walker |
Accurate Fault Modeling and Fault Simulation of Resistive Bridges. |
DFT |
1998 |
DBLP DOI BibTeX RDF |
realistic bridges, zero-ohm bridges, Resistive bridging faults, low-voltage testing |
41 | Edward K. S. Au, Wing-Hung Ki, Wai Ho Mow, Silas T. Hung, Catherine Y. Wong |
A binary--search switched--current sensing scheme for 4-state MRAM. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
magneto-resistive random access memory, switched-current |
41 | Andreas E. Gygi, George S. Moschytz |
Low-pass filter effect in the measurement of surface EMG. |
CBMS |
1997 |
DBLP DOI BibTeX RDF |
low pass filter effect, surface EMG measurement, muscular tissue, purely resistive medium, network theoretic viewpoint, simplified tissue model, electrical activity, muscle fibres, independant variables, space domain, electromyography, electrical engineering |
41 | Yuyun Liao, D. M. H. Walker |
Optimal voltage testing for physically-based faults. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise |
41 | Ali Chehab, Saurabh Patel, Rafic Z. Makki |
Scaling of iDDT Test Methods for Random Logic Circuits. |
J. Electron. Test. |
2006 |
DBLP DOI BibTeX RDF |
dynamic power supply current, design for current testability, resistive opens, resistive bridges, very deep sub-micron technologies, VDSM, fault simulation |
34 | Xiaochen Guo, Engin Ipek, Tolga Soyata |
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing. |
ISCA |
2010 |
DBLP DOI BibTeX RDF |
STT-MRAM, power-efficiency |
34 | Ji-Man Park, Sung-Ik Jun |
A resistance deviation-to-time interval converter for resistive sensors. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Alexandre Ney, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian |
Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. |
ETS |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Hugo Cheung, Sandeep K. Gupta |
Accurate modeling and fault simulation of Byzantine resistive bridges. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Alexandre Ney, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian |
Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001 |
Simulating Resistive-Bridging and Stuck-At Faults. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan |
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. |
J. Electron. Test. |
2006 |
DBLP DOI BibTeX RDF |
address decoders, memory testing, dynamic faults |
34 | Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier |
Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects. |
DFT |
2006 |
DBLP DOI BibTeX RDF |
defective interconnects, defect’s severity, fault model, crosstalk, bridging fault |
34 | Lushan Liu, Ramalingam Sridhar, Shambhu J. Upadhyaya |
A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells. |
DFT |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Heinz Koeppl |
Information Rate Maximization over a Resistive Grid. |
IJCNN |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Rongde Lu, An Lu |
Applications of the Superposition Theorem to Nonlinear Resistive Circuits. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Chien-Mo James Li, Edward J. McCluskey |
Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Keng Hoong Wee, Ji-Jon Sit, Rahul Sarpeshkar |
Biasing techniques for subthreshold MOS resistive grids. |
ISCAS (3) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Xiang Lu, Zhuo Li 0001, Wangqi Qiu, D. M. H. Walker, Weiping Shi |
A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. |
MTV |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Mohamed Azimane, Ananta K. Majhi |
New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders. |
VTS |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri |
Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Cheuk-Yiu Ng, Mitchai Chongcheawchamnan, Ian D. Robertson, K. Cho |
Resistive FET IQ vector modulator using multilayer photoimageable thick-film technology. |
ISCAS (1) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Zhuo Li 0001, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker |
A Circuit Level Fault Model for Resistive Opens and Bridges. |
VTS |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Bram Kruseman, Stefan van den Oetelaar |
Detection of Resistive Shorts in Deep Sub-micron Technologies. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Shaw Voon Wong, Abdel Magid S. Hamouda, M. Saleem J. Hashmi |
Development of Revolute-Joint Element with Rotation Limits, Locking, Resistive Moment and Damping. |
Eng. Comput. |
2002 |
DBLP DOI BibTeX RDF |
Adaptive stiffness method, Finite difference model, Locking mechanism, Numerical stability criterion, Revolute joint algorithm, Revolute joint element |
34 | Tsuyoshi Shinogi, Tomokazu Kanbayashi, Tomohiro Yoshikawa, Shinji Tsuruoka, Terumine Hayashi |
Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG Systems. |
Asian Test Symposium |
2001 |
DBLP DOI BibTeX RDF |
|
33 | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
Impact of Resistive-Bridging Defects in SRAM Core-Cell. |
DELTA |
2010 |
DBLP DOI BibTeX RDF |
core-cell, resistive-bridging defects, SRAM |
33 | Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker 0001 |
A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. |
ETS |
2008 |
DBLP DOI BibTeX RDF |
Small-delay defects, resistive opens, probabilistic fault coverage, bridging fault simulation |
33 | Michel Renovell, P. Huc, Yves Bertrand |
The concept of resistance interval: a new parametric model for realistic resistive bridging fault. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
electric resistance, resistance interval, intrinsic resistance, logic behavior, 0 to 500 ohm, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, fault detection, automatic testing, fault coverage, bridging faults, parametric model, logic gates, logic gates, resistive bridging fault, faulty behavior |
31 | Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor |
Test-Pattern Grading and Pattern Selection for Small-Delay Defects. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
Small-delay defects, pattern grading, pattern selection, ATPG |
31 | Abhishek Singh 0001, Jim Plusquellic, Dhananjay S. Phatak, Chintan Patel |
Defect Simulation Methodology for iDDT Testing. |
J. Electron. Test. |
2006 |
DBLP DOI BibTeX RDF |
iDDT, transient current testing, device testing, ATPG, fault simulation, IDDQ, defect simulation, defect-based test |
31 | Simone Borri, Magali Hage-Hassan, Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel |
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. |
J. Electron. Test. |
2005 |
DBLP DOI BibTeX RDF |
address decoders, core-cells, memory testing, dynamic faults |
31 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan |
Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri |
March iC-: An Improved Version of March C- for ADOFs Detection. |
VTS |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski |
Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Sri Vinayagamoorthy, Richard Hornsey |
On chip Gaussian processing for high resolution CMOS image sensors. |
ISCAS (4) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Andrey V. Mezhiba, Eby G. Friedman |
Scaling trends of on-chip Power distribution noise. |
SLIP |
2002 |
DBLP DOI BibTeX RDF |
technology scaling, power supply noise, power distribution |
31 | Marcello Dalpasso, Michele Favalli, Piero Olivo, Bruno Riccò |
Fault simulation of parametric bridging faults in CMOS IC's. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
31 | Andrew Lumsdaine, John L. Wyatt Jr., Ibrahim M. Elfadel |
Nonlinear analog networks for image smoothing and segmentation. |
J. VLSI Signal Process. |
1991 |
DBLP DOI BibTeX RDF |
|
31 | Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker 0001 |
Modeling Feedback Bridging Faults with Non-Zero Resistance. |
J. Electron. Test. |
2005 |
DBLP DOI BibTeX RDF |
feedback bridging faults, resistive bridging faults, bridging fault simulation |
31 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Hage-Hassan |
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. |
J. Electron. Test. |
2005 |
DBLP DOI BibTeX RDF |
SRAM core-cell, resistive open defects, memory testing, March test, dynamic faults |
31 | Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker 0001 |
X-Masking During Logic BIST and Its Impact on Defect Coverage. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
X-Masking, Resistive Bridging Faults, Defect Coverage, Logic BIST |
31 | Sreenivas Mandava, Sreejit Chakravarty, Sandip Kundu |
On Detecting Bridges Causing Timing Failures. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
Resistive Bridges, Timing Failures, Transition Fault Model, Delay Test, At-Speed Testing, Low Voltage Testing |
31 | Yu-Yau Guo, Jien-Chung Lo, Cecilia Metra |
Fast and area-time efficient Berger code checkers. |
DFT |
1997 |
DBLP DOI BibTeX RDF |
Berger code checker, ratioed FET circuit, area-time efficiency, resistive breaks, VLSI, defects, error detection codes, bridges, speed, threshold function, 32 bit, 1.2 micron |
31 | Claude Thibeault |
Detection and location of faults and defects using digital signal processing. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
sampled current, sampled voltage, quiescent current, parasitic resistive contacts, DSP technique, fault diagnosis, logic testing, integrated circuit testing, fault detection, diagnosis, signal processing, digital signal processing, fault location, fault location, defects, digital integrated circuits, test method |
26 | Olivier Michel 0002 |
Analyse mathématique et numérique d'un modèle quasi-cinétique pour la fermeture non-locale des équations de la MHD résistive. (Mathematical and numerical analysis of a quasi-kinetic model for the resistive MHD non-local closure). |
|
2022 |
RDF |
|
26 | W. Zhang, Stephen C. Jardin, Zhiwei Ma, Andreas Kleiner, H. W. Zhang |
Linear and nonlinear benchmarks between the CLT code and the M3D-C1 code for the 2/1 resistive tearing mode and the 1/1 resistive kink mode. |
Comput. Phys. Commun. |
2021 |
DBLP DOI BibTeX RDF |
|
26 | D. Borba, Kurt S. Riedel, W. Kerner, G. T. A. Huysmans, M. Ottaviani, P. J. Schmid |
Pseudo-Spectrum of the Resistive Magneto-hydrodynamics Operator: Resolving the Resistive Alfven Paradox. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
26 | Amirali Ghofrani, Miguel Angel Lastras-Montaño, Yuyang Wang 0003, Kwang-Ting Cheng |
In-place Repair for Resistive Memories Utilizing Complementary Resistive Switches. |
ISLPED |
2016 |
DBLP DOI BibTeX RDF |
|
26 | Andrew J. Lohn, Patrick R. Mickel, Conrad D. James, Matthew J. Marinella |
Degenerate Resistive Switching and Ultrahigh Density Storage in Resistive Memory. |
CoRR |
2014 |
DBLP BibTeX RDF |
|
26 | Shida Zhong, S. Saqib Khursheed, Bashir M. Al-Hashimi |
Impact of PVT variation on delay test of resistive open and resistive bridge defects. |
DFTS |
2013 |
DBLP DOI BibTeX RDF |
|
26 | Piet Engelke |
Resistive bridging faults - defect-oriented modeling and efficient testing (Resistive bridging faults - defektorientierte Modellierung und effizienter Test) |
|
2009 |
RDF |
|
23 | Engin Ipek, Jeremy Condit, Edmund B. Nightingale, Doug Burger, Thomas Moscibroda |
Dynamically replicated memory: building reliable systems from nanoscale resistive memories. |
ASPLOS |
2010 |
DBLP DOI BibTeX RDF |
write endurance, phase-change memory |
23 | Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker 0001 |
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker 0001 |
Resistive Bridging Fault Simulation of Industrial Circuits. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Susan J. Lederman, Roberta L. Klatzky, Christine Tong, Cheryl L. Hamilton |
The perceived roughness of resistive virtual textures: II. effects of varying viscosity with a force-feedback device. |
ACM Trans. Appl. Percept. |
2006 |
DBLP DOI BibTeX RDF |
virtual reality, haptics, Texture perception |
23 | Qing Su, Jamil Kawa, Charles C. Chiang, Yehia Massoud |
Accurate modeling of substrate resistive coupling for floating substrates. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
Analog and mixed signal, floating substrate, substrate modeling, system-on-chip, substrate coupling |
23 | Paul Andries Zegeling |
On Resistive MHD Models with Adaptive Moving Meshes. |
J. Sci. Comput. |
2005 |
DBLP DOI BibTeX RDF |
magnetohydrodynamics, equidistribution principle, monitor functions, adaptive moving mesh method, implicit-explicit time integration, coordinate transformation |
23 | Haixia Gao, Yintang Yang, Xiaohua Ma, Gang Dong |
Testing for Resistive Shorts in FPGA Interconnects. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Phanumas Khumsat, Apisak Worapishet |
Highly-linear, current-feedback resistive source-degenerated MOS transconductor. |
ISCAS (1) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Zhuo Li 0001, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker |
A circuit level fault model for resistive bridges. |
ACM Trans. Design Autom. Electr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
fault models, bridge faults, delay faults |
23 | Kiyotaka Yamamura, Naoya Igarashi, Yasuaki Inoue |
An interval algorithm for finding all solutions of nonlinear resistive circuits. |
ISCAS (3) |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Kiyotaka Yamamura, Takehisa Kitakawa |
Finding all solutions of piecewise-linear resistive circuits using the simplex method. |
ISCAS (3) |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Ravi Wijesiriwardana, Tilak Dias, S. Mukhopadhyay |
Resistive Fibre-Meshed Transducers. |
ISWC |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Lorenzo Repetto, Marco Storace, Mauro Parodi |
A procedure for the piecewise-linear approximation of the resistive part of a cellular nonlinear network. |
ISCAS (3) |
2002 |
DBLP DOI BibTeX RDF |
|
23 | Matthias Klaus, Ad J. van de Goor |
Tests for Resistive and Capacitive Defects in Address Decoders. |
Asian Test Symposium |
2001 |
DBLP DOI BibTeX RDF |
address decoders, test conditions, Defects, opens, dynamic faults, capacitive coupling |
23 | Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang |
Modeling Crosstalk in Resistive VLSI Interconnections. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Jonathan T.-Y. Chang, Edward J. McCluskey |
Detecting resistive shorts for CMOS domino circuits. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
23 | Franck Luthon, George V. Popescu, Alice Caplier |
An MRF Based Motion Detection Algorithm Implemented on Analog Resistive Network. |
ECCV (1) |
1994 |
DBLP DOI BibTeX RDF |
|
23 | Kiyotaka Yamamura, Kazuo Horiuchi |
A globally and quadratically convergent algorithm for solving nonlinear resistive networks. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1990 |
DBLP DOI BibTeX RDF |
|
21 | S. Saqib Khursheed, Urban Ingelsson, Paul M. Rosinger, Bashir M. Al-Hashimi, Peter Harrod |
Bridging Fault Test Method With Adaptive Power Management Awareness. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Lushan Liu, Pradeep Nagaraj, Shambhu J. Upadhyaya, Ramalingam Sridhar |
Defect Analysis and Defect Tolerant Design of Multi-port SRAMs. |
J. Electron. Test. |
2008 |
DBLP DOI BibTeX RDF |
Multi-port SRAMs, Defect/fault tolerant design, Defect analysis |
21 | Shiyan Hu, Zhuo Li 0001, Charles J. Alpert |
A polynomial time approximation scheme for timing constrained minimum cost layer assignment. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Joonsung Bae, Joo-Young Kim 0001, Hoi-Jun Yoo |
A 0.6pJ/b 3Gb/s/ch transceiver in 0.18 µm CMOS for 10mm on-chip interconnects. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
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21 | Michele Favalli, Cecilia Metra |
Interactive presentation: Pulse propagation for the detection of small delay defects. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
21 | José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura 0001 |
Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
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