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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 200 occurrences of 118 keywords
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Results
Found 158 publication records. Showing 158 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
100 | Sreejit Chakravarty |
A characterization of robust test-pairs for stuck-open faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 1(4), pp. 275-286, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
fault simulation, robust tests, stuck-open faults, test generation algorithms |
91 | Zaifu Zhang, Robert D. McLeod, Witold Pedrycz |
A neural network algorithm for testing stuck-open faults in CMOS combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(3), pp. 225-235, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
stuck-open and gate delay faults, Neural networks, test pattern generation |
83 | Mostafa I. H. Abd-El-Barr, Yanging Xu, Carl McCrosky |
Transistor Stuck-Open Fault Detection in Multilevel CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 388-, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Transistor stuck-open fault, multi-level CMOS circuits testing, robust CMOS testing, test pattern generation, two-pattern test |
79 | Hyung Ki Lee, Dong Sam Ha, Kwanghyun Kim |
Test Generation of Stuck-open Faults Using Stuck-at Test Sets in CMOS Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 345-350, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
73 | Rene David, S. Rahal, J. L. Rainard |
Some relationships between delay testing and stuck-open testing in CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 339-343, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
stuck-open, combinational circuits, CMOS, Delay testing, robust test |
60 | Kent L. Einspahr, Sharad C. Seth |
A switch-level test generation system for synchronous and asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(1), pp. 59-73, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
reverse time processing, stuck-open and stuck-at faults, time-frame expansion, sequential circuits, Automatic test generation |
57 | Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò |
Fault simulation of unconventional faults in CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(5), pp. 677-682, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
57 | Michael Nicolaidis |
Shorts in self-checking circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 1(4), pp. 257-273, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
strongly fault-secure circuits, transistor faults, error detecting codes, self-checking circuits, totally self-checking circuits |
54 | Rochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya |
CMOS Stuck-open Fault Detection Using Single Test Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 714-717, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
51 | Michael J. Bryan, Srinivas Devadas, Kurt Keutzer |
Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(6), pp. 800-803, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
51 | Sarma Sastry, Melvin A. Breuer |
Detectability of CMOS stuck-open faults using random and pseudorandom test sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(9), pp. 933-946, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
49 | Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
Detectability of internal bridging faults in scan chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 678-683, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
49 | Feng Shi 0010, Yiorgos Makris |
A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 57-67, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
49 | Janusz A. Starzyk, Dong Liu |
Locating stuck faults in analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 153-156, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
49 | Chien-Mo James Li, Edward J. McCluskey |
Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11), pp. 1748-1759, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou |
On Testability of Multiple Precharged Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 299-304, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
46 | S. Koeppe |
Optimal Layout to Avoid CMOS Stuck-Open Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 829-835, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
44 | Chien-Mo James Li, Edward J. McCluskey |
Diagnosis of Sequence-Dependent Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 187-192, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
44 | Niraj K. Jha |
Multiple Stuck-Open Fault Detection in CMOS Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(4), pp. 426-432, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
multiple stuck-open fault detection, logic testing, CMOS logic circuits, logic circuits, CMOS integrated circuits, integrated logic circuits, two-pattern tests |
42 | Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 394-402, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
42 | Elham K. Moghaddam, Shaahin Hessabi |
An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 619-625, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya |
An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 287-, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
42 | Debesh Kumar Das, Susanta Chakraborty, Bhargab B. Bhattacharya |
New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 303-309, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
42 | Sreejit Chakravarty, S. S. Ravi |
Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3), pp. 329-331, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
42 | Sreejit Chakravarty |
On Synthesizing and Identifying Stuck-Open Testable CMOS Combinational Circuits (extended abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 736-739, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
42 | Beyin Chen, Chung-Len Lee 0001 |
Universal test set generation for CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(3), pp. 313-323, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
functional testing, automatic test generation, CMOS circuits, stuck-open faults, universal test set |
42 | Samy Makar, Edward J. McCluskey |
Checking experiments to test latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 196-201, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
exhaustive functional tests, 2-state latches, minimum-length checking, D-latch, HSpice implementation, transmission gate latch, detectable shorted interconnects, open interconnects, short-to-power faults, short-to-ground faults, pin fault test set, multiplexer-based test set, sequential elements, 2-state state machines, simulation, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, CMOS, circuit analysis computing, CMOS logic circuits, SPICE, stuck open faults, checking experiments, stuck-on faults |
40 | A. B. M. Harun-ur Rashid, Mazuhidul Karim, Syed Mahfuzul Aziz |
Testing complementary pass-transistor logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 5-8, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Hyung Ki Lee, Dong Sam Ha |
SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 660-666, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
39 | Malay Kule, Hafizur Rahaman 0001, Bhargab B. Bhattacharya |
Maximal Defect-Free Component in Nanoscale Crossbar Circuits Amidst Stuck-Open and Stuck-Closed Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 28(11), pp. 1950180:1-1950180:22, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
39 | Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu |
Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12), pp. 3506-3513, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud |
Stuck-open fault diagnosis with stuck-at model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 10th European Test Symposium, ETS 2005, Tallinn, Estonia, May 22-25, 2005, pp. 182-187, 2005, IEEE Computer Society, 0-7695-2341-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud |
A novel stuck-at based method for transistor stuck-open fault diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, pp. 9, 2005, IEEE Computer Society, 0-7803-9038-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
39 | François Darlay |
Detection of multiple stuck-on/stuck-open faults by single faults test sets in MOS transistor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocessing and Microprogramming ![In: Microprocessing and Microprogramming 32(1-5), pp. 783-789, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
39 | V. Kim, T. Chen |
Assessing SRAM test coverage for sub-micron CMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 24-30, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
submicron CMOS technologies, SRAM test coverage assessment, memory fault probability model, memory array, data retention faults, memory fault coverages, memory test algorithms, functional fault class coverages, 0.5 to 1 mum, stuck-at faults, transition faults, stuck-open faults, coupling faults, physical defects, CMOS memory circuits |
39 | Salvador Manich, Michael Nicolaidis, Joan Figueras |
Enhancing realistic fault secureness in parity prediction array arithmetic operators by IDDQ monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 124-129, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
mathematical operators, parity prediction array arithmetic operators, IDDQ current monitoring, fault diagnosis, logic testing, fault detection, stuck-at faults, bridging faults, multiplying circuits, multiplier circuit, arithmetic circuits, logic arrays, stuck-open faults, topological design, SPICE simulation, fault secureness |
39 | Michele Favalli, Marcello Dalpasso, Piero Olivo |
Modeling and simulation of broken connections in CMOS IC's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(7), pp. 808-814, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
37 | Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou |
Testable Designs of Multiple Precharged Domino Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(4), pp. 461-465, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer |
SWiTEST: a switch level test generation system for CMOS combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(5), pp. 625-637, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
35 | Sandip Kundu, Sudhakar M. Reddy |
Robust tests for parity trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 1(3), pp. 191-200, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
linear gates, parity trees, URTS, robust tests, test length |
32 | Piotr R. Sidorowicz, Janusz A. Brzozowski |
A framework for testing special-purpose memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12), pp. 1459-1468, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Yinlei Yu, Jian Xu, Wei-Kang Huang, Fabrizio Lombardi |
Diagnosing Single Faults for Interconnects in SRAM Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 283-286, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
FPGA, testing, fault diagnosis, fault model |
32 | Wenyi Feng, Fred J. Meyer, Fabrizio Lombardi |
Novel Control Pattern Generators for Interconnect Testing with Boundary Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 112-120, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
BIST, boundary scan, Interconnect testing |
32 | Niraj K. Jha |
Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3), pp. 332-336, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
32 | Niraj K. Jha |
Testing for multiple faults in domino-CMOS logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1), pp. 109-116, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
32 | Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz |
A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006, pp. 185-192, 2006, IEEE Computer Society, 0-7695-2566-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | F. Darlay, Bernard Courtois |
Robust tests for stuck-open faults and design for testability of reconvergent fan-out CMOS logic networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 344-349, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
32 | Jhing-Fa Wang, Tah-Yuan Kuo, Jau-Yien Lee |
A New Approach to Derive Robust Sets for Stuck-open Faults in CMOS Combinational Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 726-729, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
32 | Weiwei Mao, Xieting Ling |
Robust test generation algorithm for stuck-open fault in CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 236-242, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
32 | Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis |
An Accumulator-Based BIST Approach for Two-Pattern Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 15(3), pp. 267-278, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
stuck-open fault testing, built-in self test, delay fault testing, two-pattern testing |
32 | Yinan N. Shen, Xiao-Tao Chen, Susumu Horiguchi, Fabrizio Lombardi |
On the multiple fault diagnosis of multistage interconnection networks: the lower bound and the CMOS fault model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 1997 International Conference on Parallel Processing (ICPP '97), August 11-15, 1997, Bloomington, IL, USA, Proceedings, pp. 350-359, 1997, IEEE Computer Society, 0-8186-8108-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
CMOS fault model, multiple fault diagnosis, interconnection networks, fault diagnosis, lower bound, multistage interconnection networks, multistage interconnection networks, CMOS technology, stuck-open faults |
32 | Meng-Lieh Sheu, Chung-Len Lee 0001 |
A programmable multiple-sequence generator for BIST applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 279-285, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
programmable multiple-sequence generator, BIST applications, two-dimension-like feedback shift register, deterministic sequence, pseudo-random vectors, sequence segmentation method, stuck-open fault testing, logic testing, delays, built-in self test, sequential circuits, shift registers, delay fault testing, binary sequences, sequential circuit testing, regular structure, MCM testing |
27 | David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil |
Fault Emulation for Dependability Evaluation of VLSI Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(4), pp. 422-431, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | S. M. Aziz, Joarder Kamruzzaman |
Fault Characterization of Low Capacitance Full-Swing BiCMOS Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 119-, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
25 | Irith Pomeranz, Sudhakar M. Reddy |
Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3), pp. 426-432, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Jin-Fu Li 0001 |
Testing Ternary Content Addressable Memories With Comparison Faults Using March-Like Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5), pp. 919-931, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Jin-Fu Li 0001, Chou-Kun Lin |
Modeling and Testing Comparison Faults for Ternary Content Addressable Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 60-65, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Jun Zhao 0005, V. Swamy Irrinki, Mukesh Puri, Fabrizio Lombardi |
Testing SRAM-Based Content Addressable Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(10), pp. 1054-1063, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
March C algorithm, fault detection, fault modeling, memory testing, Content addressable memory |
25 | Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck |
Deterministic test generation for non-classical faults on the gate level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 244-251, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST |
25 | Jos van Sas, Chay Nowé, Didier Pollet, Francky Catthoor, Paul Vanoostende, Hugo De Man |
Design of a C-testable booth multiplier using a realistic fault model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 5(1), pp. 29-41, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
test generation, design for testability, fault modelling, Array multipliers, C-testability |
25 | Chun-Hung Chen, Jacob A. Abraham |
Generation and evaluation of current and logic tests for switch-level sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(4), pp. 359-366, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
logic tests, test generation, Current tests, I DDQ |
25 | Andres R. Takach, Niraj K. Jha |
Easily testable gate-level and DCVS multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(7), pp. 932-942, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
25 | Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch |
Fault modeling and fault equivalence in CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(3), pp. 229-241, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
test generation, Fault modeling, fault collapsing, fault equivalence |
25 | Dick L. Liu, Edward J. McCluskey |
Design of large embedded CMOS PLAs for built-in self-test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1), pp. 50-59, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
22 | Tsai-Ling Tsai, Jin-Fu Li 0001, Chun-Lung Hsu, Chi-Tien Sun |
Testing stuck-open faults of priority address encoder in content addressable memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 24th Asia and South Pacific Design Automation Conference, ASPDAC 2019, Tokyo, Japan, January 21-24, 2019, pp. 347-351, 2019, ACM, 978-1-4503-6007-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras |
Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 24(5), pp. 1739-1748, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Adit D. Singh |
Cell Aware and stuck-open tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 21th IEEE European Test Symposium, ETS 2016, Amsterdam, Netherlands, May 23-27, 2016, pp. 1-6, 2016, IEEE, 978-1-4673-9659-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Xijiang Lin, Wu-Tung Cheng, Janusz Rajski |
On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 24th IEEE Asian Test Symposium, ATS 2015, Mumbai, India, November 22-25, 2015, pp. 97-102, 2015, IEEE Computer Society, 978-1-4673-9739-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
22 | Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski |
Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 28th International Conference on VLSI Design, VLSID 2015, Bangalore, India, January 3-7, 2015, pp. 399-404, 2015, IEEE Computer Society, 978-1-4799-6658-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
22 | Víctor H. Champac, Julio Vazquez Hernandez, Salvador Barcelo, Roberto Gómez 0001, Chuck Hawkins, Jaume Segura 0001 |
Testing of Stuck-Open Faults in Nanometer Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 29(4), pp. 80-91, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Szu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango Chia-Tso Chao, Shi-Hao Chen, Chih-Mou Tseng, Tsung-Ying Tsai |
Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2010 International Conference on Computer-Aided Design, ICCAD 2010, San Jose, CA, USA, November 7-11, 2010, pp. 155-161, 2010, IEEE, 978-1-4244-8192-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Narendra Devta-Prasanna, Arun Gunda, Sudhakar M. Reddy, Irith Pomeranz |
Multiple fault activation cycle tests for transistor stuck-open faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010, pp. 821, 2010, IEEE Computer Society, 978-1-4244-7206-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Roberto Gómez 0001, Víctor H. Champac, Chuck Hawkins, Jaume Segura 0001 |
A modern look at the CMOS stuck-open fault. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 10th Latin American Test Workshop, LATW 2009, Rio de Janeiro, Brazil, March 2-5, 2009, pp. 1-6, 2009, IEEE, 978-1-4244-4206-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Julio César Vázquez, Víctor H. Champac, Chuck Hawkins, Jaume Segura 0001 |
Stuck-Open Fault Leakage and Testing in Nanometer Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, pp. 315-320, 2009, IEEE Computer Society, 978-0-7695-3598-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya |
An Adaptive BIST Design for Detecting Multiple Stuck-Open Faults in a CMOS Complex Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 57(12), pp. 2838-2845, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu |
Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 17th IEEE Asian Test Symposium, ATS 2008, Sapporo, Japan, November 24-27, 2008, pp. 97-102, 2008, IEEE Computer Society, 978-0-7695-3396-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
Detection of Internal Stuck-open Faults in Scan Chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008, pp. 1-10, 2008, IEEE Computer Society, 978-1-4244-2403-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Afzel Noore |
Improved IDDQ design-for-testability technique to detect CMOS stuck-open faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 4(3), pp. 94-99, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Fadi A. Aloul, Assim Sagahyroon, Bashar Al-Rawi |
Exciting Stuck-Open faults in CMOS Circuits Using ILP Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICCSA ![In: 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), March 8-11, Dubai/Sharjah, UAE, pp. 409-414, 2006, IEEE Computer Society, 1-4244-0211-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Afzel Noore |
Reliable detection of CMOS stuck-open faults due to variable internal delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 2(8), pp. 292-297, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya |
BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Circuits Using Transition Count. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 17(6), pp. 731-737, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana, Rochit Rajsuman |
Testable design of BiCMOS circuits for stuck-open fault detection using single patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 30(8), pp. 855-863, August 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
22 | Kiyoshi Furuya, Susumu Yamazaki, Masayuki Sato |
Stuck-Open Fault Detectabilities of Various TPG Circuits for Use in Two-Pattern Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 78-D(7), pp. 889-894, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP BibTeX RDF |
|
22 | Slawomir Pilarski, Kevin James Wiebe |
Counter-Based Compaction: Delay and Stuck-Open Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(6), pp. 780-791, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
edge counting, ones counting, transition counting, built-in self-test, Aliasing probability, test response compaction |
22 | Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis |
Accumulator-based BIST approach for stuck-open and delay fault testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: 1995 European Design and Test Conference, ED&TC 1995, Paris, France, March 6-9, 1995, pp. 431-437, 1995, IEEE Computer Society, 0-8186-7039-8. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
22 | Hyung Ki Lee, Dong S. Ha 0001 |
An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2(3), pp. 199-207, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Chih-Ang Chen, Sandeep K. Gupta 0001 |
BIST Test Pattern Generators for Stuck-Open and Delay Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDAC-ETC-EUROASIC ![In: EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France, pp. 289-296, 1994, IEEE Computer Society, 0-8186-5410-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Enrico Macii, Qing Xu |
Modeling stuck-open faults in CMOS iterative circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, Kalamazoo, MI, USA, March 5-6, 1993, pp. 14-17, 1993, IEEE, 0-8186-3430-8. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
22 | Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya |
Testable design for BiCMOS stuck-open fault detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 11th IEEE VLSI Test Symposium (VTS'93), 6 Apr 1993-8 Apr 1993, Atlantic City, NJ, USA, pp. 296-302, 1993, IEEE Computer Society, 0-8186-3830-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
22 | Seiji Kajihara, Noriyoshi Itazaki, Kozo Kinoshita |
Stuck-open faults test generation for cmos combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Syst. Comput. Jpn. ![In: Syst. Comput. Jpn. 22(9), pp. 33-42, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
22 | Steven D. Millman, Edward J. McCluskey |
Bridging, Transition, and Stuck-Open Faults in Self-Testing CMOS Checkers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTCS ![In: Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, Montreal, Canada, pp. 154-161, 1991, IEEE Computer Society, 0-8186-2150-8. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
22 | Kuen-Jong Lee, Melvin A. Breuer |
On the charge sharing problem in CMOS stuck-open fault testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1990, Washington, D.C., USA, September 10-14, 1990, pp. 417-426, 1990, IEEE Computer Society, 0-8186-9064-X. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
22 | Jerry M. Soden, R. Keith Treece, Michael R. Taylor, Charles F. Hawkins |
CMOS IC Stuck-Open Fault Electrical Effects and Design Considerations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1989, Washington, D.C., USA, August 1989, pp. 423-430, 1989, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
22 | Henry Cox, Janusz Rajski |
Stuck-Open and Transition Fault Testing in CMOS Complex Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1988, Washington, D.C., USA, September 1988, pp. 688-694, 1988, IEEE Computer Society, 0-8186-0870-6. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
22 | Sudhakar M. Reddy, Madhukar K. Reddy |
Testable Realizations for FET Stuck-Open Faults CMOS Combinational Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(8), pp. 742-754, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
22 | Madhukar K. Reddy, Sudhakar M. Reddy |
Detecting FET Stuck-Open Faults in CMOS Latches and Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 3(5), pp. 17-26, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
22 | Gary L. Craig, Charles R. Kime |
Pseudo-Exhaustive Adjacency Testing: A BIST Approach for Stuck-Open Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1985, Philadelphia, PA, USA, November 1985, pp. 126-139, 1985, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP BibTeX RDF |
|
22 | Yacoub M. El-Ziq, Richard J. Cloutier |
Functional-Level Test Generation for Stuck-Open Faults in CMOS VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1981, Philadelphia, PA, USA, October 1981, pp. 536-546, 1981, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP BibTeX RDF |
|
22 | Yacoub M. El-Ziq |
Automatic test generation for stuck-open faults in CMOS VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 18th Design Automation Conference, DAC '81, Nashville, Tennessee, USA, June 29 - July 1, 1981, pp. 347-354, 1981, ACM/IEEE. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP BibTeX RDF |
|
22 | Jishun Kuang, Yu Wang, Xiaofen Wei, Changnian Zhang |
IDDT ATPG Based on Ambiguous Delay Assignments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 400-405, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
IDDT testing, delay Assignments, stuck-open fault |
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