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Publication years (Num. hits)
1992-1996 (20) 1997-1998 (28) 1999 (24) 2000 (30) 2001 (23) 2002 (33) 2003 (48) 2004 (44) 2005 (60) 2006 (57) 2007 (64) 2008 (68) 2009 (35) 2010-2011 (18) 2012-2013 (24) 2014-2015 (30) 2016 (16) 2017 (18) 2018 (15) 2019 (24) 2020 (15) 2021-2022 (33) 2023 (22) 2024 (5)
Publication types (Num. hits)
article(130) book(8) incollection(4) inproceedings(609) phdthesis(3)
Venues (Conferences, Journals, ...)
DATE(27) CoRR(24) DAC(22) ISCAS(20) VLSI Design(19) DSD(12) ICCAD(12) FPGA(11) MEMOCODE(11) ICCD(10) IEEE Trans. Comput. Aided Des....(10) IEEE Trans. Very Large Scale I...(10) ISQED(10) FMCAD(9) MSE(9) PATMOS(9) More (+10 of total 292)
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Found 754 publication records. Showing 754 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
105Jennifer Gillenwater, Gregory Malecha, Cherif R. Salama, Angela Yun Zhu, Walid Taha, Jim Grundy, John O'Leary Synthesizable high level hardware descriptions: using statically typed two-level languages to guarantee verilog synthesizability. Search on Bibsonomy PEPM The full citation details ... 2008 DBLP  DOI  BibTeX  RDF statically typed two-level languages, synthesizability, verilog elaboration, code generation, hardware description languages
103Cherif R. Salama, Gregory Malecha, Walid Taha, Jim Grundy, John O'Leary Static consistency checking for verilog wire interconnects: using dependent types to check the sanity of verilog descriptions. Search on Bibsonomy PEPM The full citation details ... 2009 DBLP  DOI  BibTeX  RDF static array bounds checking, verilog elaboration, verilog wire width consistency, dependent types, dead code elimination
76Shengchao Qin, Jifeng He 0001, Zongyan Qiu, Naixiao Zhang Hardware/Software Partitioning in Verilog. Search on Bibsonomy ICFEM The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
76Ravi Surepeddi System Verilog for Quality of Results (QoR). Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF System Verilog Design Quality Results
76Shengchao Qin, Wei-Ngan Chin, Jifeng He 0001, Zongyan Qiu From Statecharts to Verilog: a formal approach to hardware/software co-specification. Search on Bibsonomy Innov. Syst. Softw. Eng. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Operational semantics, Statecharts, Hardware/software partitioning, Homomorphism, Verilog, Algebraic laws
66David R. Smith Hardware Synthesis From Encapsulated Verilog Modules. Search on Bibsonomy ASAP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF encapsulated Verilog modules, Verilog writing style, code complexity, automatic inference of control, low level simulation, computational complexity, logic design, inference mechanisms, hardware description languages, hardware synthesis, control points, clock cycle
58Youngsun Han, Seon Kim, Chulwoo Kim Jaguar: A Compiler Infrastructure for Java Reconfigurable Computing. Search on Bibsonomy ICESS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Java, FPGA, compiler, Reconfigurable computing, Verilog
57Lijun Li, Carl Tropper A Multiway Partitioning Algorithm for Parallel Gate Level Verilog Simulation. Search on Bibsonomy ICPP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
57François Pêcheux, Christophe Lallement, Alain Vachoux VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
56Huibiao Zhu, Jifeng He 0001, Jonathan P. Bowen From algebraic semantics to denotational semantics for Verilog. Search on Bibsonomy Innov. Syst. Softw. Eng. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Unifying theories of programming, Denotational semantics, Semantic relating, Verilog, Algebraic semantics
56Sangeetha Sudhakrishnan, Janaki T. Madhavan, E. James Whitehead Jr., Jose Renau Understanding bug fix patterns in verilog. Search on Bibsonomy MSR The full citation details ... 2008 DBLP  DOI  BibTeX  RDF error classification, VHDL, verilog
56Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke Word level predicate abstraction and refinement for verifying RTL verilog. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF SAT, predicate abstraction, verilog
56Shengchao Qin, Wei-Ngan Chin Mapping Statecharts to Verilog for Hardware/Software Co-specification. Search on Bibsonomy FME The full citation details ... 2003 DBLP  DOI  BibTeX  RDF operational semantics, Statecharts, homomorphism, Verilog
56Arash Saifhashemi, Hossein Pedram Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF CHP, PLI, CSP, asynchronous circuits, channel, verilog
48Shu-Hsuan Chou, Chi-Neng Wen, Yan-Ling Liu, Tien-Fu Chen VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
47Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
47Bernhard Peischl, Naveed Riaz, Franz Wotawa Advances in Automated Source-Level Debugging of Verilog Designs. Search on Bibsonomy New Challenges in Applied Intelligence Technologies The full citation details ... 2008 DBLP  DOI  BibTeX  RDF debugging of hardware designs, multiple testcases, model-based diagnosis, software debugging
47Viet-Anh Vu Tran, Shengchao Qin, Wei-Ngan Chin An Automatic Mapping from Statecharts to Verilog. Search on Bibsonomy ICTAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
47Daniel Kroening, Edmund M. Clarke Checking consistency of C and Verilog using predicate abstraction and induction. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
47Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems. Search on Bibsonomy ISPDC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
47Yongjian Li, Jifeng He 0001 Towards a Theory of Bisimulation for a Fragment of Verilog. Search on Bibsonomy IPDPS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
47Huibiao Zhu, Jonathan P. Bowen, Jifeng He 0001 From Operational Semantics to Denotational Semantics for Verilog. Search on Bibsonomy CHARME The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
47David J. Greaves A Verilog to C Compiler. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
47James Jennings, Eric Beuscher Verischemelog: Verilog embedded in Scheme. Search on Bibsonomy DSL The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
47Peter A. Jamieson, Kenneth B. Kent Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only). Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF fpga, verilog hdl
47Ulya R. Karpuzcu Automatic verilog code generation through grammatical evolution. Search on Bibsonomy GECCO Workshops The full citation details ... 2005 DBLP  DOI  BibTeX  RDF automatic code generation, grammatical evolution, verilog
47Zaher S. Andraus, Karem A. Sakallah Automatic abstraction and verification of verilog models. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF UCLID, logic of counter arithmetic with lambda expressions and uninter-preted functions (CLU), abstraction, register transfer level (RTL), verilog
39Karl Meier, Alessandro Forin Hardware Compilation from Machine Code with M2V. Search on Bibsonomy FCCM The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
39Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
39Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models. Search on Bibsonomy DFT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
38Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model
38Geoffrey Ying, Andreas Kuehlmann, Kenneth S. Kundert, Georges G. E. Gielen, Eric Grimme, Martin O'Leary, Sandeep Tare, Warren Wong Guess, solder, measure, repeat: how do I get my mixed-signal chip right? Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Verilog-AMS, analog behavioral modeling, low power verification, mixed-signal verification, VHDL, SPICE, functional verification, Verilog, performance verification
38Clifford E. Cummings SystemVerilog implicit port enhancements accelerate system design & verification. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF *, .name, Verilog EMACS mode, implicit ports, Verilog, instantiation, SystemVerilog
37Ondrej Subrt, Petr Struhovský, Pravoslav Martínek, Jirí Hospodka Virtual Testing Environment for A/D Converters in Verilog-A and Maple Platform. Search on Bibsonomy DDECS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
37Sri Chandra Driving Analog Mixed Signal Verification through Verilog-AMS. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
37Sasidhar Sunkari, Supratik Chakraborty, Vivekananda M. Vedula, Kailasnath Maneparambil A Scalable Symbolic Simulator for Verilog RTL. Search on Bibsonomy MTV The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
37Lijun Li, Carl Tropper A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation. Search on Bibsonomy PADS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
37Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P. Chakrabarti 0001 Synthesis of system verilog assertions. Search on Bibsonomy DATE Designers' Forum The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
37Huibiao Zhu, Jifeng He 0001, Jonathan P. Bowen From Algebraic Semantics to Denotational Semantics for Verilog. Search on Bibsonomy ICECCS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
37Rishiyur S. Nikhil Bluespec System Verilog: efficient, correct RTL from high level specifications. Search on Bibsonomy MEMOCODE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
37Tom Fitzpatric System Verilog for VHDL Users. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
37Frank P. Burns, Delong Shang, Albert Koelmans, Alexandre Yakovlev An Asynchronous Synthesis Toolset Using Verilog. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
37Tun Li, Yang Guo 0003, Sikun Li, Fujiang Ao, Gongjie Li Parallel verilog simulation: architecture and circuit partition. Search on Bibsonomy ASP-DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
37Kai-Hui Chang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo A Temporal Assertion Extension to Verilog. Search on Bibsonomy ATVA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF temporal assertion, verification, PSL
37Tun Li, Yang Guo 0003, Sikun Li Design and Implementation of a Parallel Verilog Simulator: PVSim. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
37Huibiao Zhu, Jonathan P. Bowen, Jifeng He 0001 Soundness, Completeness and Non-redundancy of Operational Semantics for Verilog Based on Denotational Semantics. Search on Bibsonomy ICFEM The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
37Jifeng He 0001 An Algebraic Approach to the VERILOG Programming. Search on Bibsonomy 10th Anniversary Colloquium of UNU/IIST The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
37Kartik Mohanram, C. V. Krishna, Nur A. Touba A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL. Search on Bibsonomy ISCAS (1) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
37Huibiao Zhu, Jonathan P. Bowen, Jifeng He 0001 Deriving Operational Semantics from Denotational Semantics for Verilog. Search on Bibsonomy APSEC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
37Jordan Dimitrov Operational Semantics for Verilog. Search on Bibsonomy APSEC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
37Ivan Blunno, Luciano Lavagno Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL. Search on Bibsonomy ASYNC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
37Gerardo Schneider, Qiwen Xu Towards a Formal Semantics of Verilog Using Duration Calculus. Search on Bibsonomy FTRTFT The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
37Edmund M. Clarke, Daniel Kroening, Karen Yorav Behavioral consistency of C and verilog programs using bounded model checking. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF ANSI-C, equivalence checking, verilog
36Qinlin Chen, Nairen Zhang, Jinpeng Wang, Tian Tan 0001, Chang Xu 0001, Xiaoxing Ma, Yue Li 0006 The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog. Search on Bibsonomy Proc. ACM Program. Lang. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
36Yicong Shao, Chao Wang, Jiajie Huang, Wangzilu Lu, Zhiwen Gu, Longfan Li, Yuhang Zhang, Jian Zhao 0004, Wei Mao, Yongfu Li 0002 V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation. Search on Bibsonomy APCCAS The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
36Moon Gi Seok, Daejin Park, Geun Rae Cho, Tag Gon Kim Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability. Search on Bibsonomy VLSI-SoC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
36Geng Zheng, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov Verilog-AMS-PAM: verilog-AMS integrated with parasitic-aware metamodels for ultra-fast and layout-accurate mixed-signal design exploration. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
36Cherif R. Salama, Gregory Malecha, Walid Taha, Jim Grundy, John O'Leary Static consistency checking for Verilog wire interconnects - Using dependent types to check the sanity of Verilog descriptions. Search on Bibsonomy High. Order Symb. Comput. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
36Mile K. Stojcev S. Sutherland, S. Davidman and P. Flake, System Verilog for Design: A Guide to Using System Verilog for Hardware Design and Modeling Hardcover, Kluwer Academic Publishers, Norwell, MA (2004) ISBN 1-4020-7530-8 pp 374, plus XXVIII, euro 119. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
36Douglas J. Smith VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C. Search on Bibsonomy DAC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF VHDL
29Johannes Jendrsczok, Rolf Hoffmann, Thomas Lenck Generated Horizontal and Vertical Data Parallel GCA Machines for the N-Body Force Calculation. Search on Bibsonomy ARCS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
29John A. Nestor Teaching Computer Organization with HDLs: An Incremental Approach. Search on Bibsonomy MSE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
29Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment. Search on Bibsonomy DFT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
29Lin Yuan, Pushkin R. Pari, Gang Qu 0001 Soft IP Protection: Watermarking HDL Codes. Search on Bibsonomy Information Hiding The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
29Dennis Abts, Steve Scott, David J. Lilja So Many States, So Little Time: Verifying Memory Coherence in the Cray X1. Search on Bibsonomy IPDPS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
29Siavash Bayat Sarmadi, Seyed Ghassem Miremadi, Ghazanfar Asadi, Ali Reza Ejlali Fast Prototyping with Co-operation of Simulation and Emulation. Search on Bibsonomy FPL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
29Guido Arnout C for System Level Design. Search on Bibsonomy DATE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
29Weisheng Zhao, Guillaume Agnus, Vincent Derycke, Arianna Filoramo, Christian Gamrat, Jean-Philippe Bourgoin Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano/CMOS Circuit Design. Search on Bibsonomy NanoNet The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Hybrid Nano/CMOS circuits, OG-CNTFET, Verilog-A, Carbon Nanotube, Functional Modelling
29Gaurav Singh 0006, Sandeep K. Shukla Verifying Compiler Based Refinement of BluespecTM. Search on Bibsonomy SPIN The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Bluespec System Verilog (BSV), Formal Verification, Hardware Designs, SPIN Model Checker
29Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham Improved verification of hardware designs through antecedent conditioned slicing. Search on Bibsonomy Int. J. Softw. Tools Technol. Transf. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF LTL property, Antecedent conditioned slicing, Verilog RTL, Model checking, Program slicing, Hardware description languages, Hardware verification
29Li Shen 0002 VFSim: Concurrent Fault Simulation at Register Transfer Level. Search on Bibsonomy J. Comput. Sci. Technol. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF concurrent fault simulation, fault model, RTL, Verilog, high-level testing, circuit modeling
29Choudhury A. Rahman, Wael M. Badawy A quarter pel full search block motion estimation architecture for H.264/AVC. Search on Bibsonomy ICME The full citation details ... 2005 DBLP  DOI  BibTeX  RDF CIF frame sequence, quarter pel full search, block motion estimation architecture, H.264-AVC encoder, Xilinx Virtex2 FPGA, field programmable gate array, hardware description language, Verilog HDL
29Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations. Search on Bibsonomy CASES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF FPGA, low-power, compiler, SoC, synthesis, pipelining, VHDL, IP, ASIC, high-performance, FSM, Verilog, HDL, levelization
29M. E. Waite, T. J. Reynolds, F. Z. Ieromnimon Parallel Graph Reduction with the PACE Architecture. Search on Bibsonomy PDP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF parallel graph reduction, PACE architecture, graph reduction model, basic replicable node, prototype version, Verilog description, C simulator, parallel programming, graph theory, parallel architectures, virtual machines, distributed memory systems, parallel execution, distributed memory multiprocessor
29Rajesh K. Gupta 0001, Daniel Gajski, Randy Allen, Yatin Trivedi Opportunities and pitfalls in HDL-based system design. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF textual Hardware Description Languages, system designs, VHDL, modeling language, hardware description languages, Verilog, HDLs, hardware systems
29Nam Ling, Rajesh Advani Architecture of a fast motion estimator for MPEG video coding. Search on Bibsonomy ISPAN The full citation details ... 1996 DBLP  DOI  BibTeX  RDF fast motion estimator, MPEG video coding, 2-D log search, MPEG2 video, motion estimation, motion estimator, video coding, systolic arrays, motion vector, Verilog, Synopsys
29H. Dhanesha, K. Falakshahi, Mark Horowitz Array-of-arrays architecture for parallel floating point multiplication. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF array-of-arrays architecture, parallel floating point multiplication, mantissa path, IEEE standard 754, dual-rail domino, HSpice simulation, capacitive load model, 53 bit, 10 ns, 4.3 V, 120 C, parallel architectures, trees, latency, floating point arithmetic, multiplying circuits, CMOS technology, Verilog, synergy, 1 micron
28Matthias Raffelsieper, Mohammad Reza Mousavi 0001, Jan-Willem Roorda, Chris W. H. Strolenberg, Hans Zantema Formal Analysis of Non-determinism in Verilog Cell Library Simulation Models. Search on Bibsonomy FMICS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
28Christian Haufe, Frank Rogin Ad-Hoc Translations to Close Verilog Semantics Gap. Search on Bibsonomy DDECS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
28Flavius Gruian, Mark Westmijze VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture. Search on Bibsonomy SAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF embedded systems, java processor, Bluespec
28Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke VCEGAR: Verilog CounterExample Guided Abstraction Refinement. Search on Bibsonomy TACAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
28Junjun Li, Sopan Joshi, Ryan Barnes, Elyse Rosenbaum Compact modeling of on-chip ESD protection devices using Verilog-A. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
28Ming-Ta Hsieh, Gerald E. Sobelman Modeling and verification of high-speed wired links with Verilog-AMS. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
28Tun Li, Yang Guo 0003, Sikun Li, GongJie Liu Predicate Abstraction of RTL Verilog Descriptions Using Constraint Logic Programming. Search on Bibsonomy ATVA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
28Tun Li, Yang Guo 0003, Sikun Li, Dan Zhu Applying Constraint Logic Programming to Predicate Abstraction of RTL Verilog Descriptions. Search on Bibsonomy MICAI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
28Jun Wang, Carl Tropper Nicarus: A Distributed Verilog Compiler. Search on Bibsonomy ICPP Workshops The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
28Lijun Li, Hai Huang, Carl Tropper DVS: An Object-Oriented Framework for Distributed Verilog Simulation. Search on Bibsonomy PADS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
28Monte Mar, Bert Sullam Modeling and verification of a programmable mixed-signal device using Verilog. Search on Bibsonomy ISCAS (3) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
28Jonathan P. Bowen, Jifeng He 0001, Qiwen Xu An Animatable Operational Semantics of the Verilog Hardware Description Language. Search on Bibsonomy ICFEM The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
28Alexander Glasmacher, Kai Woska Design and Implementation of an XC6216 FPGA Model in Verilog. Search on Bibsonomy FPL The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
28Jonathan P. Bowen Combining Operational Semantics, Logic Programming and Literate Programming in the Specification and Animation of the Verilog Hardware Description Language. Search on Bibsonomy IFM The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
28Gordon J. Pace The Semantics of Verilog Using Transition System Combinators. Search on Bibsonomy FMCAD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
28Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha P. Chandrakasan Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT. Search on Bibsonomy DAC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
28Dominique Borrione, Robert Piloty, Dwight D. Hill, Karl J. Lieberherr, Philip Moorby Three Decades of HDLs: Part II, Conlan Through Verilog. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
19Shreesha Srinath, Katherine Compton Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks. Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF asymmetric multipliers, composable multipliers, multiplier design
19Rajdeep Mukhopadhyay, Subrat Kumar Panda, Pallab Dasgupta, John Gough Instrumenting AMS assertion verification on commercial platforms. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF OVL, SVA, integrated mixed signal design, verification library, simulation, Assertion
19Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti 0001, Vivekananda M. Vedula, K. S. Maneperambil Automatic Constraint Based Test Generation for Behavioral HDL Models. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
19Jonathan Bachrach, Dany Qumsiyeh, Mark M. Tobenkin Hardware Scripting in Gel. Search on Bibsonomy FCCM The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
19Pao-Lung Chen Jitter simulation and measurement of an all-digital clock generator with dynamic frequency counting loop. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
19Sangeetha Sudhakrishnan, Liying Su, Jose Renau Processor Verification with hwBugHunt. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
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