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Publication years (Num. hits)
1988-1994 (16) 1995-1996 (29) 1997 (19) 1998 (42) 1999 (32) 2000 (43) 2001 (54) 2002 (67) 2003 (104) 2004 (113) 2005 (107) 2006 (192) 2007 (164) 2008 (163) 2009 (72) 2010 (36) 2011 (20) 2012-2013 (32) 2014 (15) 2015 (26) 2016 (26) 2017 (29) 2018 (31) 2019 (23) 2020 (22) 2021 (25) 2022 (26) 2023 (17) 2024 (5)
Publication types (Num. hits)
article(243) data(1) incollection(6) inproceedings(1297) phdthesis(3)
Venues (Conferences, Journals, ...)
FPL(192) FPGA(122) FCCM(100) IPDPS(53) ISCAS(40) DSD(37) IEEE Trans. Very Large Scale I...(31) DATE(25) IEEE Trans. Comput. Aided Des....(23) J. VLSI Signal Process.(21) VLSI Design(21) ReConFig(20) CHES(18) ARC(17) DAC(17) ISVLSI(17) More (+10 of total 349)
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Found 1550 publication records. Showing 1550 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
68Jaswinder Pal Singh, Anshul Kumar, Shashi Kumar A multiplier generator for Xilinx FPGAs. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs
53Bernard Laurent, Gilles Bosco, Gabriele Saucier Fast Arithmetic on Xilinx 5200 FPGA. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF (do not appear on the paper): Arithmetic, Xilinx 5200 FPGA, Performance, Place and route
50Anup Kumar Raghavan, Peter Sutton JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs. Search on Bibsonomy IPDPS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF JBits, FPGA design flow, Partial Bitstream, Xilinx Virtex, Partial Reconfiguration
46Parimal Patel Tutorial IND2A: Embedded Systems Design with Xilinx Virtex-5 Series FPGA. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
46Michael A. Shanblatt, Brian Foulds, Patrick Kane, Anna Acevedo A University-based Web Resource Supporting the Xilinx University Program. Search on Bibsonomy MSE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
46Michael A. Shanblatt, Brian Foulds, Patrick Kane A University-Based Support Environment for the Xilinx University Program. Search on Bibsonomy MSE The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
46Madhav Y. Chikodikar, Shridhar Laddha, Ashish Sirasao A Technology Mapper for Xilinx FPGAs. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
39Michael Hübner 0001, Katarina Paulsson, Jürgen Becker 0001 Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores. Search on Bibsonomy IPDPS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39S. W. Song 0002, J. D. Zheng, William B. Gardner Prototyping a Residential Gateway Using Xilinx ISE. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
36Jean-Baptiste Note, Éric Rannaud From the bitstream to the netlist. Search on Bibsonomy FPGA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF bitstream format, FPGA, reverse-engineering
36Roman C. Kordasiewicz, Shahram Shirani On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF JVT, integer DCT, Xilinx Virtex 2-Pro, PPC, FPGA, architecture, H.264/AVC, Quantization, hardware implementations, MPEG4
36Roman C. Kordasiewicz, Shahram Shirani On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF JVT, integer DCT, Xilinx Virtex 2-Pro, PPC, FPGA, architecture, H.264/AVC, quantization, hardware implementations, MPEG4
36Sudip K. Nag, Rob A. Rutenbar Performance-driven simultaneous place and route for island-style FPGAs. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Xilinx 4000-series FPGAs, island-style FPGAs, performance-driven simultaneous placement/routing, place and route tools, FPGAs, field programmable gate arrays, logic CAD, network routing, circuit layout CAD, industrial designs, circuit layout
36Hardy J. Pottinger, Chien-Yuh Lin Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education
35Wissem Chouchene Vers une reconfiguration dynamique partielle parallèle par prise en compte de la régularité des architectures FPGA-Xilinx. (Towards a parallel partial dynamic reconfiguration by taking into account the regularity of FPGA-Xilinx architectures). Search on Bibsonomy 2017   RDF
35Belgacem Babba Synthèse optimisée sur les réseaux programmables de la famille Xilinx. (Optimized Logical Synthesis on Programmable Devices of Xilinx FPGAs). Search on Bibsonomy 1995   RDF
32George Kiokes, Nikolaos K. Uzunoglu Development of a simulation Environment for Vehicular communications, implementation of FEC coding chain in Xilinx FPGA based on IEEE 802.11p standard. Search on Bibsonomy WOWMOM The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
32Leos Kafka Analysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAs. Search on Bibsonomy DDECS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
32Michael Hübner 0001, Lars Braun, Jürgen Becker 0001, Christopher Claus, Walter Stechele Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Rainer Scholz Adapting and Automating XILINX's Partial Reconfiguration Flow for Multiple Module Implementations. Search on Bibsonomy ARC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Patrick Lysaght, Brandon Blodget, Jeff Mason, Jay Young, Brendan Bridgford Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs. Search on Bibsonomy FPL The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
32David Elléouet, Nathalie Julien, Dominique Houzet, Jean-Gabriel Cousin, Eric Martin 0001 Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA. Search on Bibsonomy DSD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
32Abdsamad Benkrid, Khaled Benkrid, Danny Crookes Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs. Search on Bibsonomy FPL The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
32Abdsamad Benkrid, Khaled Benkrid, Danny Crookes A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. Search on Bibsonomy FCCM The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
32Charles E. Stroud, Keshia N. Leach, Thomas A. Slaughter BIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
32Trevor W. Fox, Laurence E. Turner Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA. Search on Bibsonomy FPL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
32Tien-Toan Do, Holger Kropp, Carsten Reuter, Peter Pirsch A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs. Search on Bibsonomy FPL The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
29Xinyu Li, Omar Hammami Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF fpga, multiprocessor, network on chip
29Hui Qin, Tsutomu Sasao, Jon T. Butler Implementation of LPM Address Generators on FPGAs. Search on Bibsonomy ARC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
29Weifeng Xu, Ramshankar Ramanarayanan, Russell Tessier Adaptive Fault Recovery for Networked Reconfigurable Systems. Search on Bibsonomy FCCM The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
29Slo-Li Chu, Chih-Chieh Hsiao, Pin-Hua Chiu Design a Hardware Mechanism to Utilize Multiprocessors on a Uni-processor Operating System. Search on Bibsonomy ICA3PP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Xilinx ML310, FPGA, Linux, Multi-core, Inter-Processor Communication
29Nathan Jachimiec, Fernando Martinez-Vallina, Jafar Saniie CReconfigurable finite field instruction set architecture. Search on Bibsonomy FPGA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF MicroBlaze, embedded development, fast simplex links, galois fields, instruction set extensions, partial reconfiguration, finite field arithmetic, Xilinx, FSL
29Choudhury A. Rahman, Wael M. Badawy A quarter pel full search block motion estimation architecture for H.264/AVC. Search on Bibsonomy ICME The full citation details ... 2005 DBLP  DOI  BibTeX  RDF CIF frame sequence, quarter pel full search, block motion estimation architecture, H.264-AVC encoder, Xilinx Virtex2 FPGA, field programmable gate array, hardware description language, Verilog HDL
29Bruce A. Draper, Walid A. Najjar, A. P. Wim Böhm, Jeffrey Hammes, Robert Rinker, Charlie Ross, Monica Chawathe, José Bins Compiling and Optimizing Image Processing Algorithms for FPGAs. Search on Bibsonomy CAMP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF SA-C, language features, SA-C algorithms, performance numbers, image processing routines, Annapolis Microsystems WildForce board, Xilinx 4036XL FPGAs, FPGAs, VHDL, optimizing compiler, high-level language, data flow graphs, data flow graphs, image processing algorithms
29Abderrahim Doumar, Hideo Ito Testing approach within FPGA-based fault tolerant systems. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase
29Andreas Koch A Comprehensive Prototyping-Platform for Hardware-Software Codesign. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2000 DBLP  DOI  BibTeX  RDF hybrid processor, RTEMS, Virtex, FPGA, prototyping, codesign, SPARC, Xilinx
29Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor FPGA-Based Structures for On-Line FFT and DCT. Search on Bibsonomy FCCM The full citation details ... 1999 DBLP  DOI  BibTeX  RDF FPGA, interconnect, MAC, FFT, signal processing, DCT, online, on-line, distributed arithmetic, bit-serial, xilinx, on-line arithmetic
29John Woodfill, Brian Von Herzen Real-time stereo vision on the PARTS reconfigurable computer. Search on Bibsonomy FCCM The full citation details ... 1997 DBLP  DOI  BibTeX  RDF powerful scalable reconfigurable computer, PARTS engine, real-time stereo vision, Xilinx 4025 FPGAs, partial torus, concurrent SRAM access, standard PCI card, stereo vision algorithm, stereo disparity computation, RISC-equivalent operations, 1 Mbyte, images, SRAMs, stereo image processing, personal computer, workstation, memory access
29R. Maheshwari, S. S. S. P. Rao, E. G. Poonach FPGA Implementation of Median Filter. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF real time median filter, Xilinx XC4010 FPGA chip, field programmable gate arrays, design, algorithm, sliding window
29Adam Postula, David Abramson 0001, Paul Logothetis The Design of a Specialised Processor for the Simulation of Sintering A. Postula. Search on Bibsonomy EUROMICRO The full citation details ... 1996 DBLP  DOI  BibTeX  RDF specialised processor, sintering simulation, metallurgical sintering, commercially available gate array technology, Xilinx FPGA, Aptix FPIC switch technology, FPGAs, Monte-Carlo simulation, special purpose computers
29Nalini K. Ratha, Anil K. Jain 0001, Diane T. Rover FPGA-based high performance page layout segmentation. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Splash 2, page layout segmentation algorithm, FPGA array processor, Xilinx synthesis tool, 5 GHz, 1024 pixel, field programmable gate arrays, image segmentation, parallel processing, text
29Wei-Kang Huang, Xiao-Tao Chen, Fabrizio Lombardi On the diagnosis of programmable interconnect systems: Theory and application. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF field programmable interconnect system, switch grid, FPIS, Xilinx 3000, field programmable gate arrays, FPGA, fault diagnosis, logic testing, diagnosis, integrated circuit interconnections
29Anmol Mathur, Kuang-Chien Chen, C. L. Liu 0001 Re-engineering of timing constrained placements for regular architectures. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Xilinx 3000 FPGA architecture, engineering requirements, regular architectures, timing constrained placements reengineering, FPGAs, field programmable gate arrays, logic CAD, program debugging, systems re-engineering, logic arrays, design flow, gate arrays, design specification, timing performance, design cycle, design debugging
25Alexander Klimm, Oliver Sander, Jürgen Becker 0001 A MicroBlaze specific co-processor for real-time hyperelliptic curve cryptography on Xilinx FPGAs. Search on Bibsonomy IPDPS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
25Gabriel Lizárraga, Roberto Sepúlveda, Oscar Montiel, Oscar Castillo 0001 Modeling and Simulation of the Defuzzification Stage Using Xilinx System Generator and Simulink. Search on Bibsonomy Soft Computing for Hybrid Intelligent Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
25Yazmín Maldonado, Oscar Montiel, Roberto Sepúlveda, Oscar Castillo 0001 Design and Simulation of the Fuzzification Stage through the Xilinx System Generator. Search on Bibsonomy Soft Computing for Hybrid Intelligent Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
25Katarina Paulsson, Michael Hübner 0001, Jürgen Becker 0001 Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
25Mamoun F. Al-Mistarihi Separable implementation of the second order Volterra filter (SOVF) in Xilinx Virtex-E FPGA. Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
25Katarina Paulsson, Michael Hübner 0001, Günther Auer, Michael Dreschmann, Jürgen Becker 0001 Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs. Search on Bibsonomy FPL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
25Ludovico de Souza, John D. Bunton, Duncan Campbell-Wilson, Roger J. Cappallo, Barton B. Kincaid A Radio Astronomy Correlator Optimized for the XILINX VIRTEX-4 SX FPGA. Search on Bibsonomy FPL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
25Filipa Duarte, Stephan Wong Profiling Bluetooth and Linux on the Xilinx Virtex II Pro. Search on Bibsonomy DSD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Go-An Rau, Meng-Xin Guo Multiplierless Realization of Modified Comb Filter by Using Xilinx Spartan FPGAs. Search on Bibsonomy ICICIC (2) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Fabrizio Ferrandi, Giovanna Ferrara, Roberto Palazzo, Vincenzo Rana, Marco D. Santambrogio VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow. Search on Bibsonomy IPDPS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Carsten Bieser, Klaus D. Müller-Glaser Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAs. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Min-Hong Chen, Feng-Cheng Chang, Hsueh-Ming Hang Design and Implementation of an MHP Video and Graphics Subsystem on Xilinx ML310 Platform. Search on Bibsonomy IIH-MSP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Melanie Po-Leen Ooi Hardware Implementation for Face Detection on Xilinx Virtex-II FPGA using the Reversible Component Transformation Colour Space. Search on Bibsonomy DELTA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Peter J. Green, Desmond P. Taylor Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmable Gate Array. Search on Bibsonomy DELTA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Ana Toledo Moreo, Cristina Vicente-Chicote, Juan Suardíaz Muro, Sergio A. Cuenca Xilinx System Generator Based HW Components for Rapid Prototyping of Computer Vision SW/HW Systems. Search on Bibsonomy IbPRIA (1) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF FPGAs, prototyping, Simulink, co-simulation, image processing applications
25Jing Lu, John W. Lockwood IPSec Implementation on Xilinx Virtex-II Pro FPGA and Its Application. Search on Bibsonomy IPDPS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
25Kyrre Glette, Jim Tørresen A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device. Search on Bibsonomy ICES The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
25Abdsamad Benkrid, Khaled Benkrid, Danny Crookes Design and Implementation of Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. Search on Bibsonomy ISVLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25Neil Steiner, Peter M. Athanas An Alternate Wire Database for Xilinx FPGAs. Search on Bibsonomy FCCM The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25J. Chandran, R. Kaluri, Jugdutt Singh, Viktor Öwall, Ronny Veljanovski Xilinx Virtex II Pro Implementation of a Reconfigurable UMTS Digital Channel Filter. Search on Bibsonomy DELTA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25Nicholas Weaver, Yury Markovsky, Yatish Patel, John Wawrzynek Post-placement C-slow retiming for the xilinx virtex FPGA. Search on Bibsonomy FPGA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF C-slow retiming, FPGA CAD, FPGA optimization, retiming
25Jürgen Becker 0001, Michael Hübner 0001, Michael Ullmann Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations. Search on Bibsonomy SBCCI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Virtex FPGA, runtime reconfiguration, power consumption
25Ian Robertson, James Irvine 0001, Patrick Lysaght, David Robinson Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series. Search on Bibsonomy FPGA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF FPGA, verification, dynamic reconfiguration, run-time reconfiguration
25Matthias Dyer, Christian Plessl, Marco Platzner Partially Reconfigurable Cores for Xilinx Virtex. Search on Bibsonomy FPL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
25Xiaoling Sun, Jian Xu, Pieter M. Trouborst Testing Xilinx XC4000 Configurable Logic Blocks with Carry Logic Modules. Search on Bibsonomy DFT The full citation details ... 2001 DBLP  DOI  BibTeX  RDF configurable logic blocks, fault diagnosis, BIST, FPGA testing
25Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. Search on Bibsonomy J. Electron. Test. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF FPGA, test, ATPG, iterative testing
25Steve Guccione Run-Time Reconfiguration at Xilinx. Search on Bibsonomy IPDPS Workshops The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
25Scott Hauck, Zhiyuan Li 0008, Eric J. Schwabe Configuration compression for the Xilinx XC6200 FPGA. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
25Reiner W. Hartenstein, Michael Herz, Frank Gilbert Designing for Xilinx XC6200 FPGAs. Search on Bibsonomy FPL The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
25Scott Hauck, Zhiyuan Li 0008, Eric J. Schwabe Configuration Compression for the Xilinx XC6200 FPGA. Search on Bibsonomy FCCM The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
22Bradley Oraw, Vijay Choudhary, Raja Ayyanar A cosimulation approach to model-based design for complex power electronics and digital control systems. Search on Bibsonomy SCSC The full citation details ... 2007 DBLP  BibTeX  RDF Saber, automatic code generation, Simulink, cosimulation, digital control
22Wim Roelandts Creating a Culture of Innovation. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
22Yu-Pin Chang, Kai-Sheng Yang, Chao-Tang Yu Improved channel codec implementation and performance analysis of OFDM based DAB systems. Search on Bibsonomy IWCMC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF DAB, Eureka-147, OFDM, fading channel, multi-path
22Bo Yang 0010, Nikhil Joshi, Ramesh Karri A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only). Search on Bibsonomy FPGA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
22Roar Lien, Tim Grembowski, Kris Gaj A 1 Gbit/s Partially Unrolled Architecture of Hash Functions SHA-1 and SHA-512. Search on Bibsonomy CT-RSA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
22Seonil Choi, Ronald Scrofano, Viktor K. Prasanna, Ju-wook Jang Energy-efficient signal processing using FPGAs. Search on Bibsonomy FPGA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF energy efficient design techniques, matrix multiplicaiton, FPGA, FFT, performance estimation
22Henry Styles, Wayne Luk Accelerating Radiosity Calculations Using Reconfigurable Platforms. Search on Bibsonomy FCCM The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
22Radhika S. Grover, Weijia Shang, Qiang Li A Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix Multipliers. Search on Bibsonomy FPL The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
22Delon Levi, Steve Guccione GeneticFPGA: Evolving Stable Circuits on Mainstream FPGA Devices. Search on Bibsonomy Evolvable Hardware The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
21Craig P. Steffen, Gildas Genest Nallatech In-Socket FPGA Front-Side Bus Accelerator. Search on Bibsonomy Comput. Sci. Eng. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF Xeon, Field-programmable gate arrays, compiler, reconfigurable, bandwidth, accelerators, Xilinx
21Hesham Abdel Slam Aly Elzouka FPGA Based Implementation of Robust Watermarking System. Search on Bibsonomy ITNG The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Electronic Watermarking, Xilinx FPGA, Embedding Systems, Cryptography
21Jörg Ritter 0002, Paul Molitor A pipelined architecture for partitioned DWT based lossy image compression using FPGA's. Search on Bibsonomy FPGA The full citation details ... 2001 DBLP  DOI  BibTeX  RDF embedded zero tree coding, FPGA, field programmable gate arrays, architecture, wavelet transformation, pipelining, Xilinx, lossy image compression
21Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien On Routability Prediction for Field-Programmable Gate Arrays. Search on Bibsonomy DAC The full citation details ... 1993 DBLP  DOI  BibTeX  RDF XILINX 3000
21Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli Sequential Synthesis for Table Look Up Programmable Gate Arrays. Search on Bibsonomy DAC The full citation details ... 1993 DBLP  DOI  BibTeX  RDF XILINX 3000
17Lucas Leiva, Bruno Constanzo, Martín Vázquez 0001, Juan Manuel Toloza Automatic Fecal Eggs Counting in Ruminants Using Xilinx DPU. Search on Bibsonomy IEEE Embed. Syst. Lett. The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
17Maik Ender, Felix Hahn, Marc Fyrbiak, Amir Moradi 0001, Christof Paar JustSTART: How to Find an RSA Authentication Bypass on Xilinx UltraScale(+) with Fuzzing. Search on Bibsonomy CoRR The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
17Apoorva Banerjee Intelligent Traffic Light Controller using Verilog and Xilinx Spartan-3e. Search on Bibsonomy CoRR The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
17Maik Ender, Felix Hahn, Marc Fyrbiak, Amir Moradi 0001, Christof Paar JustSTART: How to Find an RSA Authentication Bypass on Xilinx UltraScale(+) with Fuzzing. Search on Bibsonomy IACR Trans. Cryptogr. Hardw. Embed. Syst. The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
17Bardia Babaei, Dirk Koch Analysis of Process Variation Within Clock Regions of AMD-Xilinx UltraScale+ Devices. Search on Bibsonomy ARC The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
17Colin Horne, Nial Peters, Matthew Ritchie Classification of LoRa Signals With Real-Time Validation Using the Xilinx Radio Frequency System-on-Chip. Search on Bibsonomy IEEE Access The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
17Ihsan Çiçek, Ahmad Alkhas A new read-write collision-based SRAM PUF implemented on Xilinx FPGAs. Search on Bibsonomy J. Cryptogr. Eng. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
17Salah S. Harb, M. Omair Ahmad, M. N. S. Swamy An efficient image steganographic scheme for a real-time embedded system and its hardware implementation on AMD Xilinx Zynq-7000 APSoC platform. Search on Bibsonomy J. Real Time Image Process. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
17Wafa Gtifa, Anis Sakly Integrating Xilinx FPGA and intelligent techniques for improved precision in 3D brain tumor segmentation in medical imaging. Search on Bibsonomy J. Real Time Image Process. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
17Muhammad Awais, Ali Zahir, Syed Ayaz Ali Shah, Pedro Reviriego, Anees Ullah, Nasim Ullah, Adam Khan, Hazrat Ali Toward Optimal Softcore Carry-aware Approximate Multipliers on Xilinx FPGAs. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
17Jie Lei, José Flich, Enrique S. Quintana-Ortí Toward matrix multiplication for deep learning inference on the Xilinx Versal. Search on Bibsonomy CoRR The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
17Saber Krim, Mohamed Faouzi Mimouni Design and Xilinx Virtex-field-programmable gate array for hardware in the loop of sensorless second-order sliding mode control and model reference adaptive system-sliding mode observer for direct torque control of induction motor drive. Search on Bibsonomy J. Syst. Control. Eng. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
17Jie Lei, José Flich, Enrique S. Quintana-Ortí Toward Matrix Multiplication for Deep Learning Inference on the Xilinx Versal. Search on Bibsonomy PDP The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
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