Search results for "ATPG"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
36	Xiao Liu 0010, Michael S. Hsiao	Constrained ATPG for Broadside Transition Testing.	DFT	2003	DBLP DOI BibTeX RDF
36	Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin	X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture.	ITC	2003	DBLP DOI BibTeX RDF
36	Qingwei Wu, Michael S. Hsiao	Efficient Sequential ATPG Based on Partitioned Finite-State-Machine Traversal.	ITC	2003	DBLP DOI BibTeX RDF
36	Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula	Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines.	VLSI Design	2003	DBLP DOI BibTeX RDF
36	Andreas G. Veneris, Magdy S. Abadir	Design rewiring using ATPG.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
36	Maria K. Michael, Spyros Tragoudas	ATPG tools for delay faults at the functional level.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	functional-level testing, path delay fault simulation (coverage), testing digital circuits, Automatic test pattern generation, Binary Decision Diagrams, delay testing, Boolean Satisfiability, path delay fault testing
36	Jacob A. Abraham, Vivekananda M. Vedula, Daniel G. Saab	Verifying Properties Using Sequential ATPG.	ITC	2002	DBLP DOI BibTeX RDF
36	HyungWon Kim 0001, John P. Hayes	Realization-independent ATPG for designs with unimplemented blocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
36	Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen	Verifying sequential equivalence using ATPG techniques.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF
36	Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal	Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model.	VLSI Design	2001	DBLP DOI BibTeX RDF
36	Silvia Chiusano, Fulvio Corno, Paolo Prinetto	Exploiting Behavioral Information in Gate-Level ATPG.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	genetic algorithms, software testing, simulated annealing, high level synthesis, high level test
36	Vamsi Boppana, Sreeranga P. Rajan, Koichiro Takayama, Masahiro Fujita	Model Checking Based on Sequential ATPG.	CAV	1999	DBLP DOI BibTeX RDF
36	Spyros Tragoudas, Maria K. Michael	ATPG Tools for Delay Faults at the Functional Level.	DATE	1999	DBLP DOI BibTeX RDF
36	Enrique San Millán, Luis Entrena, José Alberto Espejo, Silvia Chiusano, Fulvio Corno	Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization.	DATE	1999	DBLP DOI BibTeX RDF
36	HyungWon Kim 0001, John P. Hayes	High-coverage ATPG for datapath circuits with unimplemented blocks.	ITC	1998	DBLP DOI BibTeX RDF
36	Brion L. Keller, Kevin McCauley, Joseph Swenton, James Youngs	ATPG in practical and non-traditional applications.	ITC	1998	DBLP DOI BibTeX RDF
36	Jaehong Park, M. Ray Mercer	Using Functional Information and Strategy Switching in Sequential ATPG.	ICCD	1996	DBLP DOI BibTeX RDF
36	Pranav Ashar, Sharad Malik	Functional timing analysis using ATPG.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
34	Jiniun Xionq, Yiyu Shi 0001, Vladimir Zolotov, Chandu Visweswariah	Pre-ATPG path selection for near optimal post-ATPG process space coverage.	ICCAD	2009	DBLP DOI BibTeX RDF
33	Waleed K. Al-Assadi, Sindhu Kakarla	Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits.	J. Electron. Test.	2009	DBLP DOI BibTeX RDF	NULL convention logic (NCL), SCOAP, ATPG, Asynchronous circuits, Design for test (DFT)
33	Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	At-speed scan testing, Capture switching activity, X-filling, Test cube, ATPG, Low power testing
33	Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker 0001, Martin Keim, Wu-Tung Cheng	Automatic Test Pattern Generation for Interconnect Open Defects.	VTS	2008	DBLP DOI BibTeX RDF	Interconnect opens, Open-via defects, ATPG
33	Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Hans-Joachim Wunderlich	Test Set Stripping Limiting the Maximum Number of Specified Bits.	DELTA	2008	DBLP DOI BibTeX RDF	Test relaxation, tailored ATPG, test generation
33	Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001	Automatic Test Pattern Generation for Resistive Bridging Faults.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	resistive short defects, ATPG, SAT, bridging faults
33	Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta 0001, Melvin A. Breuer	STAX: statistical crosstalk target set compaction.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF	compaction degree, fault-producing target, pruning power, safe target, statistical static timing analyzer, ATPG
33	Huawei Li 0001, Xiaowei Li 0001	Selection of Crosstalk-Induced Faults in Enhanced Delay Test.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	automatic test pattern generation (ATPG), crosstalk, delay test, critical paths
33	Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas	Low power test generation for path delay faults using stability functions.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	low power, ATPG, path delay faults
33	Peter Wohl, John A. Waicukauski, Sanjay Patel	Scalable selector architecture for x-tolerant deterministic BIST.	DAC	2004	DBLP DOI BibTeX RDF	test-generation (ATPG), test-data compression
33	Takahisa Hiraide, Kwame Osei Boateng, Hideaki Konishi, Koichi Itaya, Michiaki Emori, Hitoshi Yamanaka, Takashi Mochiyama	BIST-Aided Scan Test - A New Method for Test Cost Reduction.	VTS	2003	DBLP DOI BibTeX RDF	ATPG, BIST, fault coverage, ATE, test cost reduction
33	Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin	Efficient compression and application of deterministic patterns in a logic BIST architecture.	DAC	2003	DBLP DOI BibTeX RDF	test-generation (ATPG), self-test (BIST)
33	Nuno Cardoso, Carlos Beltrán Almeida, José Carlos da Silva 0001	A System Level Boundary Scan Controller Board for VME Applications.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	IEEE 1149.1 boundary scan test, board level test and system level test, ATPG
33	Fei Li 0003, Lei He 0001	Maximum current estimation considering power gating.	ISPD	2001	DBLP DOI BibTeX RDF	low-power design, ATPG, power estimation, power gating
33	Jaehong Park, Carl Pixley, Michael Burns, Hyunwoo Cho	An Efficient Logic Equivalence Checker for Industrial Circuits.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	logic checking, ATPG, BDD, formal, combinational, functional verification, equivalence, MET
33	Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero	A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Initialization sequence, Genetic Algorithm, ATPG
33	Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka	A Design for testability Method Using RTL Partitioning.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	line-up structure, internally balanced structure, acyclic structure, partitioning, ATPG, DFT, RTL, isolation, balanced structure
33	Sybille Hellebrand, Birgit Reeb, Steffen Tarnick, Hans-Joachim Wunderlich	Pattern generation for a deterministic BIST scheme.	ICCAD	1995	DBLP DOI BibTeX RDF	ATPG, BIST, Test Synthesis
33	Hyoung B. Min, William A. Rogers	Search strategy switching: A cost model and an analysis of backtracking.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	search strategy switching, ATPG, fault coverage, backtracking
32	Alessandro Fin, Franco Fummi, Graziano Pravadelli	Mixing ATPG and property checking for testing HW/SW interfaces.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	model cecking, ATPG, fault simulation
32	Feng Lu 0002, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna	A signal correlation guided ATPG solver and its applications for solving difficult industrial cases.	DAC	2003	DBLP DOI BibTeX RDF	boolean equivalence checking, ATPG, boolean satisfiability
32	Jing Zeng, Magdy S. Abadir, Jacob A. Abraham	False timing path identification using ATPG techniques and delay-based information.	DAC	2002	DBLP DOI BibTeX RDF	false timing paths, timing slack, ATPG, static timing analysis
32	Junichi Hirase, Shinichi Yoshimura	Faster processing for microprocessor functional ATPG.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	microprocessor functional ATPG, fault coverage improvement, short test pattern, processing speed increase, logic testing, integrated circuit testing, automatic test pattern generation, identification, test pattern generation, functional testing, microprocessor chips, instruction sets, instruction sets, microprocessor tests
32	Malay K. Ganai, Adnan Aziz, Andreas Kuehlmann	Enhancing Simulation with BDDs and ATPG.	DAC	1999	DBLP DOI BibTeX RDF	simulation, formal verification, coverage, ATPG, BDDs
32	Samy Makar, Edward J. McCluskey	ATPG for scan chain latches and flip-flops.	VTS	1997	DBLP DOI BibTeX RDF	bistable element, scan chain circuit, combinational defect detection, algorithm, ATPG, automatic test pattern generation, automatic testing, stuck-at fault, flip-flop, latch, checking experiment
32	Hisashi Kondo, Kwang-Ting Cheng	Driving toward higher IDDQ test quality for sequential circuits: a generalized fault model and its ATPG.	ICCAD	1996	DBLP DOI BibTeX RDF	Selective IDDQ, Pseudo Stuck-at Fault, Sequential ATPG, Vector compaction, Test, Fault model, IDDQ, Leakage Fault
32	Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs	Identification of unsettable flip-flops for partial scan and faster ATPG.	ICCAD	1996	DBLP DOI BibTeX RDF	ISCAS89 circuits, deterministic test generation, difficult-to-set hip-hops, hip-hops, state elements, state justification, transformed circuits, unsettable flip-flops identification, logic testing, ATPG, partial scan, sequential circuits test generation
32	Wilfried Daehn	Load Balancing in a Hybrid ATPG Environment.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	test pattern computation, online estimation, Apollo DN3000, monitoring, logic testing, fault detection, ATPG, automatic testing, fault simulation, fault simulation, automatic test program generation
29	Indradeep Ghosh, Srivaths Ravi 0001	On automatic generation of RTL validation test benches using circuit testing techniques.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	OCCOM, RTL ATPG, RTL testing, path coverage, small validation, toggle coverage, test, testing, generation, ATPG, fault coverage, code coverage, test sets, design validation, coverage metrics, universal test sets, testbench, branch coverage
28	Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski	Timing-Aware Multiple-Delay-Fault Diagnosis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
28	F. S. Chim, T. K. Lam, Y. L. Wu	On improved scheme for digital circuit rewiring and application on further improving FPGA technology mapping.	ASP-DAC	2009	DBLP DOI BibTeX RDF
28	Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	GECOM: Test data compression combined with all unknown response masking.	ASP-DAC	2008	DBLP DOI BibTeX RDF
28	Venkat Satagopan, Bonita Bhaskaran, Waleed K. Al-Assadi, Scott C. Smith, Sindhu Kakarla	DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
28	Sying-Jyan Wang, Yan-Ting Chen, Katherine Shu-Min Li	Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don't-Care Filling.	ISCAS	2007	DBLP DOI BibTeX RDF
28	Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas 0001, Marcelino Bicho Dos Santos, Isabel C. Teixeira, João Paulo Teixeira 0001	Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations.	DFT	2007	DBLP DOI BibTeX RDF
28	Rolf Drechsler, Görschwin Fey	Automatic Test Pattern Generation.	SFM	2006	DBLP DOI BibTeX RDF
28	Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský	Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead.	DFT	2006	DBLP DOI BibTeX RDF
28	Arkan Abdulrahman, Spyros Tragoudas	Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level.	ISQED	2006	DBLP DOI BibTeX RDF
28	Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel	PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits.	ISVLSI	2005	DBLP DOI BibTeX RDF
28	Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards	Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits.	DATE	2004	DBLP DOI BibTeX RDF
28	Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang	Efficient reachability checking using sequential SAT.	ASP-DAC	2004	DBLP DOI BibTeX RDF
28	Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng	SATORI - A Fast Sequential SAT Engine for Circuits.	ICCAD	2003	DBLP DOI BibTeX RDF
28	Magdy S. Abadir, Juhong Zhu	Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs.	VTS	2003	DBLP DOI BibTeX RDF
28	Seongmoon Wang, Sandeep K. Gupta 0001	An automatic test pattern generator for minimizing switching activity during scan testing activity.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
28	Chen Wang 0014, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski	Conflict driven techniques for improving deterministic test pattern generation.	ICCAD	2002	DBLP DOI BibTeX RDF
28	Ajay Khoche, Erik H. Volkerink, Jochen Rivoir, Subhasish Mitra	Test Vector Compression Using EDA-ATE Synergies.	VTS	2002	DBLP DOI BibTeX RDF
28	Li-C. Wang, Magdy S. Abadir, Juhong Zhu	On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults.	ITC	2002	DBLP DOI BibTeX RDF
28	Kenichi Ichino, Takeshi Asakawa, Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara	Hybrid BIST Using Partially Rotational Scan.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
28	Kun-Han Tsai, Janusz Rajski, Malgorzata Marek-Sadowska	Star test: the theory and its applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
28	Ramakrishna Voorakaranam, Abhijit Chatterjee	Test Generation for Accurate Prediction of Analog Specifications.	VTS	2000	DBLP DOI BibTeX RDF
28	Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang	BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF
28	Michael Nicolaidis, Yervant Zorian	Scaling Deeper to Submicron: On-Line Testing to the Rescue.	DATE	1999	DBLP DOI BibTeX RDF
28	Uwe Hübner, Heinrich Theodor Vierhaus, Raul Camposano	Partitioning and analysis of static digital CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
28	H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor Vierhaus	An Efficient Dynamic Parallel Approach to Automatic Test Pattern Generation.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
28	Raghuram S. Tupuri, Jacob A. Abraham	A Novel Hierarchical Test Generation Method for Processors.	VLSI Design	1997	DBLP DOI BibTeX RDF
28	Joseph M. Wolf, Lori M. Kaufman, Robert H. Klenke, James H. Aylor, Ronald Waxman	An analysis of fault partitioned parallel test generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
28	Jaushin Lee, Janak H. Patel	Hierarchical test generation under architectural level functional constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
28	Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska	Fast Boolean optimization by rewiring.	ICCAD	1996	DBLP DOI BibTeX RDF	Boolean logic optimization, boolean optimization, mandatory assignments, Automatic Test Pattern Generation, automatic testing, rewiring
28	M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor	Compact test sets for industrial circuits.	VTS	1995	DBLP DOI BibTeX RDF	compact test sets, industrial circuits, binary logic elements, three-state elements, compaction oriented decision making, heuristics, logic testing, integrated circuit testing, automatic test pattern generation, combinational circuits, automatic testing, multivalued logic circuits, test patterns, bidirectionals, xor gates, or gates, test set size
28	Wolfgang Kunz, Prem R. Menon	Multi-level logic optimization by implication analysis.	ICCAD	1994	DBLP DOI BibTeX RDF
28	Daniel G. Saab, Youssef Saab, Jacob A. Abraham	Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0.	ICCAD	1994	DBLP DOI BibTeX RDF
28	Elisabeth Auth, Michael H. Schulz	A Test-Pattern-Generation Algorithm for Sequential Circuits.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
28	John Giraldi, Michael L. Bushnell	EST: The New Frontier in Automatic Test-Pattern Generation.	DAC	1990	DBLP DOI BibTeX RDF
26	Davide Bresolin, Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Tiziano Villa	The impact of EFSM composition on functional ATPG.	DDECS	2009	DBLP DOI BibTeX RDF
26	Zahi S. Abuhamdeh	A Case Study of ATPG Delay Path Performance Based on Measured Power Rail Integrity.	DFT	2008	DBLP DOI BibTeX RDF
26	Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram	Supply Voltage Noise Aware ATPG for Transition Delay Faults.	VTS	2007	DBLP DOI BibTeX RDF
26	Edward Flanigan, Rajsekhar Adapa, Hailong Cui, Michael Laisne, Spyros Tragoudas, Tsvetomir Petrov	Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture.	VLSI Design	2007	DBLP DOI BibTeX RDF
26	Jorge Campos, Hussain Al-Asaad	Circuit Profiling Mechanisms for High-Level {ATPG}.	MTV	2006	DBLP DOI BibTeX RDF
26	Vlado Vorisek, Bruce Swanson, Kun-Han Tsai, Dhiraj Goswami	Improved Handling of False and Multicycle Paths in ATPG.	VTS	2006	DBLP DOI BibTeX RDF
26	Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Sep Seyedi	Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	diagnostic test generation, VLSI, test generation, fault
26	Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen	Optimal Interconnect ATPG Under a Ground-Bounce Constraint.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	testing, interconnect, Hamming distance, wires, ground bounce
26	Xiao Liu 0010, Michael S. Hsiao	A Novel Transition Fault ATPG That Reduces Yield Loss.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	Hardware I Computing Methodologies
26	Srikanth Venkataraman, Srihari Sivaraj, M. Enamul Amyeen, Sangbong Lee, Ajay Ojha, Ruifeng Guo	An Experimental Study of N-Detect Scan ATPG Patterns on a Processor.	VTS	2004	DBLP DOI BibTeX RDF
26	Xiao Liu 0010, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran	Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	stuck-at vectors, delay testing, transition fault
26	Mahesh A. Iyer	Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation.	ITC	2003	DBLP DOI BibTeX RDF
26	Harald P. E. Vranken, Friedrich Hapke, Soenke Rogge, Domenico Chindamo, Erik H. Volkerink	ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume.	ITC	2003	DBLP DOI BibTeX RDF
26	Armin Biere, Wolfgang Kunz	SAT and ATPG: Boolean engines for formal hardware verification.	ICCAD	2002	DBLP DOI BibTeX RDF
26	Zhigang Jiang, Sandeep K. Gupta 0001	An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes.	ITC	2002	DBLP DOI BibTeX RDF
26	Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri	Design Rewiring Using ATPG.	ITC	2002	DBLP DOI BibTeX RDF
26	Fatih Kocan, Daniel G. Saab	ATPG for combinational circuits on configurable hardware.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
26	Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero	Effective Techniques for High-Level ATPG.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
26	Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero	RT-Level ITC'99 Benchmarks and First ATPG Results.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF