Search results for "yield"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
22	Sanae Seike, Ken Namura, Yukio Ohya, Anis Uzzaman, Shinichi Arima, Dale Meehl, Vivek Chickermane, Azumi Kobayashi, Satoshi Tanaka, Hiroyuki Adachi	Early Life Cycle Yield Learning for Nanometer Devices Using Volume Yield Diagnostics Analysis.	ATS	2006	DBLP DOI BibTeX RDF
22	Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko	Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes.	FPL	2005	DBLP DOI BibTeX RDF
22	Martin Bachmeier	Optimising the Selected Neighbourhood for Yield Mapping by Comparing Plot and Monitor Yield Values.	GI Jahrestagung (1)	2005	DBLP BibTeX RDF
22	Burak Kazaz	Production Planning Under Yield and Demand Uncertainty with Yield-Dependent Cost and Price.	Manuf. Serv. Oper. Manag.	2004	DBLP DOI BibTeX RDF
22	Peter Feldmann, Stephen W. Director	Accurate and Efficient Evaluation of Circuit Yield and Yield Gradients.	ICCAD	1990	DBLP DOI BibTeX RDF
22	Matthias Wesseling, Ulrich Ramacher, Karl Goser	Evaluation and Comparison of Selected WSI Reconfiguration Architectures in Terms of Yield and Yield per Area.	Fehlertolerierende Rechensysteme	1989	DBLP DOI BibTeX RDF
22	G. F. Griffin, G. N. Bastin	Hand-held computer program for field-capture and analysis of herbage yield and composition data using a modified dry-weight-rank and yield estimate method.	Comput. Appl. Biosci.	1988	DBLP DOI BibTeX RDF
22	Jim C. Harden	Comments on "Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I - Sources of failures and yield improvement for VLSI".	Proc. IEEE	1986	DBLP DOI BibTeX RDF
22	Dale E. Hocevar, Michael R. Lightner, Timothy N. Trick	An Extrapolated Yield Approximation Technique for Use in Yield Maximization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1984	DBLP DOI BibTeX RDF
21	Sheng-Hung Wang, Ching-Yi Chen, Cheng-Wen Wu	Fast identification of operating current for toggle MRAM by spiral search.	DAC	2010	DBLP DOI BibTeX RDF	reliability, testing, BIST, characterization, yield enhancement, MRAM
21	Paul Zuber, Petr Dobrovolný, Miguel Miranda	A holistic approach for statistical SRAM analysis.	DAC	2010	DBLP DOI BibTeX RDF	statistical SRAM analysis, process variability, yield prediction
21	Mark Redford, Joseph Sawicki, Prasad Subramaniam, Cliff Hou, Yervant Zorian, Kimon Michaels	DFM: don't care or competitive weapon?	DAC	2009	DBLP DOI BibTeX RDF	RDR, physical verification, sign-off, yield, DFM, design-for-manufacturing, design rules, manufacturing variability, DRC
21	Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl	Considering possible opens in non-tree topology wire delay calculation.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	non-tree topologies, yield, static timing analysis, delay analysis
21	Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy 0001	Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry.	VTS	2008	DBLP DOI BibTeX RDF	Design, yield, failure, SRAM, variation
21	Juan C. Rey, N. S. Nagaraj, Andrew B. Kahng, Fabian Klass, Rob Aitken, Cliff Hou, Luigi Capodieci, Vivek Singh	DFM in practice: hit or hype?	DAC	2008	DBLP DOI BibTeX RDF	critical area analysis, CMP, yield, DFM, OPC, lithography
21	Rei-Fu Huang, Chao-Hsun Chen, Cheng-Wen Wu	Economic Aspects of Memory Built-in Self-Repair.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	BIRA, BIST, yield, overhead, economic models, BISR, redundancy analysis, built-in self-repair
21	Payman Zarkesh-Ha, Ken Doniger	Stochastic interconnect layout sensitivity model.	SLIP	2007	DBLP DOI BibTeX RDF	critical area analysis, layout sensitivity, reliability, stochastic model, yield, design for manufacturability, defect density
21	Shuping Wang, Jianping Li 0001, Shulin Zhang	An Analysis About Market Efficiency in International Petroleum Markets: Evidence from Three Oil Commodities.	International Conference on Computational Science (3)	2007	DBLP DOI BibTeX RDF	International petroleum markets, Futures price spot price, Risk premium, Convenience yield, Cointegration analysis, Market efficiency
21	C. Tabery, M. Craig, Gert Burbach, B. Wagner, S. McGowan, P. Etter, S. Roling, C. Haidinyak, E. Ehrichs	Process Window and Device Variations Evaluation using Array-Based Characterization Circuits.	ISQED	2006	DBLP DOI BibTeX RDF	transistor array, transistor matching, via yield, DOE ROM, novel test circuits, DFM
21		Conference Reports.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	ETS 05, European Test Workshop, Eastern Europe, NATW 05, outlier screening, analog test, TTTC, embedded test, defect-based test, yield management
21	Antonis Papanikolaou, F. Lobmaier, Hua Wang, Miguel Miranda, Francky Catthoor	A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	system-level compensation, process variability, parametric yield
21	Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001	Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations.	ISLPED	2005	DBLP DOI BibTeX RDF	process variation, yield, leakage, dual-Vt, metal gate
21	André K. Nieuwland, Richard P. Kleihorst	IC Cost Reduction by Applying Embedded Fault Tolerance for Soft Errors.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	IC cost, IC production, fault tolerant, redundancy, yield, soft error, on-line test, defect density, SEU, SER, BISR
21	Songqing Zhang, Vineet Wason, Kaustav Banerjee	A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations.	ISLPED	2004	DBLP DOI BibTeX RDF	die-to-die variations, electrothermal couplings, subthreshold leakage power distribution, yield estimation, process variations, within-die variations
21	Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri	Optimal Spare Utilization in Repairable and Reliable Memory Cores.	MTDT	2003	DBLP DOI BibTeX RDF	Embedded Memory Repair and Reliability, Fault-Tolerant Memory Core, System-on-chip, Yield, Built-In-Self-Repair
21	Puneet Gupta 0001, Andrew B. Kahng, Dennis Sylvester, Jie Yang 0010	A cost-driven lithographic correction methodology based on off-the-shelf sizing tools.	DAC	2003	DBLP DOI BibTeX RDF	VLSI manufacturability, yield, OPC, lithography, RET
21	Phillip Christie, José Pineda de Gyvez	Pre-layout prediction of interconnect manufacturability.	SLIP	2001	DBLP DOI BibTeX RDF	design, reliability, interconnect, theory, yield, Rent's rule, critical areas
21	Tadayoshi Horita, Itsuo Takanami	Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	The 1$frac{1}{2}$-track switch model, reconfiguration, yield enhancement, wafer scale integration, mesh-connected processor arrays
21	Frederic Duvivier	Automatic Detection of Spatial Signature on Wafermaps in a High Volume Production.	DFT	1999	DBLP DOI BibTeX RDF	wafermap, spatial signature, automated data collection, yield
21	Tadayoshi Horita, Itsuo Takanami	Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions.	ISPAN	1999	DBLP DOI BibTeX RDF	The 1 1/2-track switch model, wefer scale integration, reconfiguration, yield enhancement, mesh-connected processor arrays
21	Wojciech Maly, Pranab K. Nag, Hans T. Heineken, Jitendra Khare	Design-Manufacturing Interface: Part I - Vision.	DATE	1998	DBLP DOI BibTeX RDF	design, synthesis, manufacturability, yield, design rules
21	Anil Gandhi, Stacy Hall, Ron Harris	An examination of empirically derived within-die local probabilities of failure.	DFT	1997	DBLP DOI BibTeX RDF	empirically derived within-die local probabilities, circuit densities, yield sensitivity, in-line defect inspection equipment, back-end sort data, model free approach, defect review sampling, failure, failure analysis
21	Chen-Yang Pan, Kwang-Ting Cheng	Implicit functional testing for analog circuits.	VTS	1996	DBLP DOI BibTeX RDF	implicit functional testing, linear time-invariant circuits, impulse response samples, pseudo-random technique, production testing time, yield coverages, VLSI, integrated circuit testing, fault coverage, analog circuits, analogue integrated circuits, mixed analogue-digital integrated circuits, transient response
20	Aashish Pant, Puneet Gupta 0001, Mihaela van der Schaar	Software adaptation in quality sensitive applications to deal with hardware variability.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	hardware software interface, adaptation, variability
20	Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen 0001, Hai Li 0001	Tolerating process variations in large, set-associative caches: The buddy cache.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	caches, Processor architectures, fault recovery, memory structures
20	Feng Wang 0004, Xiaoxia Wu, Yuan Xie 0001	Variability-driven module selection with joint design time optimization and post-silicon tuning.	ASP-DAC	2008	DBLP DOI BibTeX RDF
20	Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy 0001	Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
20	Raul Camposano	Adding Manufacturability to the Quality of Results.	ISQED	2006	DBLP DOI BibTeX RDF
20	Ajay Khoche, Peter Muhmenthaler	Session Abstract.	VTS	2006	DBLP DOI BibTeX RDF
19	Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif	Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives.	ISLPED	2010	DBLP DOI BibTeX RDF	sram
19	Somnath Paul, Swarup Bhunia	VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement.	ISLPED	2010	DBLP DOI BibTeX RDF	narrow-width operand, superscalar processor, within-die variation
19	Lavanya Jagan, Ratan Deep Singh, V. Kamakoti 0001, Ananta K. Majhi	Efficient Grouping of Fail Chips for Volume Yield Diagnostics.	VLSI Design	2009	DBLP DOI BibTeX RDF
19	Lin Xie, Azadeh Davoodi	Robust Estimation of Timing Yield With Partial Statistical Information on Process Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
19	Khaled R. Heloue, Farid N. Najm	Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
19	Sawal Ali, Reuben Wilcock, Peter R. Wilson, Andrew D. Brown	A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits.	DATE	2008	DBLP DOI BibTeX RDF
19	Georges G. E. Gielen, Pieter De Wit, Elie Maricau, Johan Loeckx, Javier Martín-Martínez, Ben Kaczer, Guido Groeseneken, Rosana Rodríguez, Montserrat Nafría	Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies.	DATE	2008	DBLP DOI BibTeX RDF
19	Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah	Incremental Criticality and Yield Gradients.	DATE	2008	DBLP DOI BibTeX RDF
19	Chenjie Gu, Jaijeet S. Roychowdhury	An efficient, fully nonlinear, variability-aware non-monte-carlo yield estimation procedure with applications to SRAM cells and ring oscillators.	ASP-DAC	2008	DBLP DOI BibTeX RDF
19	Baker Mohammad, Stephen Bijansky, Adnan Aziz, Jacob A. Abraham	Adaptive SRAM memory for low power and high yield.	ICCD	2008	DBLP DOI BibTeX RDF
19	Murari Mani, Anirudh Devgan, Michael Orshansky, Yaping Zhan	A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
19	Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen	Multilevel Full-Chip Routing With Testability and Yield Enhancement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
19	Ming-e Jing, Yue Hao, Dian Zhou, Xuan Zeng 0001	A Novel Optimization Method for Parametric Yield: Uniform Design Mapping Distance Algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
19	Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang	A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits.	PATMOS	2007	DBLP DOI BibTeX RDF
19	Ruiming Chen, Hai Zhou 0001	Fast Buffer Insertion for Yield Optimization Under Process Variations.	ASP-DAC	2007	DBLP DOI BibTeX RDF
19	Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha	Vt balancing and device sizing towards high yield of sub-threshold static logic gates.	ISLPED	2007	DBLP DOI BibTeX RDF	variability, sub-threshold
19	Somnath Paul, Swarup Bhunia	Memory based computation using embedded cache for processor yield and reliability improvement.	ICCD	2007	DBLP DOI BibTeX RDF
19	Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia	Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield.	IOLTS	2007	DBLP DOI BibTeX RDF
19	Daniel Mazor, Michael L. Bushnell, David J. Mulligan, Richard J. Blaikie	Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors.	VLSI Design	2007	DBLP DOI BibTeX RDF
19	Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril	Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations.	VLSI Design	2007	DBLP DOI BibTeX RDF
19	Debjit Sinha, Narendra V. Shenoy, Hai Zhou 0001	Statistical Timing Yield Optimization by Gate Sizing.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
19	Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh	Combining Negative Binomial and Weibull Distributions for Yield and Reliability Prediction.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	fault tolerance, reliability, testing
19	Ting Li 0022, Eric van Heck, Peter Vervest	Dynamic Pricing Strategies for Yield Improvement with Smart Card Adoption in the Dutch Travel Industry.	ENTER	2006	DBLP DOI BibTeX RDF
19	Kuang-Yao Lee, Ting-Chi Wang	Post-routing redundant via insertion for yield/reliability improvement.	ASP-DAC	2006	DBLP DOI BibTeX RDF
19	Kazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera	A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime.	FPL	2006	DBLP DOI BibTeX RDF
19	Yufa Xu, Guochu Chen, Jinshou Yu	The Kalman Particle Swarm Optimization Algorithm and Its Application in Soft-Sensor of Acrylonitrile Yield.	ICNC (2)	2006	DBLP DOI BibTeX RDF
19	Alberto Fazzi, Luca Magagni, Mario de Dominicis, Paolo Zoffoli, Roberto Canegallo, Pier Luigi Rolandi, Alberto L. Sangiovanni-Vincentelli, Roberto Guerrieri	Yield prediction for 3D capacitive interconnections.	ICCAD	2006	DBLP DOI BibTeX RDF
19	Wei-Lun Hung, Xiaoxia Wu, Yuan Xie 0001	Guaranteeing performance yield in high-level synthesis.	ICCAD	2006	DBLP DOI BibTeX RDF
19	Lukasz Zielinski, Bartlomiej Puchalski, Jerzy Rutkowski	Yield enhancement by means of evolutionary computation techniques.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Jeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Müller 0003, Sven Peyer, Christian Schulte 0002	Yield Improvement by Local Wiring Redundancy.	ISQED	2006	DBLP DOI BibTeX RDF
19	Arnaud Epinat, N. Vijayaraghavan, Matthieu Sautier, Olivier Callen, Sebastien Fabre, Ryan Ross, Paul Simon, Robin Wilson	Yield Enhancement Methodology for CMOS Standard Cells.	ISQED	2006	DBLP DOI BibTeX RDF
19	Takumi Uezono, Kenichi Okada, Kazuya Masu	Via Distribution Model for Yield Estimation.	ISQED	2006	DBLP DOI BibTeX RDF
19	Rasit Onur Topaloglu	Early, Accurate and Fast Yield Estimation through Monte Carlo-Alternative Probabilistic Behavioral Analog System Simulations.	VTS	2006	DBLP DOI BibTeX RDF
19	Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti	A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
19	Rajeev R. Rao, David T. Blaauw, Dennis Sylvester, Anirudh Devgan	Modeling and Analysis of Parametric Yield under Power and Performance Constraints.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	G.4.g Reliability and robustness, B.7 Integrated Circuits, Fault-Tolerance
19	Fei Su, Krishnendu Chakrabarty, Vamsee K. Pamula	Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration.	DATE	2005	DBLP DOI BibTeX RDF
19	Gyu-Sik Han, Daewon Lee, Jaewook Lee 0001	Estimating the Yield Curve Using Calibrated Radial Basis Function Networks.	ISNN (2)	2005	DBLP DOI BibTeX RDF
19	Gang Liu, Xuehong Yang, Minzan Li	An Artificial Neural Network Model for Crop Yield Responding to Soil Parameters.	ISNN (3)	2005	DBLP DOI BibTeX RDF
19	Andrew B. Kahng, Bao Liu 0001, Ion I. Mandoiu	Nontree routing for reliability and yield improvement [IC layout].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
19	Naran Sirisantana, Bipul Chandra Paul, Kaushik Roy 0001	Enhancing Yield at the End of the Technology Roadmap.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
19	Davide Appello, Alessandra Fudoli, Katia Giarda, Vincenzo Tancorre, Emil Gizdarski, Ben Mathew	Understanding Yield Losses in Logic Circuits.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
19	Amit Agarwal 0001, Bipul Chandra Paul, Kaushik Roy 0001	A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies.	IOLTS	2004	DBLP DOI BibTeX RDF
19	Christian Gotzel, Karl Inderfurth	Approximate Policies for Hybrid Production and Rework Systems with Stochastic Demand and Yield.	OR	2004	DBLP DOI BibTeX RDF
19	Phil Nigh	Redefining ATE: "Data Collection Engines that Drive Yield Learning and Process Optimization".	ITC	2004	DBLP DOI BibTeX RDF
19	Jitendra Khare	Memory Yield Improvement - SoC Design Perspective.	ITC	2004	DBLP DOI BibTeX RDF
19	Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy 0001	Novel sizing algorithm for yield improvement under process variation in nanometer technology.	DAC	2004	DBLP DOI BibTeX RDF	Performance, Design, Algorithms, Reliability
19	Thomas S. Barnett, Adit D. Singh, Victor P. Nelson	Extending integrated-circuit yield-models to estimate early-life reliability.	IEEE Trans. Reliab.	2003	DBLP DOI BibTeX RDF
19	Yervant Zorian, Samvel K. Shoukourian	Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
19	Doru P. Munteanu, Víctor Suñé, Rosa Rodríguez-Montañés, Juan A. Carrasco	A Combinatorial Method for the Evaluation of Yield of Fault-Tolerant Systems-on-Chip.	DSN	2003	DBLP DOI BibTeX RDF
19	Kumaraswamy Ponnambalam, Abbas Seifi, Jirí Vlach	Yield optimization with correlated design parameters and non-symmetrical marginal distributions.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
19	L. Forli, Jean-Michel Portal, Didier Née, Bertrand Borot	Infrastructure IP for Back-End Yield Improvement.	ITC	2003	DBLP DOI BibTeX RDF
19	Thomas S. Barnett, Adit D. Singh	Relating Yield Models to Burn-In Fall-Out in Time.	ITC	2003	DBLP DOI BibTeX RDF
19	Andrew B. Kahng, Bao Liu 0001, Ion I. Mandoiu	Non-tree routing for reliability and yield improvement.	ICCAD	2002	DBLP DOI BibTeX RDF
19	Yonghua Cong, Randall L. Geiger	Formulation of INL and DNL yield estimation in current-steering D/A converters.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
19	Giovanni Spagnuolo	An interval arithmetic-based yield evaluation in circuit tolerance design.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
19	Yu Lin, Randall L. Geiger	Resistors layout for enhancing yield of R-2R DACs.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
19	Thomas S. Barnett, Adit D. Singh, Matt Grady, Kathleen G. Purdy	Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction.	VTS	2002	DBLP DOI BibTeX RDF
19	Zhigang Jiang, Sandeep K. Gupta 0001	An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes.	ITC	2002	DBLP DOI BibTeX RDF
19	Yervant Zorian	Embedded Memory Test and Repair: Infrastructure IP for SOC Yield.	ITC	2002	DBLP DOI BibTeX RDF
19	Mark Craig, Alvin Jee, Prashant Maniar	An Integrated Approach to Yield Loss Characterization.	ITC	2002	DBLP DOI BibTeX RDF
19	Junichi Hirase	Yield Increase of VLSI after Redundancy-Repairing.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF