|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 6138 occurrences of 3479 keywords
|
|
|
Results
Found 8586 publication records. Showing 8586 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
22 | Sanae Seike, Ken Namura, Yukio Ohya, Anis Uzzaman, Shinichi Arima, Dale Meehl, Vivek Chickermane, Azumi Kobayashi, Satoshi Tanaka, Hiroyuki Adachi |
Early Life Cycle Yield Learning for Nanometer Devices Using Volume Yield Diagnostics Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 15th Asian Test Symposium, ATS 2006, Fukuoka, Japan, November 20-23, 2006, pp. 415-420, 2006, IEEE, 0-7695-2628-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko |
Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005, pp. 409-414, 2005, IEEE, 0-7803-9362-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Martin Bachmeier |
Optimising the Selected Neighbourhood for Yield Mapping by Comparing Plot and Monitor Yield Values. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GI Jahrestagung (1) ![In: 35. Jahrestagung der Gesellschaft für Informatik, Informatik LIVE!, INFORMATIK 2005, Bonn, Germany, September 19-22, 2005, Band 1, pp. 360-364, 2005, GI, 3-88579-396-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
22 | Burak Kazaz |
Production Planning Under Yield and Demand Uncertainty with Yield-Dependent Cost and Price. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Manuf. Serv. Oper. Manag. ![In: Manuf. Serv. Oper. Manag. 6(3), pp. 209-224, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Peter Feldmann, Stephen W. Director |
Accurate and Efficient Evaluation of Circuit Yield and Yield Gradients. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1990, Santa Clara, CA, USA, November 11-15, 1990. Digest of Technical Papers, pp. 120-123, 1990, IEEE Computer Society, 0-8186-2055-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
22 | Matthias Wesseling, Ulrich Ramacher, Karl Goser |
Evaluation and Comparison of Selected WSI Reconfiguration Architectures in Terms of Yield and Yield per Area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Fehlertolerierende Rechensysteme ![In: Fehlertolerierende Rechensysteme / Fault-Tolerant Computing Systems, Automatisierungssysteme, Methoden, Anwendungen / Automation Systems, Methods, Applications; 4. Internationale GI/ITG/GMA-Fachtagung, Baden-Baden, Deutschland, 20.-22. September 1989, Proceedings, pp. 74-84, 1989, Springer, 3-540-51565-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
22 | G. F. Griffin, G. N. Bastin |
Hand-held computer program for field-capture and analysis of herbage yield and composition data using a modified dry-weight-rank and yield estimate method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Appl. Biosci. ![In: Comput. Appl. Biosci. 4(2), pp. 239-242, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
22 | Jim C. Harden |
Comments on "Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I - Sources of failures and yield improvement for VLSI". ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 74(3), pp. 515-516, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
22 | Dale E. Hocevar, Michael R. Lightner, Timothy N. Trick |
An Extrapolated Yield Approximation Technique for Use in Yield Maximization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(4), pp. 279-287, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
|
21 | Sheng-Hung Wang, Ching-Yi Chen, Cheng-Wen Wu |
Fast identification of operating current for toggle MRAM by spiral search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 923-928, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
reliability, testing, BIST, characterization, yield enhancement, MRAM |
21 | Paul Zuber, Petr Dobrovolný, Miguel Miranda |
A holistic approach for statistical SRAM analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 717-722, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
statistical SRAM analysis, process variability, yield prediction |
21 | Mark Redford, Joseph Sawicki, Prasad Subramaniam, Cliff Hou, Yervant Zorian, Kimon Michaels |
DFM: don't care or competitive weapon? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 296-297, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
RDR, physical verification, sign-off, yield, DFM, design-for-manufacturing, design rules, manufacturing variability, DRC |
21 | Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl |
Considering possible opens in non-tree topology wire delay calculation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 17-22, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
non-tree topologies, yield, static timing analysis, delay analysis |
21 | Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy 0001 |
Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 101-106, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Design, yield, failure, SRAM, variation |
21 | Juan C. Rey, N. S. Nagaraj, Andrew B. Kahng, Fabian Klass, Rob Aitken, Cliff Hou, Luigi Capodieci, Vivek Singh |
DFM in practice: hit or hype? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 898-899, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
critical area analysis, CMP, yield, DFM, OPC, lithography |
21 | Rei-Fu Huang, Chao-Hsun Chen, Cheng-Wen Wu |
Economic Aspects of Memory Built-in Self-Repair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(2), pp. 164-172, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
BIRA, BIST, yield, overhead, economic models, BISR, redundancy analysis, built-in self-repair |
21 | Payman Zarkesh-Ha, Ken Doniger |
Stochastic interconnect layout sensitivity model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 9-14, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
critical area analysis, layout sensitivity, reliability, stochastic model, yield, design for manufacturability, defect density |
21 | Shuping Wang, Jianping Li 0001, Shulin Zhang |
An Analysis About Market Efficiency in International Petroleum Markets: Evidence from Three Oil Commodities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science (3) ![In: Computational Science - ICCS 2007, 7th International Conference, Beijing, China, May 27 - 30, 2007, Proceedings, Part III, pp. 992-999, 2007, Springer, 978-3-540-72587-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
International petroleum markets, Futures price spot price, Risk premium, Convenience yield, Cointegration analysis, Market efficiency |
21 | C. Tabery, M. Craig, Gert Burbach, B. Wagner, S. McGowan, P. Etter, S. Roling, C. Haidinyak, E. Ehrichs |
Process Window and Device Variations Evaluation using Array-Based Characterization Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 260-265, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
transistor array, transistor matching, via yield, DOE ROM, novel test circuits, DFM |
21 | |
Conference Reports. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(5), pp. 480-481, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
ETS 05, European Test Workshop, Eastern Europe, NATW 05, outlier screening, analog test, TTTC, embedded test, defect-based test, yield management |
21 | Antonis Papanikolaou, F. Lobmaier, Hua Wang, Miguel Miranda, Francky Catthoor |
A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 117-122, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
system-level compensation, process variability, parametric yield |
21 | Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001 |
Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 14-19, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
process variation, yield, leakage, dual-Vt, metal gate |
21 | André K. Nieuwland, Richard P. Kleihorst |
IC Cost Reduction by Applying Embedded Fault Tolerance for Soft Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(5), pp. 533-542, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
IC cost, IC production, fault tolerant, redundancy, yield, soft error, on-line test, defect density, SEU, SER, BISR |
21 | Songqing Zhang, Vineet Wason, Kaustav Banerjee |
A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 156-161, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
die-to-die variations, electrothermal couplings, subthreshold leakage power distribution, yield estimation, process variations, within-die variations |
21 | Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri |
Optimal Spare Utilization in Repairable and Reliable Memory Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 64-71, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Embedded Memory Repair and Reliability, Fault-Tolerant Memory Core, System-on-chip, Yield, Built-In-Self-Repair |
21 | Puneet Gupta 0001, Andrew B. Kahng, Dennis Sylvester, Jie Yang 0010 |
A cost-driven lithographic correction methodology based on off-the-shelf sizing tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 16-21, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
VLSI manufacturability, yield, OPC, lithography, RET |
21 | Phillip Christie, José Pineda de Gyvez |
Pre-layout prediction of interconnect manufacturability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 167-173, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
design, reliability, interconnect, theory, yield, Rent's rule, critical areas |
21 | Tadayoshi Horita, Itsuo Takanami |
Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(6), pp. 542-552, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
The 1$frac{1}{2}$-track switch model, reconfiguration, yield enhancement, wafer scale integration, mesh-connected processor arrays |
21 | Frederic Duvivier |
Automatic Detection of Spatial Signature on Wafermaps in a High Volume Production. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 61-, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
wafermap, spatial signature, automated data collection, yield |
21 | Tadayoshi Horita, Itsuo Takanami |
Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1999 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '99), 23-25 June 1999, Fremantle, Australia, pp. 135-137, 1999, IEEE Computer Society, 0-7695-0231-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
The 1 1/2-track switch model, wefer scale integration, reconfiguration, yield enhancement, mesh-connected processor arrays |
21 | Wojciech Maly, Pranab K. Nag, Hans T. Heineken, Jitendra Khare |
Design-Manufacturing Interface: Part I - Vision. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 550-556, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
design, synthesis, manufacturability, yield, design rules |
21 | Anil Gandhi, Stacy Hall, Ron Harris |
An examination of empirically derived within-die local probabilities of failure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 53-61, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
empirically derived within-die local probabilities, circuit densities, yield sensitivity, in-line defect inspection equipment, back-end sort data, model free approach, defect review sampling, failure, failure analysis |
21 | Chen-Yang Pan, Kwang-Ting Cheng |
Implicit functional testing for analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 489-494, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
implicit functional testing, linear time-invariant circuits, impulse response samples, pseudo-random technique, production testing time, yield coverages, VLSI, integrated circuit testing, fault coverage, analog circuits, analogue integrated circuits, mixed analogue-digital integrated circuits, transient response |
20 | Aashish Pant, Puneet Gupta 0001, Mihaela van der Schaar |
Software adaptation in quality sensitive applications to deal with hardware variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 85-90, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
hardware software interface, adaptation, variability |
20 | Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen 0001, Hai Li 0001 |
Tolerating process variations in large, set-associative caches: The buddy cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 6(2), pp. 8:1-8:34, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
caches, Processor architectures, fault recovery, memory structures |
20 | Feng Wang 0004, Xiaoxia Wu, Yuan Xie 0001 |
Variability-driven module selection with joint design time optimization and post-silicon tuning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 2-9, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy 0001 |
Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2427-2436, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Raul Camposano |
Adding Manufacturability to the Quality of Results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 511, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Ajay Khoche, Peter Muhmenthaler |
Session Abstract. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 288-289, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif |
Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 337-342, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
sram |
19 | Somnath Paul, Swarup Bhunia |
VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 37-42, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
narrow-width operand, superscalar processor, within-die variation |
19 | Lavanya Jagan, Ratan Deep Singh, V. Kamakoti 0001, Ananta K. Majhi |
Efficient Grouping of Fail Chips for Volume Yield Diagnostics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 97-102, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Lin Xie, Azadeh Davoodi |
Robust Estimation of Timing Yield With Partial Statistical Information on Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12), pp. 2264-2276, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Khaled R. Heloue, Farid N. Najm |
Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10), pp. 1826-1839, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Sawal Ali, Reuben Wilcock, Peter R. Wilson, Andrew D. Brown |
A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 152-157, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Georges G. E. Gielen, Pieter De Wit, Elie Maricau, Johan Loeckx, Javier Martín-Martínez, Ben Kaczer, Guido Groeseneken, Rosana Rodríguez, Montserrat Nafría |
Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1322-1327, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah |
Incremental Criticality and Yield Gradients. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1130-1135, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Chenjie Gu, Jaijeet S. Roychowdhury |
An efficient, fully nonlinear, variability-aware non-monte-carlo yield estimation procedure with applications to SRAM cells and ring oscillators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 754-761, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Baker Mohammad, Stephen Bijansky, Adnan Aziz, Jacob A. Abraham |
Adaptive SRAM memory for low power and high yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 176-181, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Murari Mani, Anirudh Devgan, Michael Orshansky, Yaping Zhan |
A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10), pp. 1790-1802, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen |
Multilevel Full-Chip Routing With Testability and Yield Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9), pp. 1625-1636, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Ming-e Jing, Yue Hao, Dian Zhou, Xuan Zeng 0001 |
A Novel Optimization Method for Parametric Yield: Uniform Design Mapping Distance Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6), pp. 1149-1155, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang |
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 148-159, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Ruiming Chen, Hai Zhou 0001 |
Fast Buffer Insertion for Yield Optimization Under Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 19-24, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha |
Vt balancing and device sizing towards high yield of sub-threshold static logic gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 355-358, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
variability, sub-threshold |
19 | Somnath Paul, Swarup Bhunia |
Memory based computation using embedded cache for processor yield and reliability improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 341-346, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia |
Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 29-36, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Daniel Mazor, Michael L. Bushnell, David J. Mulligan, Richard J. Blaikie |
Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 657-664, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril |
Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 711-716, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Debjit Sinha, Narendra V. Shenoy, Hai Zhou 0001 |
Statistical Timing Yield Optimization by Gate Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(10), pp. 1140-1146, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh |
Combining Negative Binomial and Weibull Distributions for Yield and Reliability Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(2), pp. 110-116, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
fault tolerance, reliability, testing |
19 | Ting Li 0022, Eric van Heck, Peter Vervest |
Dynamic Pricing Strategies for Yield Improvement with Smart Card Adoption in the Dutch Travel Industry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ENTER ![In: Information and Communication Technologies in Tourism, ENTER 2006, Proceedings of the International Conference in Lausanne, Switzerland, 2006, pp. 234, 2006, Springer, 978-3-211-30987-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Kuang-Yao Lee, Ting-Chi Wang |
Post-routing redundant via insertion for yield/reliability improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 303-308, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Kazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera |
A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Yufa Xu, Guochu Chen, Jinshou Yu |
The Kalman Particle Swarm Optimization Algorithm and Its Application in Soft-Sensor of Acrylonitrile Yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNC (2) ![In: Advances in Natural Computation, Second International Conference, ICNC 2006, Xi'an, China, September 24-28, 2006. Proceedings, Part II, pp. 176-179, 2006, Springer, 3-540-45907-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Alberto Fazzi, Luca Magagni, Mario de Dominicis, Paolo Zoffoli, Roberto Canegallo, Pier Luigi Rolandi, Alberto L. Sangiovanni-Vincentelli, Roberto Guerrieri |
Yield prediction for 3D capacitive interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 809-814, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Wei-Lun Hung, Xiaoxia Wu, Yuan Xie 0001 |
Guaranteeing performance yield in high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 303-309, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Lukasz Zielinski, Bartlomiej Puchalski, Jerzy Rutkowski |
Yield enhancement by means of evolutionary computation techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Jeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Müller 0003, Sven Peyer, Christian Schulte 0002 |
Yield Improvement by Local Wiring Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 473-478, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Arnaud Epinat, N. Vijayaraghavan, Matthieu Sautier, Olivier Callen, Sebastien Fabre, Ryan Ross, Paul Simon, Robin Wilson |
Yield Enhancement Methodology for CMOS Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 497-502, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Takumi Uezono, Kenichi Okada, Kazuya Masu |
Via Distribution Model for Yield Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 479-484, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Rasit Onur Topaloglu |
Early, Accurate and Fast Yield Estimation through Monte Carlo-Alternative Probabilistic Behavioral Analog System Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 136-142, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti |
A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(5), pp. 630-638, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Rajeev R. Rao, David T. Blaauw, Dennis Sylvester, Anirudh Devgan |
Modeling and Analysis of Parametric Yield under Power and Performance Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(4), pp. 376-385, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
G.4.g Reliability and robustness, B.7 Integrated Circuits, Fault-Tolerance |
19 | Fei Su, Krishnendu Chakrabarty, Vamsee K. Pamula |
Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 1196-1201, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Gyu-Sik Han, Daewon Lee, Jaewook Lee 0001 |
Estimating the Yield Curve Using Calibrated Radial Basis Function Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (2) ![In: Advances in Neural Networks - ISNN 2005, Second International Symposium on Neural Networks, Chongqing, China, May 30 - June 1, 2005, Proceedings, Part II, pp. 885-890, 2005, Springer, 3-540-25913-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Gang Liu, Xuehong Yang, Minzan Li |
An Artificial Neural Network Model for Crop Yield Responding to Soil Parameters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (3) ![In: Advances in Neural Networks - ISNN 2005, Second International Symposium on Neural Networks, Chongqing, China, May 30 - June 1, 2005, Proceedings, Part III, pp. 1017-1021, 2005, Springer, 3-540-25914-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Andrew B. Kahng, Bao Liu 0001, Ion I. Mandoiu |
Nontree routing for reliability and yield improvement [IC layout]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1), pp. 148-156, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Naran Sirisantana, Bipul Chandra Paul, Kaushik Roy 0001 |
Enhancing Yield at the End of the Technology Roadmap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 21(6), pp. 563-571, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Davide Appello, Alessandra Fudoli, Katia Giarda, Vincenzo Tancorre, Emil Gizdarski, Ben Mathew |
Understanding Yield Losses in Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 21(3), pp. 208-215, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Amit Agarwal 0001, Bipul Chandra Paul, Kaushik Roy 0001 |
A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 12-14 July 2004, Funchal, Madeira Island, Portugal, pp. 149-154, 2004, IEEE Computer Society, 0-7695-2180-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Christian Gotzel, Karl Inderfurth |
Approximate Policies for Hybrid Production and Rework Systems with Stochastic Demand and Yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OR ![In: Operations Research, Proceedings 2004, Selected Papers of the Annual International Conference of the German Operations Research Society (GOR), Jointly Organized with the Netherlands Society for Operations Research (NGB), Tilburg, The Netherlands, September 1-3, 2004, pp. 41-49, 2004, 978-3-540-24274-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Phil Nigh |
Redefining ATE: "Data Collection Engines that Drive Yield Learning and Process Optimization". ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1429, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Jitendra Khare |
Memory Yield Improvement - SoC Design Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1445, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy 0001 |
Novel sizing algorithm for yield improvement under process variation in nanometer technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 454-459, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Performance, Design, Algorithms, Reliability |
19 | Thomas S. Barnett, Adit D. Singh, Victor P. Nelson |
Extending integrated-circuit yield-models to estimate early-life reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 52(3), pp. 296-300, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Yervant Zorian, Samvel K. Shoukourian |
Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 20(3), pp. 58-66, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Doru P. Munteanu, Víctor Suñé, Rosa Rodríguez-Montañés, Juan A. Carrasco |
A Combinatorial Method for the Evaluation of Yield of Fault-Tolerant Systems-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2003 International Conference on Dependable Systems and Networks (DSN 2003), 22-25 June 2003, San Francisco, CA, USA, Proceedings, pp. 563-572, 2003, IEEE Computer Society, 0-7695-1952-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Kumaraswamy Ponnambalam, Abbas Seifi, Jirí Vlach |
Yield optimization with correlated design parameters and non-symmetrical marginal distributions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 736-739, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | L. Forli, Jean-Michel Portal, Didier Née, Bertrand Borot |
Infrastructure IP for Back-End Yield Improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 1129-1134, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Thomas S. Barnett, Adit D. Singh |
Relating Yield Models to Burn-In Fall-Out in Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 77-84, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Andrew B. Kahng, Bao Liu 0001, Ion I. Mandoiu |
Non-tree routing for reliability and yield improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 260-266, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Yonghua Cong, Randall L. Geiger |
Formulation of INL and DNL yield estimation in current-steering D/A converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 149-152, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Giovanni Spagnuolo |
An interval arithmetic-based yield evaluation in circuit tolerance design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 753-756, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Yu Lin, Randall L. Geiger |
Resistors layout for enhancing yield of R-2R DACs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 97-100, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Thomas S. Barnett, Adit D. Singh, Matt Grady, Kathleen G. Purdy |
Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 75-80, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Zhigang Jiang, Sandeep K. Gupta 0001 |
An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 824-833, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Yervant Zorian |
Embedded Memory Test and Repair: Infrastructure IP for SOC Yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 340-349, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Mark Craig, Alvin Jee, Prashant Maniar |
An Integrated Approach to Yield Loss Characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 350-356, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Junichi Hirase |
Yield Increase of VLSI after Redundancy-Repairing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 353-358, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
Displaying result #301 - #400 of 8586 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5][ 6][ 7][ 8][ 9][ 10][ 11][ 12][ 13][ >>] |
|