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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 5098 occurrences of 1721 keywords
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Results
Found 24872 publication records. Showing 24872 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
14 | James A. Hilder, Andy M. Tyrrell |
An evolutionary platform for developing next-generation electronic circuits. |
GECCO (Companion) |
2007 |
DBLP DOI BibTeX RDF |
analogue circuit design, genetic algorithms, genetic programming, CMOS, SPICE |
14 | Franz X. Ruckerbauer, Georg Georgakos |
Soft Error Rates in 65nm SRAMs--Analysis of new Phenomena. |
IOLTS |
2007 |
DBLP DOI BibTeX RDF |
NSER, ASER, multi-bit upset, soft errors and radiation, CMOS, SRAM, SEU |
14 | Anand Mohan, Aladin Zayegh, Aleksandar Stojcevski |
A High Speed Analog to Digital Converter for Ultra Wide Band Applications. |
EUC Workshops |
2007 |
DBLP DOI BibTeX RDF |
Flash Topology, UWB, Power Saving, ADC, CMOS Technology |
14 | Xudong Niu, Yan Song, Bo Li, Wei Bian, Yadong Tao, Feng Liu, Jinhua Hu, Yu Chen, Frank He |
Tests on Symmetry and Continuity between BSIM4 and BSIM5. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
BSIM4, BSIM5, CMOS circuit design, symmetry, continuity, compact model |
14 | Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi |
Diagnosis of Full Open Defects in Interconnecting Lines. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
Defect Diagnosis, Full Open Defect, Interconnecting Line, CMOS |
14 | Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi |
Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
Current Based Diagnosis, Current Signatures, I_DDQ, Very Low Voltage, CMOS, Bridging Defect |
14 | Mohamed A. Gomaa, T. N. Vijaykumar |
Opportunistic Transient-Fault Detection. |
IEEE Micro |
2006 |
DBLP DOI BibTeX RDF |
Transient-fault detection, redundancy, soft errors, CMOS scaling |
14 | Amit Agarwal 0001, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy 0001, Chris H. Kim |
Leakage Power Analysis and Reduction for Nanoscale Circuits. |
IEEE Micro |
2006 |
DBLP DOI BibTeX RDF |
nanoscale circuits, CMOS, technology scaling, leakage power reduction |
14 | Sachin S. Sapatnekar |
Book Reviews: Plumbing the Depths of Leakage. |
IEEE Des. Test Comput. |
2006 |
DBLP DOI BibTeX RDF |
nanometer CMOS technology, leakage |
14 | József Sziray |
Test Calculation for Logic and Delay Faults in Digital Circuits. |
MTV |
2006 |
DBLP DOI BibTeX RDF |
Test-pattern calculation, logic faults, CMOS transistor structures, functional testing, delay faults, multi-valued logic |
14 | Pablo Aguirre, Fernando Silveira |
Bias circuit design for low-voltage cascode transistors. |
SBCCI |
2006 |
DBLP DOI BibTeX RDF |
CMOS, low voltage, analog design |
14 | Amin Shameli, Payam Heydari |
A novel power optimization technique for ultra-low power RFICs. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
radio-frequency integrated circuit, CMOS, ultra-low power, low-noise amplifier |
14 | Qi Wang, Mani Soma |
RF Front-end System Gain and Linearity Built-in Test. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
CMOS RF amplitude detector, gfain measurement, linearity measurement, built-in test, RF test |
14 | J. W. McPherson |
Reliability challenges for 45nm and beyond. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
design, reliability, CMOS, scaling, materials |
14 | Osamu Takahashi, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Joel Silberman |
Power-Conscious Design of the Cell Processor's Synergistic Processor Element. |
IEEE Micro |
2005 |
DBLP DOI BibTeX RDF |
Synergistic processor element, power-conscious design, low power, CMOS, SPE, Cell Processor |
14 | Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen |
Architecture for area-efficient 2-D transform in H.264/AVC. |
ICME |
2005 |
DBLP DOI BibTeX RDF |
architecture shrinking, 2-D transform, H.264-AVC, automatic volume control, very large scale integration, ASIC, application-specific integrated circuit, matrix multiplication, minimization, CMOS technology, VLSI technology |
14 | Peter C. S. Scholtens, David Smola, Maarten Vertregt |
Systematic power reduction and performance analysis of mismatch limited ADC designs. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
CMOS analog circuits, bandwidth scaling, flash/folding architecture, low power, technology scaling, A/D converters |
14 | Dietmar Fey, Daniel Schmidt 0003 |
Marching-pixels: a new organic computing paradigm for smart sensor processor arrays. |
Conf. Computing Frontiers |
2005 |
DBLP DOI BibTeX RDF |
image pre-processing, smart CMOS camera, smart pixels, self-organization, organic computing |
14 | Gaurav Gulati, Erik Brunvand |
Design of a cell library for asynchronous microengines. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
CMOS cell library, microprogramed control, asynchronous control, self-timed systems |
14 | Gerard Allwein, Hilmi Demir, Lee Pike |
Logics for Classes of Boolean Monoids. |
J. Log. Lang. Inf. |
2004 |
DBLP DOI BibTeX RDF |
algebras of relations, Boolean monoids, correspondence theory, Kripke frames, relative modalities, CMOS circuits |
14 | Brian Moore 0001, Christopher J. Backhouse, Martin Margala |
Design of Wireless Sub-Micron Characterization System. |
VTS |
2004 |
DBLP DOI BibTeX RDF |
Communication, Low-power-design, CMOS, Faults, Low-voltage, Mixed-signal |
14 | Kaviraj Chopra, Sarma B. K. Vrudhula |
Implicit pseudo boolean enumeration algorithms for input vector control. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
power, CMOS, SAT, binary decision diagrams, leakage, symbolic methods |
14 | Cassondra Neau, Kaushik Roy 0001 |
Optimal body bias selection for leakage improvement and process compensation over different technology generations. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
band-to-band tunneling, leakage components, process compensation, substrate bias, process variation, leakage current, CMOS scaling, body bias |
14 | Hesam Amir Aslanzadeh, Saeid Mehrmanesh, Mohammad B. Vahidfar, Amin Quasem Safarian, Reza Lotfi |
A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using "Slew Boost" technique. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
CMOS analog circuit, Slew Boost technique, class AB, low power, high speed, operational amplifier, pipelined analog to digital converter, ultra low voltage |
14 | Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe 0001, Marios C. Papaefthymiou |
A 225 MHz resonant clocked ASIC chip. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
adiabatic logic, resonant LC tank, single phase, VLSI, CMOS, flip-flop, low energy, clock generator |
14 | Sunjaya Djaja, Glenn H. Chapman, Desmond Y. H. Cheung, Yves Audet |
Implementation and Testing of Fault-Tolerant Photodiode-Based Active Pixel Sensor (APS). |
DFT |
2003 |
DBLP DOI BibTeX RDF |
photodiode APS, fault-tolerance, redundancy, SOC, CMOS image sensor, active pixel sensor |
14 | Brian A. Floyd, Xiaoling Guo, James Caserta, Timothy O. Dickson, Chih-Ming Hung, Kihong Kim, Kenneth K. O |
Wireless interconnects for clock distribution. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
integrated antenna, wireless interconnect, wireless communication, interconnect, clock distribution, RF CMOS |
14 | Norio Kuji, Takako Ishihara |
EB-Testing-Pad Method and Its Evaluation by Actual Devices. |
Asian Test Symposium |
2001 |
DBLP DOI BibTeX RDF |
E-beam tester, stacked vias, testing pads, multi level wiring, CMp, SIMOX/CMOS technology, observability |
14 | Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada |
Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field. |
DFT |
2001 |
DBLP DOI BibTeX RDF |
supply current test, time-variable electric field, test pattern generation, CMOS IC, open defects |
14 | Hans A. R. Manhaeve, Stefaan Kerckenaere |
An On-Chip Detection Circuit for the Verification of IC Supply Connections. |
DFT |
2001 |
DBLP DOI BibTeX RDF |
IC connections, connection verification, supply current measurements, on-chip monitor, reliability, DFT, CMOS, Scan, Boundary Scan, IP core, Current monitor |
14 | Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald |
Self-Timed Carry-Lookahead Adders. |
IEEE Trans. Computers |
2000 |
DBLP DOI BibTeX RDF |
delay-insenstive circuits, tree iterative circuits, CMOS, Self-timed circuits, carry-lookahead adders |
14 | Michele Favalli, Cecilia Metra |
Bridging Faults in Pipelined Circuits. |
J. Electron. Test. |
2000 |
DBLP DOI BibTeX RDF |
fault modeling, bridging faults, CMOS circuits, pipelined circuits |
14 | Rong Lin |
Parallel Multiplier Designs Utilizing A Non-Binary Logic Scheme. |
EUROMICRO |
2000 |
DBLP DOI BibTeX RDF |
parallel counter and compressor, low power high performance CMOS circuit design, VLSI design, Arithmetic circuit, partial product reduction |
14 | Hans-Martin Blüthgen, Tobias G. Noll |
A Programmable Processor for Approximate String Matching with High Throughput Rate. |
ASAP |
2000 |
DBLP DOI BibTeX RDF |
information retrieval, VLSI, dynamic programming, CMOS, edit distance, approximate string matching |
14 | Chun Lu, Bingxue Shi |
Circuit Realization of a Programmable Neuron Transfer Function and Its Derivative. |
IJCNN (4) |
2000 |
DBLP DOI BibTeX RDF |
Artificial Neural Networks (ANN), CMOS analogue integrated circuits |
14 | Masayuki Tsukisaka, Takashi Nanya |
A testable design for asynchronous fine-grain pipeline circuits. |
PRDC |
2000 |
DBLP DOI BibTeX RDF |
asynchronous fine-grain pipeline circuits, dynamic gates, high-performance datapath design, pipeline latches, scan latch libraries, logic testing, logic CAD, SPICE, CMOS technology, scan path, SPICE simulation, testable design |
14 | Takahiro Hozumi, Osamu Kakusho, Yutaka Hata |
The Output Permutation for the Multiple-Valued Logic Minimization with Universal Literals. |
ISMVL |
1999 |
DBLP DOI BibTeX RDF |
universal literal, output permutation, current-mode CMOS circuits, logic synthesis, cost reduction |
14 | Kwabena Boahen 0001 |
A Throughput-On-Demand Address-Event Transmitter for Neuromorphic Chips. |
ARVLSI |
1999 |
DBLP DOI BibTeX RDF |
Address-Events, Retinomorphic, VLSI, TDMA, Spiking Neurons, CMOS Imager, Neuromorphic |
14 | Sadiq M. Sait, Habib Youssef, Munir M. Zahra |
Tabu Search Based Circuit Optimization. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
CMOS/BiCMOS, Mixed Technologies, Tabu Search, Search Algorithms, Critical Path, False Path, Circuit Optimization |
14 | R. V. K. Pillai, Asim J. Al-Khalili, Dhamin Al-Khalili |
A Low Power Floating Point Accumulator. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
low power CMOS, Digital arithmetic, VLSI architecture, floating point |
14 | Cheng-Wen Wu |
On energy efficiency of VLSI testing. |
Asian Test Symposium |
1997 |
DBLP DOI BibTeX RDF |
test efficiency models, CMOS power consumption model, high testability, high power dissipation, high-power testing, transition activity factor, fabricated chip, testing energy, VLSI, energy efficiency, fault coverage, design optimization, VLSI testing, testing time, test efficiency, testing power |
14 | Michael J. Flynn |
What's ahead in computer design? |
EUROMICRO |
1997 |
DBLP DOI BibTeX RDF |
die area improvement, very high level superscalar processors, very large cache, pin bandwidth, processor complexity, scalability, multiprocessors, logic design, instruction level parallelism, VLIW, CMOS technology, lithography, cycle time, computer design, silicon area, cache size |
14 | Peter M. Kuhn, Andreas Weisgerber, Robert Poppenwimmer, Walter Stechele |
A flexible VLSI architecture for variable block size segment matching with luminance correction. |
ASAP |
1997 |
DBLP DOI BibTeX RDF |
flexible VLSI architecture, variable block size segment matching, luminance correction, segment matching VLSI architecture, evolving motion estimation algorithms, preprocessing unit, halfpel interpolation, pixel decimation, VHDL synthesis, VLSI, CMOS technology, motion vectors, RAM, block matching algorithms, video coding standards |
14 | Ron Lin |
Shift Switching with Domino Logic: Asynchronous VLSI Comparator Schemes. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
shift switching, asynchronous VLSI comparator, precharged CMOS domino logic, VLSI, semaphore |
14 | Gab Joong Jeong, Kyoung Hwan Kwon, Moon Key Lee, Seung Han An |
A Scalable Memory System Design. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
scalable memory system, pipeline technique, systolic data flow, sub-memory blocks, partial binary tree structure, multidirectional data flow, chip size, 4 kbit, 0.8 micron, 5.1 ns, 3.5 mm, throughput, latency, memory architecture, memory architecture, CMOS technology, communication channel, access time, operating speed, clock speed |
14 | D. A. Pierce, Parag K. Lala |
Modular implementation of efficient self-checking checkers for the Berger code. |
J. Electron. Test. |
1996 |
DBLP DOI BibTeX RDF |
conventional Berger code, 1's counters, fully-testable circuits, partitioning, CMOS technology, totally self-checking checkers, Berger code |
14 | Massoud Pedram |
Power minimization in IC design: principles and applications. |
ACM Trans. Design Autom. Electr. Syst. |
1996 |
DBLP DOI BibTeX RDF |
adiabatic circuits, dynamic power dissipation, low power layout, low power synthesis, lower-power design, power analysis and estimation, power minimization and management, silicon-on-insulator technology, switched capacitance, synthesis, system design, power management, layout, probabilistic analysis, symbolic simulation, CMOS circuits, switching activity, statistical sampling, computer-aided design of VLSI, gated clocks, energy-delay product |
14 | Christian Piguet, Thierry Schneider, Jean-Marc Masgonty, Claude Arm, Serge Durand, M. Stegers |
Low-Power Embedded Microprocessor Design. |
EUROMICRO |
1996 |
DBLP DOI BibTeX RDF |
low-power embedded microprocessor design, low-power RISC-like architectures, gated clock techniques, power savings, microprocessor chips, CMOS technology, hierarchical memories, clock cycles |
14 | S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri |
A VLSI chip for image compression using variable block size segmentation. |
ICCD |
1996 |
DBLP DOI BibTeX RDF |
variable block size segmentation, VBSS scheme, variable size blocks, redundancy features, maximum compression, nearest neighbor communication, CMOS VLSI chip, image characteristics extraction subsystem, Cadence design tools, VLSI, parallelism, pipelining, image compression, VLSI architecture, VLSI implementation, lossless image compression, VLSI chip, coding techniques |
14 | Navin Chaddha, Mohan Vishwanath |
A low power video encoder with power, memory and bandwidth scalability. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
low power video encoder, power scalability, memory scalability, bandwidth scalability, portable video, generic block transform, memory rate distortion, perceptually weighted hierarchical vector quantization, 150 to 300 W, 0.8 micron, 1.5 V, video coding, power consumption, transform coding, table lookup, table lookup, CMOS technology, vector quantisation, block codes |
14 | Janusz A. Brzozowski, Kaamran Raahemifar |
Testing C-elements is not elementary. |
ASYNC |
1995 |
DBLP DOI BibTeX RDF |
C-elements testing, gate circuits, C-element, CMOS implementations, logic testing, logic tests, asynchronous circuits, fault location, stuck-at faults, speed-independence |
14 | Branka Medved Rogina, Bozidar Vojnovic |
Metastability evaluation method by propagation delay distribution measurement. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
propagation delay distribution measurement, edge-triggered flip-flops, input signals time relationship, output signal timing characteristics, analytical representation, propagation delay density distribution function, fault events, integrated propagation delay density distribution function, flip-flop normal propagation delay, resolution time constant, automatic data acquisition, complex architecture microsystems, MTBF, latch devices, custom CMOS, VLSI, VLSI, fault diagnosis, logic testing, delays, logic design, asynchronous circuits, flip-flops, data acquisition, failure analysis, reliability analysis, graphical representation, metastability, PLD, asynchronous logic, integrated circuit reliability, statistical measurement |
14 | Gensoh Matsubara, Nobuhiro Ide, Haruyuki Tago, Seigo Suzuki, Nobuyuki Goto |
30-ns 55-b Radix 2 Division and Square Root Using a Self-Timed Circuit. |
IEEE Symposium on Computer Arithmetic |
1995 |
DBLP DOI BibTeX RDF |
simulation, CMOS, division, square root, self-timed, SRT, on-the-fly |
14 | Qiang Li, David B. Gustavson |
Fat-tree for local area multiprocessors. |
IPPS |
1995 |
DBLP DOI BibTeX RDF |
local area multiprocessors, LAMP, high-performance low-cost parallel computing, LAN-size area, remote data cache, high performance multiprocessor, point-to-point physical connections, high system throughput, fat-tree topology, cable length, link clock speeds, biCMOS chips, performance evaluation, parallel architectures, parallel architecture, multiprocessor interconnection networks, local area networks, latency, packet switching, packet switch, CMOS, shared memory systems, distributed memory systems, simulation results, cache storage, system buses, SCI, buffer requirements, distributed-shared-memory multiprocessor, scalable coherent interface |
14 | Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama |
Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. |
ISMVL |
1995 |
DBLP DOI BibTeX RDF |
multiple-valued arithmetic integrated circuits, dual-rail source-coupled logic, multiple-valued current-mode MOS integrated circuit, high-speed arithmetic systems, multiple-valued source-coupled logic circuit, dual-rail complementary inputs, pipelined multiplier, 54 bit, 200 MHz, 0.8 mum, 1.5 V, CMOS logic circuits, multiplying circuits, multivalued logic circuits, current-mode logic, pipeline arithmetic |
14 | Wai-Chi Fang, Bing J. Sheu, Holger Venus, Rainer Sandau |
Smart-pixel array processors based on optimal cellular neural networks for space sensor applications. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
artificial satellites, smart-pixel array processors, optimal cellular neural networks, space sensor applications, hardware annealing, digitally programmable synaptic weights, multisensor parallel interface, programmable multi-dimensional array, optoelectronic neurons, neuroprocessor, scalable multiprocessor system, intelligent multisensor, advanced small satellites, neuroprocessor array chip, performance evaluation, real-time systems, parallel processing, CMOS technology, image sensors, aerospace computing, computing performance, neural chips, intelligent sensors, neural net architecture, active-pixel sensors, cellular neural nets |
14 | Chuan-Yu Wang, Kaushik Roy 0001 |
Control unit synthesis targeting low-power processors. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
control unit synthesis, low-power processors, low-power decoding scheme, microprogrammed architecture, nanoprogrammed architecture, 8086 instruction set, instruction opcodes, computer architecture, logic design, encoding, decoding, microprocessor chips, graph embedding, instruction sets, microprogramming, CMOS circuits, logic minimization, system reliability, switching activity, minimisation of switching nets, pseudo-Boolean programming |
14 | H. Dhanesha, K. Falakshahi, Mark Horowitz |
Array-of-arrays architecture for parallel floating point multiplication. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
array-of-arrays architecture, parallel floating point multiplication, mantissa path, IEEE standard 754, dual-rail domino, HSpice simulation, capacitive load model, 53 bit, 10 ns, 4.3 V, 120 C, parallel architectures, trees, latency, floating point arithmetic, multiplying circuits, CMOS technology, Verilog, synergy, 1 micron |
14 | James Phillips, Stamatis Vassiliadis |
High-Performance 3-1 Interlock Collapsing ALU's. |
IEEE Trans. Computers |
1994 |
DBLP DOI BibTeX RDF |
3-1 interlock collapsing ALU, execution interlocks, multiple instruction issuing machines, parallel architectures, delay, digital arithmetic, CMOS technology, critical path, reduced instruction set computing, Boolean equations |
14 | Michele Favalli, Piero Olivo, Bruno Riccò, Fabio Somenzi |
Fault simulation for general FCMOS ICs. |
J. Electron. Test. |
1991 |
DBLP DOI BibTeX RDF |
fault simulation, bridging faults, CMOS circuits, stuck-open faults, critical path analysis |
14 | Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija |
Energy efficient implementation of parallel CMOS multipliers with improved compressors. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
arithmetic and logic structures, VLSI, low-power design, high- speed arithmetic, booth encoding |
14 | Leila Koushaeian, Stan Skafidas |
A 65nm CMOS low-power, low-voltage bandgapreference with using self-biased composite cascode opamp. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
bandgap voltage reference, self-biased, self-cascode, temperature coefficient, voltage reference |
14 | Nandish Ashutosh Mehta, Gururaj V. Naik, Bharadwaj S. Amrutur |
In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
DVTS loop, in-situ power monitor, power optimum point, variable body bias, variable supply voltage, low power, ground bounce |
14 | Kagan Irez, Jiaping Hu, Charles A. Zukowski |
Characteristics of MS-CMOS logic in sub-32nm technologies. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
MSCMOS, gate leakage reduction, hs&ls, logic overhead, upsizing, noise margin, input vector, domino, downsizing |
14 | Hsiu-Ming Chang 0001, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, Cheng-Wen Wu |
An error tolerance scheme for 3D CMOS imagers. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
image sensor, error tolerance, 3D IC |
14 | Yngvar Berg, Omid Mirmotahari |
Low voltage precharge CMOS logic. |
DDECS |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz |
Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS. |
DDECS |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Georges G. E. Gielen |
Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS. |
DDECS |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Ahmet Öncü, Minoru Fujishima |
Low-power CMOS transceiver circuits for 60GHz band millimeter-wave impulse radio. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Xiaolei Zhu, Sanroku Tsukamoto, Tadahiro Kuroda |
A 1 GHz CMOS comparator with dynamic offset control technique. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya |
A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Samiran DasGupta, Pradip Mandal |
An automated design approach for CMOS LDO regulators. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Genival Mariano de Araujo, Heider Marconi G. Madureira, José Camargo da Costa |
Design and characterization of a 0.35 micron CMOS voltage-to-current converter. |
SBCCI |
2009 |
DBLP DOI BibTeX RDF |
voltage-to-current converter, system on chip, current reference |
14 | Kuande Wang, Li Chen, Jinsheng Yang |
AN ultra low power fault tolerant SRAM design in 90nm CMOS. |
CCECE |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Sanjay Kumar Wadhwa |
A Low Voltage CMOS Proportional-to-Absolute Temperature Current Reference. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Sheng-Chih Lin, Kaustav Banerjee |
A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner |
Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Brajesh Kumar Kaushik, Sankar Sarkar |
Crosstalk Analysis for a CMOS-Gate-Driven Coupled Interconnects. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Gülin Tulunay, Sina Balkir |
A Synthesis Tool for CMOS RF Low-Noise Amplifiers. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann |
The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu |
Controllability of Static CMOS Circuits for Timing Characterization. |
J. Electron. Test. |
2008 |
DBLP DOI BibTeX RDF |
Design for test, Delay fault testing, Scan design |
14 | Snorre Aunet, Bengt Oelmann, Per Andreas Norseng, Yngvar Berg |
Real-Time Reconfigurable Subthreshold CMOS Perceptron. |
IEEE Trans. Neural Networks |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Marcin J. Beresinski, Tomasz Borejko, Witold A. Pleskacz, Viera Stopjaková |
Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology. |
DDECS |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Baozhen Chen, Chengwu Tao, Sumarlin William, Santosh Pandey |
Biochemical sensing of charged polyelectrolytes with a novel CMOS floating-gate device architecture. |
EIT |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Luciano Severino de Paula, Altamiro Amadeu Susin, Sergio Bampi |
A wide band CMOS differential voltage-controlled ring oscillator. |
SBCCI |
2008 |
DBLP DOI BibTeX RDF |
SSB mixer, wide-band oscillators, voltage-controlled oscillator, frequency synthesizer |
14 | Jorge Oliveros, Dwight Cabrera, Elkim Roa, Wilhelmus A. M. Van Noije |
An improved and automated design tool for the optimization of CMOS OTAs using geometric programming. |
SBCCI |
2008 |
DBLP DOI BibTeX RDF |
OTA design, analog CAD, analog circuit optimization, design methodologies, geometric programming |
14 | Pietro Maris Ferreira, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia |
Current mode read-out circuit for infrared photodiode applications in 0.35 mum cmos. |
SBCCI |
2008 |
DBLP DOI BibTeX RDF |
infra-red, read-out, image sensor, current-mode |
14 | Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia |
Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
STTRAM, emerging memory technologies, nonvolatile FPGA |
14 | Joseph T.-s. Tsai, Herming Chiueh |
High linear voltage references for on-chip CMOS smart temperature sensor from -60degreeC to 140degreeC. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Kuo-Ken Huang, Sen Wang, Ching-Kuang C. Tzuang |
Active bandpass filter using transformer feedback in 0.18-µm CMOS for 802.11a wireless LAN. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Saul Rodriguez 0001, Ana Rusu, Li-Rong Zheng 0001, Mohammed Ismail 0001 |
Digital calibration of gain and linearity in a CMOS RF mixer. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Ming-Dou Ker, Chun-Yu Lin 0001, Guo-Xuan Meng |
ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Tongqiang Gao, Chun Zhang, Baoyong Chi, Zhihua Wang 0001 |
An improved method of power control with CMOS class-E power amplifiers. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Benoit Gosselin, Mohamad Sawan |
An ultra low-power CMOS action potential detector. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Mohammad B. Vahidfar, Omid Shoaei |
An IIP2 calibration technique for CMOS multi-standard mixers. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Mohammad B. Vahidfar, Omid Shoaei |
A CMOS high IIP2 mixer for multi-standard receivers. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Sedigheh Hashemi, Omid Shoaei |
A 0.9V 10-bit 100 MS/s switched-RC pipelined ADC without using a front-end S/H in 90nm CMOS. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Christian Peters, Fabian Henrici, Maurits Ortmanns, Yiannos Manoli |
High-bandwidth floating gate CMOS rectifiers with reduced voltage drop. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Bradley A. Minch |
A simple class-AB transconductor in CMOS. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Chen-Yuan Chu, Chien-Cheng Wei, Hui-Chen Hsu, Shu-Hau Feng, Wu-Shiung Feng |
A 24GHz low-power CMOS receiver design. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
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