Search results for "FPGAs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Jae-Jin Lee, Gi-Yong Song	Super Semi-systolic Array-Based Application-Specific PLD Architecture.	ARC	2006	DBLP DOI BibTeX RDF
17	Scott J. Campbell, Sunil P. Khatri	Resource and delay efficient matrix multiplication using newer FPGA devices.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	FPGA, floating point, multiplier, matrix
17	Xin Jia, Ranga Vemuri	CAD Tools for a Globally Asynchronous Locally Synchronous FPGA Architecture.	VLSI Design	2006	DBLP DOI BibTeX RDF
17	Sanghamitra Roy, Prith Banerjee	An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	field programmable gate arrays, Automation, quantization, floating-point arithmetic, fixed-point arithmetic
17	Kara K. W. Poon, Steven J. E. Wilton, Andy Yan	A detailed power model for field-programmable gate arrays.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Power estimation model, architecture, sensitivity analysis, power consumption
17	Sajid Baloch, Imran Ahmed 0001, Tughrul Arslan	Domain-Specific Reconfigurable Array Targeting Discrete Wavelet Transform for System-on-Chip Applications.	IPDPS	2005	DBLP DOI BibTeX RDF
17	Weisheng Chong, Sho Ogata, Masanori Hariyama, Michitaka Kameyama	Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory.	IPDPS	2005	DBLP DOI BibTeX RDF
17	Young-Su Kwon, Payam Lajevardi, Anantha P. Chandrakasan, Frank Honoré, Donald E. Troxel	A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool.	SLIP	2005	DBLP DOI BibTeX RDF	3-D FPGA, wire resource prediction
17	Viktor K. Prasanna	High Performance Computing using Reconfigurable Hardware.	ENC	2005	DBLP DOI BibTeX RDF
17	Xizhen Xu, Sotirios G. Ziavras	H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication.	ICCD	2005	DBLP DOI BibTeX RDF
17	Kuan Zhou, John F. McDonald 0001	Multi-GHz SiGe design methodologies for reconfigurable computing.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	CLB, virtex, FPGA, SiGe
17	Ling Zhuo, Viktor K. Prasanna	High Performance Linear Algebra Operations on Reconfigurable Systems.	SC	2005	DBLP DOI BibTeX RDF
17	Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu 0011	Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Data communications devices, application studies resulting in better multiple-processor systems, reconfigurable hardware, wireless systems, special-purpose and application-based systems, adaptable architectures, heterogeneous (hybrid) systems, design studies, signal processing systems
17	Nicholas Weaver, John R. Hauser, John Wawrzynek	The SFRA: a corner-turn FPGA architecture.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA CAD, FPGA design study, FPGA optimization, FPGA architecture
17	Maya B. Gokhale, Janette Frigo, Christine Ahrens, Justin L. Tripp, Ronald G. Minnich	Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer.	FPL	2004	DBLP DOI BibTeX RDF
17	Mike Hutton	Advances and trends in FPGA design.	SBCCI	2004	DBLP DOI BibTeX RDF
17	Sami Khawam, Tughrul Arslan, Fred Westall	Synthesizable Reconfigurable Array Targeting Distributed Arithmetic for System-on-Chip Applications.	IPDPS	2004	DBLP DOI BibTeX RDF
17	David Wentzlaff, Anant Agarwal	A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation.	FCCM	2004	DBLP DOI BibTeX RDF
17	Fei Li 0003, Yan Lin 0001, Lei He 0001	Vdd programmability to reduce FPGA interconnect power.	ICCAD	2004	DBLP DOI BibTeX RDF
17	Ross Snider, Yongming Zhu	Developing a Data Driven System for Computational Neuroscience.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
17	Roar Lien, Tim Grembowski, Kris Gaj	A 1 Gbit/s Partially Unrolled Architecture of Hash Functions SHA-1 and SHA-512.	CT-RSA	2004	DBLP DOI BibTeX RDF
17	Seonil Choi, Ju-wook Jang, Sumit Mohanty, Viktor K. Prasanna	Domain-Specific Modeling for Rapid Energy Estimation of Reconfigurable Architectures.	J. Supercomput.	2003	DBLP DOI BibTeX RDF	FPGA, energy optimization, domain-specific modeling, energy estimation
17	Fernanda Lima 0001, Luigi Carro, Ricardo Augusto da Luz Reis	Reducing pin and area overhead in fault-tolerant FPGA-based designs.	FPGA	2003	DBLP DOI BibTeX RDF	fault-tolerance, FPGA
17	Seokjin Lee, Hua Xiang 0001, D. F. Wong 0001, Richard Y. Sun	Wire type assignment for FPGA routing.	FPGA	2003	DBLP DOI BibTeX RDF	min-cost flow algorithm, wire type assignment, FPGA routing
17	Sumit Mohanty, Viktor K. Prasanna	An Algorithm Designer's Workbench for Platform FPGA's.	FPL	2003	DBLP DOI BibTeX RDF
17	Heather Quinn, Laurie A. Smith King, Miriam Leeser, Waleed Meleis	Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines.	FCCM	2003	DBLP DOI BibTeX RDF
17	Michael J. Wirthlin, Darrel Eric Johnson, Nathan Rollins, Michael P. Caffrey, Paul S. Graham	The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets.	FCCM	2003	DBLP DOI BibTeX RDF
17	Jason Cong, Yizhou Lin, Wangning Long	SPFD-based global rewiring.	FPGA	2002	DBLP DOI BibTeX RDF	FPGA synthesis, SPFD, SPFD-based global rewiring, logical re-synthesis
17	Deshanand P. Singh, Stephen Dean Brown	Constrained clock shifting for field programmable gate arrays.	FPGA	2002	DBLP DOI BibTeX RDF
17	K. K. Lee, D. F. Wong 0001	Incremental reconfiguration of multi-FPGA systems.	FPGA	2002	DBLP DOI BibTeX RDF
17	J. Bryan Lewis, Ivo Bolsens, Rudy Lauwereins, Chris Wheddon, Bhusan Gupta, Yankin Tanurhan	Reconfigurable SoC - What Will it Look Like?	DATE	2002	DBLP DOI BibTeX RDF
17	Thomas Lehmann, Andreas Schreckenberg	Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-Linux.	FPL	2001	DBLP DOI BibTeX RDF
17	Mohammed A. S. Khalid, Jonathan Rose	A novel and efficient routing architecture for multi-FPGA systems.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
17	Amit Singh 0001, Luca Macchiarulo, Arindam Mukherjee 0001, Malgorzata Marek-Sadowska	A novel high throughput reconfigurable FPGA architecture.	FPGA	2000	DBLP DOI BibTeX RDF
17	Stephen J. Bellis, William P. Marnane	A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System.	FPL	2000	DBLP DOI BibTeX RDF
17	Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi	EVIDENCE: An FPGA-Based System for Photon EVent IDENtification and CEntroiding.	FCCM	2000	DBLP DOI BibTeX RDF
17	José Ignacio Hidalgo, Juan Lanchares, Román Hermida	Partitioning and Placement for Multi-FPGA Systems Using Genetic Algorithms.	EUROMICRO	2000	DBLP DOI BibTeX RDF
17	John Morris, Gary A. Bundell, Sonny Tham	A Re-Configurable Processor for Petri Net Simulation.	HICSS	2000	DBLP DOI BibTeX RDF
17	James Hwang, Cameron Patterson, Sujoy Mitra	VHDL Placement Directives for Parametric IP Blocks.	FCCM	1999	DBLP DOI BibTeX RDF
17	Masaru Katayama, Atsushi Takahara, Toshiaki Miyazaki	Reconfigurable Signal Probing Mechanism for a Transmutable Telecom System.	ICPP Workshops	1999	DBLP DOI BibTeX RDF
17	Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar	Satisfiability-Based Detailed FPGA Routing.	VLSI Design	1999	DBLP DOI BibTeX RDF
17	Mohammed A. S. Khalid, Jonathan Rose	A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems.	FPGA	1998	DBLP DOI BibTeX RDF
17	Jason Cong, Yuzheng Ding	Combinational logic synthesis for LUT based field programmable gate arrays.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	FPGA, routing, synthesis, system design, decomposition, technology mapping, simplification, programmable logic, power minimization, logic optimization, delay modeling, delay minimization, computer-aided design of VLSI, area minimization
17	Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki	A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays.	ICCAD	1994	DBLP DOI BibTeX RDF
17	Marianne E. Louie, Milos D. Ercegovac	On digit-recurrence division implementations for field programmable gate arrays.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
17	Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic	A detailed router for field-programmable gate arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
16	Huimin Bian, Andrew C. Ling, Alexander Choong, Jianwen Zhu	Towards scalable placement for FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, convex optimization, quadratic placement, bipartite matching
16	Edward A. Stott, Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung	Degradation in FPGAs: measurement and modelling.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, self test
16	Shreesha Srinath, Katherine Compton	Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks.	FPGA	2010	DBLP DOI BibTeX RDF	asymmetric multipliers, composable multipliers, multiplier design
16	Larkhoon Leem, James A. Weaver, Metha Jeeradit, James S. Harris Jr.	Nano-magnetic non-volatile CMOS circuits for nano-scale FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	spin-torque devices, fpga, spintronics
16	Hoang Le, Yi-Hua E. Yang, Viktor K. Prasanna	Memory efficient string matching: a modular approach on FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	deep packet classification, fpga, packet filtering
16	Julien Lamoureux, Scott Miller, Mihai Sima	Fine-grained vs. coarse-grained shift-and-add arithmetic in FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	shift-and-add arithmetic, fpga, cordic, coarse-grained
16	Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita	Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	overclocking, timing error detection, timing error recovery, fpga
16	René Müller 0001, Jens Teubner	FPGAs: a new point in the database design space.	EDBT	2010	DBLP DOI BibTeX RDF	FPGA, VLSI, hardware acceleration, data processing
16	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne	Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	Field Programmable Compressor Tree (FPCT), compressor tree, Field Programmable Gate Array (FPGA)
16	Eric S. Chung, Michael Papamichael, Eriko Nurvitadhi, James C. Hoe, Ken Mai, Babak Falsafi	ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	simulator, FPGA, prototype, multiprocessor, multicore, emulator
16	Timothy R. Pearson	Real-time invariant textural object recognition with FPGAs.	EIT	2009	DBLP DOI BibTeX RDF
16	Lei Chen 0010, Zhiquan Zhang, Zhiping Wen 0001	A novel BIST approach for testing input/output buffers in FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	i/o buffers, built-in self-test, fpga testing
16	Weirong Jiang, Viktor K. Prasanna	Large-scale wire-speed packet classification on FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, decision tree, pipeline, sram, packet classification
16	Dirk Koch, Christian Beckhoff, Jürgen Teich	A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, reconfiguration, communication architecture
16	David B. Thomas, Lee W. Howes, Wayne Luk	A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation.	FPGA	2009	DBLP DOI BibTeX RDF	mppa, fpga, monte-carlo, random numbers, gpu
16	Sumanta Chaudhuri	Diagonal tracks in FPGAs: a performance evaluation.	FPGA	2009	DBLP DOI BibTeX RDF	diagonal tracks, octagonal, fpga, hexagonal
16	Jason Helge Anderson	Emerging application domains: research challenges and opportunities for FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	performance, field-programmable gate array, fpga, applications, high-performance computing, power, reconfigurable computing
16	Val Pevzner, Andrew A. Kennings, Andy Fox	Physical optimization for FPGAs using post-placement topology rewriting.	ISPD	2009	DBLP DOI BibTeX RDF	fpga, timing optimization, physical synthesis
16	Nikolaos Alachiotis 0001, Euripides Sotiriades, Apostolos Dollas, Alexandros Stamatakis	Exploring FPGAs for accelerating the phylogenetic likelihood function.	IPDPS	2009	DBLP DOI BibTeX RDF
16	Alexander Klimm, Oliver Sander, Jürgen Becker 0001	A MicroBlaze specific co-processor for real-time hyperelliptic curve cryptography on Xilinx FPGAs.	IPDPS	2009	DBLP DOI BibTeX RDF
16	Luca Sterpone	Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs.	ARC	2009	DBLP DOI BibTeX RDF	fault tolerance, FPGA, Single Event Upset, Triple Modular Redundancy, Timing-driven Placement
16	Heiner Litz, Holger Fröning, Ulrich Brüning 0001	A HyperTransport 3 Physical Layer Interface for FPGAs.	ARC	2009	DBLP DOI BibTeX RDF
16	Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu	High-performance CUDA kernel execution on FPGAs.	ICS	2009	DBLP DOI BibTeX RDF	cuda programming model, fpga, high level synthesis, high performance computing, gpu, coarse grained parallelism
16	Taiga Takata, Yusuke Matsunaga	An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	FPGA, logic synthesis, technology mapping
16	Akhilesh Kumar, Mohab Anis	IR-drop management CAD techniques in FPGAs for power grid reliability.	ISQED	2009	DBLP DOI BibTeX RDF
16	Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Hanpei Koike, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa	Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	FPGA, configuration, within-die variation, timing yield
16	Satish Sivaswamy, Kia Bazargan	Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	skew assignment, routing, Statistical timing analysis
16	Yan Lin 0001, Lei He 0001, Mike Hutton	Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
16	Ignacio Bravo Muñoz, Manuel Mazo 0001, José Luis Lázaro, Pedro Jiménez, Alfredo Gardel Vicente, Marta Marrón	Novel HW Architecture Based on FPGAs Oriented to Solve the Eigen Problem.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
16	Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton	GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
16	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	Input Vector Reordering for Leakage Power Reduction in FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
16	Yu Hu 0002, Victor Shih, Rupak Majumdar, Lei He 0001	Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
16	Zhi Guo, Walid A. Najjar, Betul Buyukkurt	Efficient hardware code generation for FPGAs.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	FPGA, high-level synthesis, VHDL, Reconfigurable computing, data reuse
16	Rajarshi Mukherjee, Song Liu, Seda Ogrenci Memik, Somsubhra Mondal	A high-level clustering algorithm targeting dual Vdd FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	clustering, field programmable gate arrays, partitioning, placement, voltage scaling, Dynamic power
16	Bernd Neumann, Thorsten von Sydow, Holger Blume, Tobias G. Noll	Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	eFPGA, Parametrisable architecture, Arithmetic oriented, Processor-eFPGA coupling, ASIP
16	Andrzej Krasniewski	Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAs.	DDECS	2008	DBLP DOI BibTeX RDF
16	Rosemary M. Francis, Simon W. Moore, Robert D. Mullins	A Network of Time-Division Multiplexed Wiring for FPGAs.	NOCS	2008	DBLP DOI BibTeX RDF	time division multplexing, fpga, network-on-chip
16	Florent de Dinechin, Jérémie Detrey, Octavian Cret, Radu Tudoran	When FPGAs are better at floating-point than microprocessors.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, floating-point, arithmetic
16	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk	High-throughput interconnect wave-pipelining for global communication in FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF
16	Mingjie Lin, Abbas El Gamal	TORCH: a design tool for routing channel segmentation in FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, performance analysis, segmentation, routing architecture
16	Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai	A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	simulator, FPGA, prototype, multiprocessor, multicore, emulator
16	Ian Kuon, Jonathan Rose	Area and delay trade-offs in the circuit and architecture design of FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	optimization, FPGA, architecture
16	Luca Sterpone, M. A. Aguirre, Jonathan Noel Tombs, Hipólito Guzmán-Miranda	On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications.	DATE	2008	DBLP DOI BibTeX RDF
16	Bernd Neumann, Thorsten von Sydow, Holger Blume, Tobias G. Noll	Design flow for embedded FPGAs based on a flexible architecture template.	DATE	2008	DBLP DOI BibTeX RDF
16	Taiga Takata, Yusuke Matsunaga	Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs.	ASP-DAC	2008	DBLP DOI BibTeX RDF
16	Shilpa Bhoj, Dinesh Bhatia	A dynamic temperature control simulation system for FPGAs.	FPL	2008	DBLP DOI BibTeX RDF
16	Gang Zhou, Li Li 0027, Harald Michalik	Area optimization of bit parallel finite field multipliers with fast carry logic on FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
16	O. Wohlmuth	Keynote: High performance computing based on FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
16	Hanyu Liu, Xiaolei Chen, Yajun Ha	An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects.	FPL	2008	DBLP DOI BibTeX RDF
16	Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi Onodera	A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
16	Paul Schumacher, Pradip Jha	Fast and accurate resource estimation of RTL-based designs targeting FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
16	Xing Wei, Juanjuan Chen, Qiang Zhou 0001, Yici Cai, Jinian Bian, Xianlong Hong	MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation.	FPL	2008	DBLP DOI BibTeX RDF
16	Jorge Surís, Cameron D. Patterson, Peter Athanas	An efficient run-time router for connecting modules in FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
16	Alexander Klimm, Lars Braun, Jürgen Becker 0001	An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores.	IPDPS	2008	DBLP DOI BibTeX RDF