Search results for "RF-interconnect"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
88	Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Bendix	Prediction of interconnect adjacency distribution: derivation, validation, and applications.	SLIP	2004	DBLP DOI BibTeX RDF	interconnect adjacency, interconnect pattern density, prediction, stochastic model, probability density function
87	Narender Hanchate, Nagarajan Ranganathan	A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Game theory, transmission lines, crosstalk noise, interconnect models, wire sizing, interconnect delay
77	Ian O'Connor	Optical solutions for system-level interconnect.	SLIP	2004	DBLP DOI BibTeX RDF	interconnect technology, optical network on chip, optical interconnect
75	Desmond Kirkpatrick, Peter J. Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester	The great interconnect buffering debate: are you a chicken or an ostrich?	ISPD	2004	DBLP DOI BibTeX RDF
73	Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex	Global interconnect trade-off for technology over memory modules to application level: case study.	SLIP	2003	DBLP DOI BibTeX RDF	Pareto-optimal energy/delay interconnect exploration, interconnect wire processing, intra/inter-memory interconnect
72	Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Wright	Prediction of interconnect pattern density distribution: derivation, validation, and applications.	SLIP	2003	DBLP DOI BibTeX RDF	interconnect network prediction, interconnect pattern density, Stochastic model, probability density function
70	Xiang Qiu, Yuchun Ma, Xiangqing He, Xianlong Hong	IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization.	ISQED	2008	DBLP DOI BibTeX RDF	interconnect power, piecewise model, slack
69	Marvin Tom, David Leong, Guy G. Lemieux	Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs.	ICCAD	2006	DBLP DOI BibTeX RDF	channel width constraints, clustering, field-programmable gate arrays (FPGA), packing
68	Jian Liu, Meigen Shen, Li-Rong Zheng 0001, Hannu Tenhunen	System level interconnect design for network-on-chip using interconnect IPs.	SLIP	2003	DBLP DOI BibTeX RDF	interconnect IP, network on chip, interconnect, bandwidth optimization
66	Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson 0001, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi	Predictions of CMOS compatible on-chip optical interconnect.	SLIP	2005	DBLP DOI BibTeX RDF	CMOS compatible, on-chip, optical interconnect, trends
62	Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex	Interconnect exploration for future wire dominated technologies.	SLIP	2002	DBLP DOI BibTeX RDF	interconnect wire processing, intra/inter-memory interconnect, pareto-optimal energy/delay interconnect exploration
61	Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla, Zhi Zhu, Wayne P. Burleson	NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods.	SLIP	2004	DBLP DOI BibTeX RDF	on-chip, spice-based, network-on-chip, interconnects, signaling
61	Basel Halak, Santosh Shedabale, Hiran Ramakrishnan, Alexandre Yakovlev, Gordon Russell 0002	The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk.	SLIP	2008	DBLP DOI BibTeX RDF	cross-talk, interconnect, variability, Bit Error Rate(BER)
61	Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum Shamir	Interconnect-power dissipation in a microprocessor.	SLIP	2004	DBLP DOI BibTeX RDF	interconnect power, wire spacing, routing, low-power design
61	Michael D. Hutton	Interconnect prediction for programmable logic devices.	SLIP	2001	DBLP DOI BibTeX RDF	interconnect prodiction, wireability, architecture, programmable logic device
60	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Interconnect power and delay optimization by dynamic programming in gridded design rules.	ISPD	2010	DBLP DOI BibTeX RDF	gridded design rules, interconnect sizing and spacing, power-delay optimization, dynamic programming, interconnect optimization
60	Edmund Lee 0002, Guy Lemieux, Shahriar Mirabbasi	Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	routing design, FPGA, computer-aided design, interconnect design, FPGA interconnect
60	Narender Hanchate, Nagarajan Ranganathan	Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Game theory, gate sizing, transmission lines, crosstalk noise, interconnect models, interconnect delay
60	Emrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi	Time-Domain Simulation of Variational Interconnect Models.	ISQED	2002	DBLP DOI BibTeX RDF	simulation, Interconnect, variational models, reduced order modeling
59	Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma	Interconnect Tuning Strategies for High-Performance Ics.	DATE	1998	DBLP DOI BibTeX RDF
56	Wim Heirman, Joni Dambre, Jan Van Campenhout	Synthetic traffic generation as a tool for dynamic interconnect evaluation.	SLIP	2007	DBLP DOI BibTeX RDF	dynamic interconnect requirements, reconfigurable interconnect, synthetic traffic generation
56	Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex	Impact of interconnect resistance increase on system performance of low power and high performance designs.	SLIP	2006	DBLP DOI BibTeX RDF	interconnect sizing, interconnect technology evaluation, power-delay trade-off, wire sizing
56	Jens Lienig	Interconnect and current density stress: an introduction to electromigration-aware design.	SLIP	2005	DBLP DOI BibTeX RDF	interconnect, layout, physical design, electromigration, current density, interconnect reliability
56	Arthur Nieuwoudt, Yehia Massoud	Investigating the Design, Performance, and Reliability of Multi-Walled Carbon Nanotube Interconnect.	ISQED	2008	DBLP DOI BibTeX RDF	Mutli-walled carbon nanotubes, nanotube interconnect, interconnect, interconnect reliability
56	Boyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy	Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form.	ASP-DAC	2007	DBLP DOI BibTeX RDF	moment-matching methods, passive interconnect macromodeling, descriptor form, passive model order reduction, projection-based truncated balanced realization method, large RLC interconnect circuits, Lur'e equation, algebraic Riccati equations, generalized Lyapunov equations, passivity preservation, congruence transformation, large scale interconnect circuit, linear systems, structure information, Krylov-subspace methods, block structure, balanced truncation
56	Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko	Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA redundancy, interconnect faults, fault tolerance, yield enhancement, interconnect model, yield prediction, catastrophic faults, FPGA interconnect
55	Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topaloglu	Is overlay error more important than interconnect variations in double patterning?	SLIP	2009	DBLP DOI BibTeX RDF	double patterning lithography, interconnect variations, overlay
55	Bill R. Bottoms	Interconnect solutions for TeraScale computing.	SLIP	2009	DBLP DOI BibTeX RDF	interconnect
55	Puneet Gupta 0001, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester	Investigation of performance metrics for interconnect stack architectures.	SLIP	2004	DBLP DOI BibTeX RDF	back-end metrics, interconnect stacks, via blockage, throughput, energy, bandwidth
55	Md. Sajjad Rahaman, Masud H. Chowdhury	Improved ber performance in intra-chip rf/wireless interconnect systems.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	RF interconnect, intra-chip channel, wireless interconnect, interleaver, error control coding, channel coding
55	Roger D. Chamberlain, Mark A. Franklin, Praveen Krishnamurthy, Abhijit Mahajan	VLSI Photonic Ring Multicomputer Interconnect: Architecture and Signal Processing Performance.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	VLSI photonics, signal processing performance, multicomputer interconnect architecture, optical interconnect
55	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh	A Scalable Communication-Centric SoC Interconnect Architecture.	ISQED	2004	DBLP DOI BibTeX RDF	switch-based interconnect, butterfly fat-tree, global wire delay, System on chip, interconnect architecture, timing closure
55	Andrew B. Kahng, Kei Masuko, Sudhakar Muddu	Analytical delay models for VLSI interconnects under ramp input.	ICCAD	1996	DBLP DOI BibTeX RDF	SPICE-computed delay, VLSI routing topologies layout, analytical delay models, arbitrary interconnect trees, interconnect transfer function, performance-driven synthesis, ramp input, source-sink delays, VLSI, Elmore delay, interconnect delays, VLSI interconnects, RLC interconnections
54	Yehia Massoud, Arthur Nieuwoudt	Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits.	ACM J. Emerg. Technol. Comput. Syst.	2006	DBLP DOI BibTeX RDF	nanotube bundle, interconnect, inductance, Carbon nanotube, resistance
54	Yu Cao 0001, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester	Improved a priori interconnect predictions and technology extrapolation in the GTX system.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
54	Jinhwan Jeon, Daehong Kim, Dongwan Shin, Kiyoung Choi	High-level synthesis under multi-cycle interconnect delay.	ASP-DAC	2001	DBLP DOI BibTeX RDF
54	James D. Meindl	XXI Century Gigascale Integration (GSI) : The Interconnect Problem.	ARVLSI	1999	DBLP DOI BibTeX RDF
53	Jian Li 0061, Rajesh K. Gupta 0001	An Algorithm To Determine Mutually Exclusive Operations In Behavioral Descriptions.	DATE	1998	DBLP DOI BibTeX RDF
51	Wenyi Feng, Jonathan W. Greene	Post-placement interconnect entropy: how many configuration bits does a programmable logic device need?	SLIP	2006	DBLP DOI BibTeX RDF	switching requirement, FPGAs, lower bound, entropy, interconnect, placement, rent's rule, programmable interconnect
51	N. P. van der Meijs, T. Smedes	Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits.	ICCAD	1996	DBLP DOI BibTeX RDF	Physical Design Verification, Interconnect Resistance Extraction, Interconnect Capacitance Extraction, Substrate Resistance Extraction, Interconnect Modeling
50	Yu Hu 0002, King Ho Tam, Tong Jing, Lei He 0001	Fast dual-vdd buffering based on interconnect prediction and sampling.	SLIP	2007	DBLP DOI BibTeX RDF	routing, low power, interconnect, buffer insertion, dual-Vdd
50	Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand	Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry.	SLIP	2005	DBLP DOI BibTeX RDF	wire-length distribution model, routing, interconnect, rent
50	Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex	Interconnect width selection for deep submicron designs using the table lookup method.	SLIP	2004	DBLP DOI BibTeX RDF	interconnect sizing, power-delay trade-off, wire sizing
50	Ajay Joshi, Jeffrey A. Davis	A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI).	SLIP	2004	DBLP DOI BibTeX RDF	interconnect area, wire sharing, time-division multiplexing
50	Vikas Chandra, Anthony Xu, Herman Schmit	A low power approach to system level pipelined interconnect design.	SLIP	2004	DBLP DOI BibTeX RDF	pipelined interconnect, low power, voltage scaling
50	Chao-Yang Yeh, Malgorzata Marek-Sadowska	Sequential delay budgeting with interconnect prediction.	SLIP	2003	DBLP DOI BibTeX RDF	delay budgeting, sequential circuits, interconnect prediction
50	Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham	A hierarchical three-way interconnect architecture for hexagonal processors.	SLIP	2003	DBLP DOI BibTeX RDF	Y architecture, Y tree, interconnect architecture
50	Shankar Balachandran, Dinesh Bhatia	A-priori wirelength and interconnect estimation based on circuit characteristics.	SLIP	2003	DBLP DOI BibTeX RDF	routing demand, placement, wirelength, interconnect estimation
50	Phillip Christie, José Pineda de Gyvez	Pre-layout prediction of interconnect manufacturability.	SLIP	2001	DBLP DOI BibTeX RDF	design, reliability, interconnect, theory, yield, Rent's rule, critical areas
50	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for SRAM cluster interconnect testing at board level.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
49	Andrew B. Kahng, Bao Liu 0001, Xu Xu 0001	Statistical crosstalk aggressor alignment aware interconnect delay calculation.	SLIP	2006	DBLP DOI BibTeX RDF
49	Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain, Rebecca Berman, Peng Liu 0016, Michael C. Huang 0001, Hui Wu, Eby G. Friedman, Gary Wicks, Duncan Moore	An intra-chip free-space optical interconnect.	ISCA	2010	DBLP DOI BibTeX RDF	free-space optical interconnect, intra-chip, 3d
49	Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. N. Srikant	INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations.	CASES	2007	DBLP DOI BibTeX RDF	interconnect, energy modeling, energy-aware scheduling, clustered VLIW processors
49	Neal K. Bambha, Shuvra S. Bhattacharyya	Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	scheduling, task graphs, interconnect synthesis, Embedded multiprocessors
49	Ankireddy Nalamalpu, Wayne P. Burleson	Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters.	ISPD	2001	DBLP DOI BibTeX RDF	methodology, timing, interconnect, buffering
49	Ian G. Harris, Russell Tessier	Interconnect testing in cluster-based FPGA architectures.	DAC	2000	DBLP DOI BibTeX RDF	field-programmable gate arrray, interconnect testing, hierarchical test
48	Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee 0001, Jwu E. Chen	IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
48	Chun-Ying Lai, Shyh-Kang Jeng, Yao-Wen Chang, Chia-Chun Tsai	Inductance extraction for general interconnect structures.	ISCAS	2006	DBLP DOI BibTeX RDF
48	Geetanjali Kshirsagar, Masud H. Chowdhury	Optical Interconnect Technology; Photons Based Signal Communication.	APCCAS	2006	DBLP DOI BibTeX RDF
48	Fei Li 0003, Yan Lin 0001, Lei He 0001	Vdd programmability to reduce FPGA interconnect power.	ICCAD	2004	DBLP DOI BibTeX RDF
48	Navaratnasothie Selvakkumaran, Phiroze N. Parakh, George Karypis	Perimeter-degree: a priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement.	SLIP	2003	DBLP DOI BibTeX RDF	interconnection complexity, multilevel global placement, nonhomogeneity, perimeter-degree, congestion, routability
48	Akis Doganis	Interconnect Statistical Modeling: Structures and Measurement Methodologies.	VLSI Design	2000	DBLP DOI BibTeX RDF
48	Jianmin Li, Chung-Kuan Cheng	Routability improvement using dynamic interconnect architecture.	FCCM	1995	DBLP DOI BibTeX RDF
48	Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera	Worst-case delay analysis considering the variability of transistors and interconnects.	ISPD	2007	DBLP DOI BibTeX RDF	worst-case delay, interconnect, process variation
46	Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand	Impact of interconnect length changes on effective materials properties (dielectric constant).	SLIP	2007	DBLP DOI BibTeX RDF	performance, routing, interconnect, cycle time, interconnect model, rent, path delay
46	David Yeager, Darius Chiu, Guy G. Lemieux	Congestion estimation and localization in FPGAS: a visual tool for interconnect prediction.	SLIP	2007	DBLP DOI BibTeX RDF	congestion estimation, congestion localization, interconnect prediction, FPGA routing, FPGA interconnect
46	Dennis Sylvester	Measurement techniques and interconnect estimation.	SLIP	2000	DBLP DOI BibTeX RDF	capacitance measurement, interconnect characterization, noise measurement, process variation, interconnect estimation
45	Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny	Timing optimization in logic with interconnect.	SLIP	2008	DBLP DOI BibTeX RDF	interconnect, logic circuits, timing optimization, repeaters, logical effort
45	Andrew B. Kahng, Rasit Onur Topaloglu	Generation of design guarantees for interconnect matching.	SLIP	2006	DBLP DOI BibTeX RDF	design guarantee generation, interconnect matching
45	Viet H. Nguyen, Phillip Christie	The impact of interstratal interconnect density on the performance of three-dimensional integrated circuits.	SLIP	2005	DBLP DOI BibTeX RDF	interstratal interconnect, 3D-IC, system-level
45	Luca Daniel, Chin Siong Ong, Sok Chay Low, Kwok Hong Lee, Jacob White 0001	Geometrically parameterized interconnect performance models for interconnect synthesis.	ISPD	2002	DBLP DOI BibTeX RDF	parametrized model order reduction, interconnect synthesis
45	Ingrid Verbauwhede, M.-C. Frank Chang	Reconfigurable interconnect for next generation systems.	SLIP	2002	DBLP DOI BibTeX RDF	architectures, reconfiguration, interconnect, design methods, power efficiency
45	Qinwei Xu, Pinaki Mazumder	Novel interconnect modeling by using high-order compact finite difference methods.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	differential quadrature method, discrete interconnect modeling, passivity, interconnect modeling, transient simulation
45	Jason Cong, Lei He 0001, Cheng-Kok Koh, David Zhigang Pan	Global interconnect sizing and spacing with consideration of coupling capacitance.	ICCAD	1997	DBLP DOI BibTeX RDF	GISS solutions, asymmetric wire sizing, delay reduction, fringing capacitances, global interconnect sizing and spacing, global wire sizing, interconnect delay minimization, multiple nets, optimal wire sizing, spacing solution, symmetric effective fringing properties, VLSI, coupling capacitance
44	Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown	Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow.	SLIP	2006	DBLP DOI BibTeX RDF
44	N. S. Nagaraj	Dealing with interconnect process variations.	SLIP	2005	DBLP DOI BibTeX RDF
44	Joshua Hursey, Timothy Mattox, Andrew Lumsdaine	Interconnect agnostic checkpoint/restart in open MPI.	HPDC	2009	DBLP DOI BibTeX RDF	checkpoint coordination protocol, fault tolerance, MPI, shared memory, rollback-recovery, infiniband, myrinet, high speed interconnect, checkpoint/restart
44	Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Diederik Verkest	Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor.	VLSI Design	2008	DBLP DOI BibTeX RDF	Interconnect-Aware Design, Low Power, Processor Architecture, Energy-Aware Design
44	Frank Huebbers, Ali Dasdan, Yehea I. Ismail	Computation of accurate interconnect process parameter values for performance corners under process variations.	DAC	2006	DBLP DOI BibTeX RDF	sorners, delay, interconnect, STA, variations
44	Akshay Sharma, Katherine Compton, Carl Ebeling, Scott Hauck	Exploration of pipelined FPGA interconnect structures.	FPGA	2004	DBLP DOI BibTeX RDF	PipeRoute, pipelined FPGA, pipelined interconnect, registered routing, architecture explorations
44	Shalini Ghosh, F. Joel Ferguson	Estimating detection probability of interconnect opens using stuck-at tests.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	break fault, interconnect open, stuck-at test
44	Kavel M. Büyüksahin, Farid N. Najm	High-level power estimation with interconnect effects.	ISLPED	2000	DBLP DOI BibTeX RDF	high-level power estimation, interconnect capacitance estimation, register transfer level (RTL) power estimation
43	Chiu-Wing Sham, Evangeline F. Y. Young	Area reduction by deadspace utilization on interconnect optimized floorplan.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	area reduction, Floorplanning
43	Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen, Narayanan Vijaykrishnan, Yehia Massoud	Assessing carbon nanotube bundle interconnect for future FPGA architectures.	DATE	2007	DBLP DOI BibTeX RDF
43	Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David T. Blaauw	Statistical interconnect metrics for physical-design optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
43	Vishal Suthar, Shantanu Dutt	Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions.	VTS	2006	DBLP DOI BibTeX RDF
43	N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell	Benchmarks for Interconnect Parasitic Resistance and Capacitance.	ISQED	2003	DBLP DOI BibTeX RDF
43	John Marty Emmert, Stanley Baumgart, Pankaj Kataria, Andrew M. Taylor, Charles E. Stroud, Miron Abramovici	On-Line Fault Tolerance for FPGA Interconnect with Roving STARs.	DFT	2001	DBLP DOI BibTeX RDF
43	Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas	Impact of interconnect variations on the clock skew of a gigahertz microprocessor.	DAC	2000	DBLP DOI BibTeX RDF
43	Frank W. Angelotti	Generating interconnect models from prototype hardware.	ITC	1998	DBLP DOI BibTeX RDF
43	Jessica Qian, Satyamurthy Pullela, Lawrence T. Pillage	Modeling the "Effective capacitance" for the RC interconnect of CMOS gates.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
43	Tai A. Ly, W. Lloyd Elwood, Emil F. Girczyc	A Generalized Interconnect Model for Data Path Synthesis.	DAC	1990	DBLP DOI BibTeX RDF
43	Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley	Efficient tiling patterns for reconfigurable gate arrays.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA hexagonal octagonal, tiling interconnect
39	Robert Fischbach, Jens Lienig, Tilo Meister	From 3D circuit technologies and data structures to interconnect prediction.	SLIP	2009	DBLP DOI BibTeX RDF	3d floorplanning, three-dimensional circuits, data structures, 3d integration, interconnect prediction
39	Peng Sun, Rong Luo	Closed-form solution for timing analysis of process variations on SWCNT interconnect.	SLIP	2009	DBLP DOI BibTeX RDF	interconnect, process variation, timing analysis, carbon nanotube, closed-form
39	Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy 0001	Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates.	ISLPED	2007	DBLP DOI BibTeX RDF	signal slope, interconnect, gate delay, subthreshold operation
39	James D. Z. Ma, Lei He 0001	Simultaneous signal and power routing under K model.	SLIP	2001	DBLP DOI BibTeX RDF	net ordering, on-chip inductance, shield insertion, interconnect estimation, interconnect design
39	Jianhua Shao, Richard M. M. Chen	MCM Interconnect Design Using Two-Pole Approximation.	DATE	1998	DBLP DOI BibTeX RDF	Two-Pole Approximation, Interconnect Optimization, Interconnect Design
39	Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi	PRIMA: passive reduced-order interconnect macromodeling algorithm.	ICCAD	1997	DBLP DOI BibTeX RDF	MPVL, PRIMA, RLC interconnect circuits, block Arnoldi technique, driver-load models, guaranteed passivity, macromodel passivity, macromodel stability, passive reduced-order interconnect macromodeling algorithm, path tracing algorithm, reduced order N-port models, simulation, CAD, integrated circuit layout, frequency domain, circuit stability
39	Steven D. Corey, Andrew T. Yang	Automatic netlist extraction for measurement-based characterization of off-chip interconnect.	ICCAD	1996	DBLP DOI BibTeX RDF	MCM substrate-level interconnect circuitry, SPICE netlist, automatic netlist extraction, linear circuits, measured time domain refectometry data, measurement-based characterization, microstrip circuits, multiport system, off-chip interconnect, reflection transmission, time-domain scattering parameters, user-specified cutoff frequency, delay, crosstalk, circuit simulator, multichip modules, nonlinear circuits