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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 374 occurrences of 220 keywords
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Results
Found 270 publication records. Showing 270 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
48 | Franco Fummi, Donatella Sciuto |
Implicit test pattern generation constrained to cellular automata embedding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 54-59, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
implicit test pattern generation, cellular automata embedding, test sequence identification, autonomous finite state machine, off-line self-testable circuit, BIST strategy, deterministic test sequences, MCNC benchmarks, controller, built-in self test, stuck-at faults, ASIC design, circuit under test |
47 | Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch |
An optimized BIST test pattern generator for delay testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 94-100, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
BIST test pattern generator, robust delay fault coverage, single input change test sequence, compatible inputs, optimization, delays, built-in self-test, fault detection, delay testing, test length, area overhead, circuit under test |
44 | Fidel Muradali, Janusz Rajski |
A self-driven test structure for pseudorandom testing of non-scan sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 17-25, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
self-driven test structure, primary inputs, nonscan sequential circuits, test point structure, parallel pseudorandom test patterns, test mode flag, stuck-at fault coverage, ISCAS-89 benchmarks, logic testing, built-in self test, integrated circuit testing, design for testability, sequential circuits, BIST, automatic testing, circuit under test |
44 | Nur A. Touba, Edward J. McCluskey |
Test point insertion based on path tracing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 2-8, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
probabilistic techniques, primary inputs, insertion methods, VLSI, VLSI, fault diagnosis, logic testing, logic testing, probability, built-in self test, timing, integrated circuit testing, BIST, automatic testing, fault coverage, test point insertion, path tracing, circuit-under-test |
41 | Irith Pomeranz, Sudhakar M. Reddy |
On methods to match a test pattern generator to a circuit-under-test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(3), pp. 432-444, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
40 | Mark C. Hansen, John P. Hayes |
High-level test generation using physically-induced faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 20-28, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high-level test generation, physically-induced faults, industry-standard single stuck-line faults, independent functional faults, near-minimal size, fault diagnosis, logic testing, integrated circuit testing, design for testability, automatic testing, functional tests, failure analysis, benchmark circuits, circuit under test |
39 | Nicola Nicolici, Bashir M. Al-Hashimi |
Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(6), pp. 721-734, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Digital systems testing, design for test, low power circuits |
36 | Chih-Ang Chen, Sandeep K. Gupta |
Efficient BIST TPG design and test set compaction via input reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8), pp. 692-705, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
32 | Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Constantin Halatsis |
A concurrent built-in self-test architecture based on a self-testing RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 54(1), pp. 69-78, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Jeanne Tongbong, Salvador Mir, Jean-Louis Carbonéro |
Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 731-736, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Wen Ching Wu, Chung-Len Lee 0001, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir |
Oscillation Ring Delay Test for High Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(1-2), pp. 147-155, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
oscillation ring testing, sensitized path, robust path dealy fault, hazard-free path delay fault, multiple reconvergent fanout, flunk lines, stuck at fault, delay fault testing, gate delay fault |
32 | Biranchinath Sahu, Abhijit Chatterjee |
Automatic Test Generation for Analog Circuits Using Compact Test Transfer Function Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 405-410, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
test transfer function model, AC testing, optimization, fault simulation |
31 | Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich |
Design based analog testing by Characteristic Observation Inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 620-626, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
30 | Ramakrishna Voorakaranam, Abhijit Chatterjee |
Hierarchical Test Generation for Analog Circuits Using Incremental Test Development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 296-303, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Kewal K. Saluja, Rajiv Sharma, Charles R. Kime |
A concurrent testing technique for digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(12), pp. 1250-1260, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
28 | Chun-Yi Lee, Hung-Mao Lin, Fang-Min Wang, James Chien-Mo Li |
Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 835-840, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
systematic defects, cyclic-column parity row selection technique, built-in self tested circuits, cyclic scan chains, masking circuitry, transient errors, circuit under test, nanometer technologies |
27 | Savita Banerjee, Srimat T. Chakradhar, Rabindra K. Roy |
Synchronous Test Generation Model for Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 178-185, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
26 | Andrej A. Morosov, Michael Gössel, Krishnendu Chakrabarty, Bhargab B. Bhattacharya |
Design of Parameterizable Error-Propagating Space Compactors for Response Observation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 48-53, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Ender Yilmaz, Sule Ozev |
Adaptive test elimination for analog/RF circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 720-725, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
adaptive testing |
26 | Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich |
Analog testing by characteristic observation inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9), pp. 1353-1368, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
24 | Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici |
Scan Architecture for Shift and Capture Cycle Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 129-137, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Hyunwoo Cho, Seh-Woong Jeong, Fabio Somenzi, Carl Pixley |
Synchronizing sequences and symbolic traversal techniques in test generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(1), pp. 19-31, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
implicit state enumeration, multiple observation time, test generation, Binary decision diagram, synchronizing sequence |
24 | Mohamed A. El-Gamal, Hany L. Abdel-Malek, M. A. Sorour |
A neural-network-based approach for post-fabrication circuit tuning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Comput. Appl. ![In: Neural Comput. Appl. 14(1), pp. 25-35, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Clustering, Neural networks, Feature selection, Self organizing maps, Circuit tuning |
24 | Alexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty |
Robust Space Compaction of Test Responses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 254-259, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
23 | Hamidreza Hashempour, Fred J. Meyer, Fabrizio Lombardi |
Test Time Reduction in a Manufacturing Environment by Combining BIST and ATE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 186-194, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
23 | Hideyuki Ichihara, Kozo Kinoshita, Koji Isodono, Shigeki Nishikawa |
Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 329-334, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Achintya Halder, Abhijit Chatterjee |
Automated Test Generation and Test Point Selection for Specification Test of Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 401-406, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
test point selection, automated test generation, specification testing, parametric failure |
23 | Karim Arabi, Bozena Kaminska |
Testing analog and mixed-signal integrated circuits using oscillation-test method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7), pp. 745-753, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
23 | Karim Arabi, Bozena Kaminska |
Oscillation-test strategy for analog and mixed-signal integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 476-482, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
circuit oscillations, oscillation test strategy, analog ICs, low-cost test method, oscillation frequency deviation, wafer-probe testing, final production testing, ASIC testing, integrated circuit testing, operational amplifiers, analogue integrated circuits, mixed analogue-digital integrated circuits, production testing, analogue-digital conversion, mixed-signal ICs |
23 | Hyoung B. Min, Hwei-Tsu Ann Luh, William A. Rogers |
Hierarchical test pattern generation: a cost model and implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7), pp. 1029-1039, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
23 | Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Toshiyuki Matsunaga |
A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 320-325, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
marginal delay, test generation, combinational circuit, gate delay faults |
22 | Lei Li 0036, Krishnendu Chakrabarty |
Test set embedding for deterministic BIST using a reconfigurable interconnection network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(9), pp. 1289-1305, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 149-152, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey |
Optimized reseeding by seed ordering and encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2), pp. 264-270, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Aiman H. El-Maleh, Khaled Al-Utaibi |
An efficient test relaxation technique for synchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(6), pp. 933-940, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Aiman H. El-Maleh, Khaled Al-Utaibi |
On efficient extraction of partially specified test sets for synchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 545-548, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Aiman H. El-Maleh, Khaled Al-Utaibi |
An Efficient Test Relaxation Technique for Synchronous Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 179-185, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Bjørg Reppen, Einar J. Aas |
Combined probabilistic testability calculation and compact test generation for PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(3), pp. 215-227, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
probabilistic testability, Fault coverage, test pattern generation, programmable logic arrays |
21 | Haralampos-G. D. Stratigopoulos, Salvador Mir, Ahcène Bounceur |
Evaluation of Analog/RF Test Measurements at the Design Stage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(4), pp. 582-590, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy |
Fault Diagnosis and Fault Model Aliasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 206-211, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Lei Li 0036, Krishnendu Chakrabarty |
Deterministic BIST Based on a Reconfigurable Interconnection Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 460-469, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar |
Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(5), pp. 633-636, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Irith Pomeranz, Sudhakar M. Reddy |
Functional test generation for delay faults in combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 3(2), pp. 231-248, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
function-robust tests, functional delay fault model, delay faults, path delay faults, robust tests |
21 | Sverre Wichlund, Frank Berntsen, Einar J. Aas |
Scan Test Response Compaction Combined with Diagnosis Capabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 235-246, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Scan compression, Diagnosis, ATPG, Yield, Design for test, ATE |
20 | Manobendra Nath Mondal, Animesh Basak Chowdhury, Manjari Pradhan, Susmita Sur-Kolay, Bhargab B. Bhattacharya |
Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 28th IEEE Asian Test Symposium, ATS 2019, Kolkata, India, December 10-13, 2019, pp. 25-30, 2019, IEEE, 978-1-7281-2695-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Jishun Kuang, Ouyang Xiong, Zhiqiang You |
A Novel BIST Scheme Using Test Vectors Applied by Circuit-under-Test Itself. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 17th IEEE Asian Test Symposium, ATS 2008, Sapporo, Japan, November 24-27, 2008, pp. 75-80, 2008, IEEE Computer Society, 978-0-7695-3396-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Irith Pomeranz, Sudhakar M. Reddy |
A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics - Join Them, Baltimore, Maryland, USA, October 17-21, 1993, pp. 998-1007, 1993, IEEE Computer Society, 0-7803-1430-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
20 | Haibo Wang 0005, Suchitra Kulkarni, Spyros Tragoudas |
On-line Testing Field Programmable Analog Array Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1340-1348, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Madhu K. Iyer, Michael L. Bushnell |
Effect of Noise on Analog Circuit Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 15(1-2), pp. 11-22, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
analog test generation, noise analysis |
20 | Nilanjan Mukherjee 0001, Tapan J. Chakraborty, Sudipta Bhawmik |
A BIST scheme for the detection of path-delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 422-431, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
20 | Zhaoliang Pan, Melvin A. Breuer |
Estimating Error Rate in Defective Logic Using Signature Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(5), pp. 650-661, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Binning integrated circuits, effective yield, signature testing, error rate, error tolerance, yield loss |
20 | Sudarshan Bahukudumbi, Krishna Bharath |
A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 804-807, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Christophe Fagot, Olivier Gascuel, Patrick Girard 0001, Christian Landrault |
A Ring Architecture Strategy for BIST Test Pattern Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(3), pp. 223-231, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
pseudo-random testing, deterministic BIST, logic BIST |
20 | Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty |
Synthesis of single-output space compactors for scan-based sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10), pp. 1171-1179, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Mustapha Slamani, Karim Arabi |
Reducing Test Time in the High-Volume Production of Analog Circuits using Efficient Test-Vector Generation and Interpolation Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(5), pp. 417-425, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
analog circuits testing, interpolation technique, sensitivity analysis, frequency domain analysis, test vectors generation |
20 | Paulo F. Flores, Horácio C. Neto, Krishnendu Chakrabarty, João Marques-Silva 0001 |
Test pattern generation for width compression in BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 114-118, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Irith Pomeranz, Sudhakar M. Reddy |
Built-in test generation for synchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 421-426, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
comparison units, built-in self-test, synchronous sequential circuits, at-speed test |
20 | Yukihiro Kamiya, Takayuki Miki, Yoshihiro Iwadare |
Randomness Properties of Partial \gamma-\beta Planes as LSI Test Inputs and their Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AAECC ![In: Applied Algebra, Algebraic Algorithms and Error-Correcting Codes, 11th International Symposium, AAECC-11, Paris, France, July 17-22, 1995, Proceedings, pp. 297-311, 1995, Springer, 3-540-60114-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada |
Electric field for detecting open leads in CMOS logic circuits by supply current testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2995-2998, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Sasikumar Cherubal, Abhijit Chatterjee |
Parametric Fault Diagnosis for Analog Systems Using Functional Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 195-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Bapiraju Vinnakota, Jason Andrews |
Fast fault translation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(1), pp. 122-133, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Yukiya Miura, Hiroshi Yamazaki |
A Low-Loss Built-In Current Sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(1-2), pp. 39-48, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
low-voltage LSIs, multiple power supplies, IDDQ testing, Built-in current sensor |
19 | Lei Li 0036, Krishnendu Chakrabarty, Nur A. Touba |
Test data compression using dictionaries with selective entries and fixed-length indices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 8(4), pp. 470-490, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
reduced pin-count testing, SoC testing, test application time, Embedded core testing, test data volume |
19 | Andrzej Krasniewski, Slawomir Pilarski |
Circular self-test path: a low-cost BIST technique for VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(1), pp. 46-55, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
19 | Ehsan Atoofian, Zainalabedin Navabi |
A Test Approach for Look-Up Table Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 21(1), pp. 141-146, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
LUT testing, TPG with LE, BIST, memory testing, FPGA testing |
19 | Ehsan Atoofian, Zainalabedin Navabi |
A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 84-89, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed |
Low-Transition Test Pattern Generation for BIST-Based Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(3), pp. 303-315, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Low power pattern generation, Test generation, Built-in tests, Testing strategies, Random generation |
18 | Lei Li 0036, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan |
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 53-58, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Christophe Fagot, Olivier Gascuel, Patrick Girard 0001, Christian Landrault |
A Ring Architecture Strategy for BIST Test Pattern Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 418-423, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Slawomir Pilarski, Andrzej Krasniewski, Tiko Kameda |
Estimating testing effectiveness of the circular self-test path technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(10), pp. 1301-1316, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
18 | Pramodchandran N. Variyam, Abhijit Chatterjee |
Test generation for comprehensive testing of linear analog circuits using transient response sampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 382-385, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Implicit functional testing, Transient testing, Linear Analog Circuits |
17 | Ramakrishna Voorakaranam, Abhijit Chatterjee |
Test Generation for Accurate Prediction of Analog Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 137-142, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Lei Li 0036, Zhanglei Wang, Krishnendu Chakrabarty |
Scan-BIST based on cluster analysis and the encoding of repeating sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(1), pp. 4:1-4:21, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
clustering test data volume, Built-in self-test (BIST), test compression |
17 | Katherine Shu-Min Li, Chung-Len Lee 0001, Tagin Jiang, Chauchin Su, Jwu E. Chen |
Finite State Machine Synthesis for At-Speed Oscillation Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 360-365, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas |
A new built-in TPG method for circuits with random patternresistant faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(7), pp. 859-866, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Xiaowei Li 0001, Huawei Li 0001, Yinghua Min |
Reducing Power Dissipation during At-Speed Test Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 116-, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Test-pair Ordering, Power Dissipation, At-speed Test |
17 | Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray |
Deterministic Built-in Pattern Generation for Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 15(1-2), pp. 97-114, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Comma coding, pattern decoding, statistical encoding, BIST, Huffman coding, run-length encoding, embedded-core testing, sequential circuit testing |
17 | Yeong-Ruey Shieh, Cheng-Wen Wu |
DC control and observation structures for analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 120-126, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
level-sensitive scan-design, test points, DC voltage levels, diagnosis capability, calibration process, read-out voltage levels, VLSI, VLSI, fault diagnosis, controllability, controllability, integrated circuit testing, calibration, observability, observability, analog circuits, mixed signal circuits, mixed analogue-digital integrated circuits |
17 | Donghoon Han, Selim Sermet Akbay, Soumendu Bhattacharya, Abhijit Chatterjee, William R. Eisenstadt |
On-Chip Self-Calibration of RF Circuits Using Specification-Driven Built-In Self Test (S-BIST). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 106-111, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Soon-Jyh Chang, Chung-Len Lee 0001, Jwu E. Chen |
Structural Fault Based Specification Reduction for Testing Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(6), pp. 571-581, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
specification-based test, analog test, fault-based test, test cost reduction |
17 | Dimitrios Kagaris, Fillia Makedon, Spyros Tragoudas |
A method for pseudo-exhaustive test pattern generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9), pp. 1170-1178, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
17 | Zhuo Zhang 0008, Sudhakar M. Reddy, Irith Pomeranz |
Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 817-822, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi |
A concurrent testing method for NoC switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1171-1176, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | P. Kalpana, K. Gunavathi |
A Novel Specification Based Test Pattern Generation Using Genetic Algorithm and Wavelets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 504-507, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar |
Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 22-27, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Irith Pomeranz, Sudhakar M. Reddy |
Functional test generation for delay faults in combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 687-694, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
gate-level realizations, logic testing, delays, test generation, test generators, combinational circuits, fault simulated, logic CAD, delay faults, functional fault model, functional test generation |
17 | Wen-Ben Jone, Anita Gleason |
Analysis of Hamming count compaction scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(4), pp. 373-384, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
index vector, spectral coefficients, Built-in self test, compaction, syndrome |
16 | Weiguang Sheng, Liyi Xiao, Zhigang Mao |
Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 502-507, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
genetic algorithm, optimization, soft error, multi-objective |
16 | Érika F. Cota, Luigi Carro, Marcelo Lubaszewski |
A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 184-188, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | C. P. Ravikumar, Nitin Kakkar, Saurabh Chopra |
Mutual Testing based on Wavelet Transforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 347-352, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Mutual Testing, Discrete Wavelet Transform, At-Speed Testing |
16 | Achintya Halder, Abhijit Chatterjee |
Specification Based Digital Compatible Built-in Test of Embedded Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 344-, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Alvernon Walker |
A Step Response Based Mixed-Signal BIST Approach . ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 329-337, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Maoxiang Yi, Huaguo Liang, Kaihua Zhan, Cuiyun Jiang |
Optimal LFSR-Coding Test Data Compression Based on Test Cube Dividing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSE (2) ![In: Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, CSE 2009, Vancouver, BC, Canada, August 29-31, 2009, pp. 698-702, 2009, IEEE Computer Society, 978-1-4244-5334-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Zhanglei Wang, Krishnendu Chakrabarty |
Test Data Compression Using Selective Encoding of Scan Slices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(11), pp. 1429-1440, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Rashid Rashidzadeh, Majid Ahmadi, William C. Miller |
Test and Measurement of Analog and RF Cores in Mixed-Signal SoC Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10), pp. 1855-1865, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Sverre Wichlund, Frank Berntsen, Einar J. Aas |
Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 119-127, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel |
Implementing a Scheme for External Deterministic Self-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 101-106, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Deterministic self-test, external BIST, test data compression, test resource partitioning |
16 | Michael Gössel, Krishnendu Chakrabarty, Vitalij Ocheretnij, Andreas Leininger |
A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(6), pp. 611-622, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
algebraic analysis, intervals of test vectors, fault diagnosis, linearity, MISR |
16 | Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya |
Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 487-492, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Lei Li 0036, Krishnendu Chakrabarty |
Test Data Compression Using Dictionaries with Fixed-Length Indices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 219-224, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
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