Search results for "circuit-under-test"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
48	Franco Fummi, Donatella Sciuto	Implicit test pattern generation constrained to cellular automata embedding.	VTS	1997	DBLP DOI BibTeX RDF	implicit test pattern generation, cellular automata embedding, test sequence identification, autonomous finite state machine, off-line self-testable circuit, BIST strategy, deterministic test sequences, MCNC benchmarks, controller, built-in self test, stuck-at faults, ASIC design, circuit under test
47	Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch	An optimized BIST test pattern generator for delay testing.	VTS	1997	DBLP DOI BibTeX RDF	BIST test pattern generator, robust delay fault coverage, single input change test sequence, compatible inputs, optimization, delays, built-in self-test, fault detection, delay testing, test length, area overhead, circuit under test
44	Fidel Muradali, Janusz Rajski	A self-driven test structure for pseudorandom testing of non-scan sequential circuits.	VTS	1996	DBLP DOI BibTeX RDF	self-driven test structure, primary inputs, nonscan sequential circuits, test point structure, parallel pseudorandom test patterns, test mode flag, stuck-at fault coverage, ISCAS-89 benchmarks, logic testing, built-in self test, integrated circuit testing, design for testability, sequential circuits, BIST, automatic testing, circuit under test
44	Nur A. Touba, Edward J. McCluskey	Test point insertion based on path tracing.	VTS	1996	DBLP DOI BibTeX RDF	probabilistic techniques, primary inputs, insertion methods, VLSI, VLSI, fault diagnosis, logic testing, logic testing, probability, built-in self test, timing, integrated circuit testing, BIST, automatic testing, fault coverage, test point insertion, path tracing, circuit-under-test
41	Irith Pomeranz, Sudhakar M. Reddy	On methods to match a test pattern generator to a circuit-under-test.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
40	Mark C. Hansen, John P. Hayes	High-level test generation using physically-induced faults.	VTS	1995	DBLP DOI BibTeX RDF	high-level test generation, physically-induced faults, industry-standard single stuck-line faults, independent functional faults, near-minimal size, fault diagnosis, logic testing, integrated circuit testing, design for testability, automatic testing, functional tests, failure analysis, benchmark circuits, circuit under test
39	Nicola Nicolici, Bashir M. Al-Hashimi	Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Digital systems testing, design for test, low power circuits
36	Chih-Ang Chen, Sandeep K. Gupta	Efficient BIST TPG design and test set compaction via input reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
32	Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Constantin Halatsis	A concurrent built-in self-test architecture based on a self-testing RAM.	IEEE Trans. Reliab.	2005	DBLP DOI BibTeX RDF
32	Jeanne Tongbong, Salvador Mir, Jean-Louis Carbonéro	Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical model.	DATE	2007	DBLP DOI BibTeX RDF
32	Wen Ching Wu, Chung-Len Lee 0001, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir	Oscillation Ring Delay Test for High Performance Microprocessors.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	oscillation ring testing, sensitized path, robust path dealy fault, hazard-free path delay fault, multiple reconvergent fanout, flunk lines, stuck at fault, delay fault testing, gate delay fault
32	Biranchinath Sahu, Abhijit Chatterjee	Automatic Test Generation for Analog Circuits Using Compact Test Transfer Function Models.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	test transfer function model, AC testing, optimization, fault simulation
31	Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich	Design based analog testing by Characteristic Observation Inference.	ICCAD	1995	DBLP DOI BibTeX RDF
30	Ramakrishna Voorakaranam, Abhijit Chatterjee	Hierarchical Test Generation for Analog Circuits Using Incremental Test Development.	VTS	1999	DBLP DOI BibTeX RDF
29	Kewal K. Saluja, Rajiv Sharma, Charles R. Kime	A concurrent testing technique for digital circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
28	Chun-Yi Lee, Hung-Mao Lin, Fang-Min Wang, James Chien-Mo Li	Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies.	ASP-DAC	2007	DBLP DOI BibTeX RDF	systematic defects, cyclic-column parity row selection technique, built-in self tested circuits, cyclic scan chains, masking circuitry, transient errors, circuit under test, nanometer technologies
27	Savita Banerjee, Srimat T. Chakradhar, Rabindra K. Roy	Synchronous Test Generation Model for Asynchronous Circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF
26	Andrej A. Morosov, Michael Gössel, Krishnendu Chakrabarty, Bhargab B. Bhattacharya	Design of Parameterizable Error-Propagating Space Compactors for Response Observation.	VTS	2001	DBLP DOI BibTeX RDF
26	Ender Yilmaz, Sule Ozev	Adaptive test elimination for analog/RF circuits.	DAC	2009	DBLP DOI BibTeX RDF	adaptive testing
26	Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich	Analog testing by characteristic observation inference.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
24	Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici	Scan Architecture for Shift and Capture Cycle Power Reduction.	DFT	2002	DBLP DOI BibTeX RDF
24	Hyunwoo Cho, Seh-Woong Jeong, Fabio Somenzi, Carl Pixley	Synchronizing sequences and symbolic traversal techniques in test generation.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	implicit state enumeration, multiple observation time, test generation, Binary decision diagram, synchronizing sequence
24	Mohamed A. El-Gamal, Hany L. Abdel-Malek, M. A. Sorour	A neural-network-based approach for post-fabrication circuit tuning.	Neural Comput. Appl.	2005	DBLP DOI BibTeX RDF	Clustering, Neural networks, Feature selection, Self organizing maps, Circuit tuning
24	Alexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty	Robust Space Compaction of Test Responses.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
23	Hamidreza Hashempour, Fred J. Meyer, Fabrizio Lombardi	Test Time Reduction in a Manufacturing Environment by Combining BIST and ATE.	DFT	2002	DBLP DOI BibTeX RDF
23	Hideyuki Ichihara, Kozo Kinoshita, Koji Isodono, Shigeki Nishikawa	Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs.	VLSI Design	2003	DBLP DOI BibTeX RDF
23	Achintya Halder, Abhijit Chatterjee	Automated Test Generation and Test Point Selection for Specification Test of Analog Circuits.	ISQED	2004	DBLP DOI BibTeX RDF	test point selection, automated test generation, specification testing, parametric failure
23	Karim Arabi, Bozena Kaminska	Testing analog and mixed-signal integrated circuits using oscillation-test method.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
23	Karim Arabi, Bozena Kaminska	Oscillation-test strategy for analog and mixed-signal integrated circuits.	VTS	1996	DBLP DOI BibTeX RDF	circuit oscillations, oscillation test strategy, analog ICs, low-cost test method, oscillation frequency deviation, wafer-probe testing, final production testing, ASIC testing, integrated circuit testing, operational amplifiers, analogue integrated circuits, mixed analogue-digital integrated circuits, production testing, analogue-digital conversion, mixed-signal ICs
23	Hyoung B. Min, Hwei-Tsu Ann Luh, William A. Rogers	Hierarchical test pattern generation: a cost model and implementation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
23	Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Toshiyuki Matsunaga	A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	marginal delay, test generation, combinational circuit, gate delay faults
22	Lei Li 0036, Krishnendu Chakrabarty	Test set embedding for deterministic BIST using a reconfigurable interconnection network.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
22	Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey	Optimized reseeding by seed ordering and encoding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
22	Aiman H. El-Maleh, Khaled Al-Utaibi	An efficient test relaxation technique for synchronous sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
22	Aiman H. El-Maleh, Khaled Al-Utaibi	On efficient extraction of partially specified test sets for synchronous sequential circuits.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
22	Aiman H. El-Maleh, Khaled Al-Utaibi	An Efficient Test Relaxation Technique for Synchronous Sequential Circuits.	VTS	2003	DBLP DOI BibTeX RDF
22	Bjørg Reppen, Einar J. Aas	Combined probabilistic testability calculation and compact test generation for PLAs.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	probabilistic testability, Fault coverage, test pattern generation, programmable logic arrays
21	Haralampos-G. D. Stratigopoulos, Salvador Mir, Ahcène Bounceur	Evaluation of Analog/RF Test Measurements at the Design Stage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
21	Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy	Fault Diagnosis and Fault Model Aliasing.	ISVLSI	2005	DBLP DOI BibTeX RDF
21	Lei Li 0036, Krishnendu Chakrabarty	Deterministic BIST Based on a Reconfigurable Interconnection Network.	ITC	2003	DBLP DOI BibTeX RDF
21	Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar	Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
21	Irith Pomeranz, Sudhakar M. Reddy	Functional test generation for delay faults in combinational circuits.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	function-robust tests, functional delay fault model, delay faults, path delay faults, robust tests
21	Sverre Wichlund, Frank Berntsen, Einar J. Aas	Scan Test Response Compaction Combined with Diagnosis Capabilities.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Scan compression, Diagnosis, ATPG, Yield, Design for test, ATE
20	Manobendra Nath Mondal, Animesh Basak Chowdhury, Manjari Pradhan, Susmita Sur-Kolay, Bhargab B. Bhattacharya	Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test.	ATS	2019	DBLP DOI BibTeX RDF
20	Jishun Kuang, Ouyang Xiong, Zhiqiang You	A Novel BIST Scheme Using Test Vectors Applied by Circuit-under-Test Itself.	ATS	2008	DBLP DOI BibTeX RDF
20	Irith Pomeranz, Sudhakar M. Reddy	A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test.	ITC	1993	DBLP DOI BibTeX RDF
20	Haibo Wang 0005, Suchitra Kulkarni, Spyros Tragoudas	On-line Testing Field Programmable Analog Array Circuits.	ITC	2004	DBLP DOI BibTeX RDF
20	Madhu K. Iyer, Michael L. Bushnell	Effect of Noise on Analog Circuit Testing.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	analog test generation, noise analysis
20	Nilanjan Mukherjee 0001, Tapan J. Chakraborty, Sudipta Bhawmik	A BIST scheme for the detection of path-delay faults.	ITC	1998	DBLP DOI BibTeX RDF
20	Zhaoliang Pan, Melvin A. Breuer	Estimating Error Rate in Defective Logic Using Signature Analysis.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Binning integrated circuits, effective yield, signature testing, error rate, error tolerance, yield loss
20	Sudarshan Bahukudumbi, Krishna Bharath	A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores.	VLSI Design	2005	DBLP DOI BibTeX RDF
20	Christophe Fagot, Olivier Gascuel, Patrick Girard 0001, Christian Landrault	A Ring Architecture Strategy for BIST Test Pattern Generation.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	pseudo-random testing, deterministic BIST, logic BIST
20	Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty	Synthesis of single-output space compactors for scan-based sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
20	Mustapha Slamani, Karim Arabi	Reducing Test Time in the High-Volume Production of Analog Circuits using Efficient Test-Vector Generation and Interpolation Techniques.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	analog circuits testing, interpolation technique, sensitivity analysis, frequency domain analysis, test vectors generation
20	Paulo F. Flores, Horácio C. Neto, Krishnendu Chakrabarty, João Marques-Silva 0001	Test pattern generation for width compression in BIST.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
20	Irith Pomeranz, Sudhakar M. Reddy	Built-in test generation for synchronous sequential circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	comparison units, built-in self-test, synchronous sequential circuits, at-speed test
20	Yukihiro Kamiya, Takayuki Miki, Yoshihiro Iwadare	Randomness Properties of Partial \gamma-\beta Planes as LSI Test Inputs and their Implementations.	AAECC	1995	DBLP DOI BibTeX RDF
19	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada	Electric field for detecting open leads in CMOS logic circuits by supply current testing.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
19	Sasikumar Cherubal, Abhijit Chatterjee	Parametric Fault Diagnosis for Analog Systems Using Functional Mapping.	DATE	1999	DBLP DOI BibTeX RDF
19	Bapiraju Vinnakota, Jason Andrews	Fast fault translation.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
19	Yukiya Miura, Hiroshi Yamazaki	A Low-Loss Built-In Current Sensor.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	low-voltage LSIs, multiple power supplies, IDDQ testing, Built-in current sensor
19	Lei Li 0036, Krishnendu Chakrabarty, Nur A. Touba	Test data compression using dictionaries with selective entries and fixed-length indices.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	reduced pin-count testing, SoC testing, test application time, Embedded core testing, test data volume
19	Andrzej Krasniewski, Slawomir Pilarski	Circular self-test path: a low-cost BIST technique for VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
19	Ehsan Atoofian, Zainalabedin Navabi	A Test Approach for Look-Up Table Based FPGAs.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	LUT testing, TPG with LE, BIST, memory testing, FPGA testing
19	Ehsan Atoofian, Zainalabedin Navabi	A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
18	Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed	Low-Transition Test Pattern Generation for BIST-Based Applications.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Low power pattern generation, Test generation, Built-in tests, Testing strategies, Random generation
18	Lei Li 0036, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan	Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores.	VLSI Design	2005	DBLP DOI BibTeX RDF
18	Christophe Fagot, Olivier Gascuel, Patrick Girard 0001, Christian Landrault	A Ring Architecture Strategy for BIST Test Pattern Generation.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
18	Slawomir Pilarski, Andrzej Krasniewski, Tiko Kameda	Estimating testing effectiveness of the circular self-test path technique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
18	Pramodchandran N. Variyam, Abhijit Chatterjee	Test generation for comprehensive testing of linear analog circuits using transient response sampling.	ICCAD	1997	DBLP DOI BibTeX RDF	Implicit functional testing, Transient testing, Linear Analog Circuits
17	Ramakrishna Voorakaranam, Abhijit Chatterjee	Test Generation for Accurate Prediction of Analog Specifications.	VTS	2000	DBLP DOI BibTeX RDF
17	Lei Li 0036, Zhanglei Wang, Krishnendu Chakrabarty	Scan-BIST based on cluster analysis and the encoding of repeating sequences.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	clustering test data volume, Built-in self-test (BIST), test compression
17	Katherine Shu-Min Li, Chung-Len Lee 0001, Tagin Jiang, Chauchin Su, Jwu E. Chen	Finite State Machine Synthesis for At-Speed Oscillation Testability.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
17	Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas	A new built-in TPG method for circuits with random patternresistant faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
17	Xiaowei Li 0001, Huawei Li 0001, Yinghua Min	Reducing Power Dissipation during At-Speed Test Application.	DFT	2001	DBLP DOI BibTeX RDF	Test-pair Ordering, Power Dissipation, At-speed Test
17	Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray	Deterministic Built-in Pattern Generation for Sequential Circuits.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	Comma coding, pattern decoding, statistical encoding, BIST, Huffman coding, run-length encoding, embedded-core testing, sequential circuit testing
17	Yeong-Ruey Shieh, Cheng-Wen Wu	DC control and observation structures for analog circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	level-sensitive scan-design, test points, DC voltage levels, diagnosis capability, calibration process, read-out voltage levels, VLSI, VLSI, fault diagnosis, controllability, controllability, integrated circuit testing, calibration, observability, observability, analog circuits, mixed signal circuits, mixed analogue-digital integrated circuits
17	Donghoon Han, Selim Sermet Akbay, Soumendu Bhattacharya, Abhijit Chatterjee, William R. Eisenstadt	On-Chip Self-Calibration of RF Circuits Using Specification-Driven Built-In Self Test (S-BIST).	IOLTS	2005	DBLP DOI BibTeX RDF
17	Soon-Jyh Chang, Chung-Len Lee 0001, Jwu E. Chen	Structural Fault Based Specification Reduction for Testing Analog Circuits.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	specification-based test, analog test, fault-based test, test cost reduction
17	Dimitrios Kagaris, Fillia Makedon, Spyros Tragoudas	A method for pseudo-exhaustive test pattern generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
17	Zhuo Zhang 0008, Sudhakar M. Reddy, Irith Pomeranz	Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes.	ASP-DAC	2007	DBLP DOI BibTeX RDF
17	Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi	A concurrent testing method for NoC switches.	DATE	2006	DBLP DOI BibTeX RDF
17	P. Kalpana, K. Gunavathi	A Novel Specification Based Test Pattern Generation Using Genetic Algorithm and Wavelets.	VLSI Design	2005	DBLP DOI BibTeX RDF
17	Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar	Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters.	VTS	1999	DBLP DOI BibTeX RDF
17	Irith Pomeranz, Sudhakar M. Reddy	Functional test generation for delay faults in combinational circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	gate-level realizations, logic testing, delays, test generation, test generators, combinational circuits, fault simulated, logic CAD, delay faults, functional fault model, functional test generation
17	Wen-Ben Jone, Anita Gleason	Analysis of Hamming count compaction scheme.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	index vector, spectral coefficients, Built-in self test, compaction, syndrome
16	Weiguang Sheng, Liyi Xiao, Zhigang Mao	Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm.	DAC	2009	DBLP DOI BibTeX RDF	genetic algorithm, optimization, soft error, multi-objective
16	Érika F. Cota, Luigi Carro, Marcelo Lubaszewski	A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester.	DATE	1999	DBLP DOI BibTeX RDF
16	C. P. Ravikumar, Nitin Kakkar, Saurabh Chopra	Mutual Testing based on Wavelet Transforms.	VLSI Design	2003	DBLP DOI BibTeX RDF	Mutual Testing, Discrete Wavelet Transform, At-Speed Testing
16	Achintya Halder, Abhijit Chatterjee	Specification Based Digital Compatible Built-in Test of Embedded Analog Circuits.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
16	Alvernon Walker	A Step Response Based Mixed-Signal BIST Approach .	DFT	2001	DBLP DOI BibTeX RDF
16	Maoxiang Yi, Huaguo Liang, Kaihua Zhan, Cuiyun Jiang	Optimal LFSR-Coding Test Data Compression Based on Test Cube Dividing.	CSE (2)	2009	DBLP DOI BibTeX RDF
16	Zhanglei Wang, Krishnendu Chakrabarty	Test Data Compression Using Selective Encoding of Scan Slices.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
16	Rashid Rashidzadeh, Majid Ahmadi, William C. Miller	Test and Measurement of Analog and RF Cores in Mixed-Signal SoC Environment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
16	Sverre Wichlund, Frank Berntsen, Einar J. Aas	Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor.	DFT	2006	DBLP DOI BibTeX RDF
16	Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel	Implementing a Scheme for External Deterministic Self-Test.	VTS	2005	DBLP DOI BibTeX RDF	Deterministic self-test, external BIST, test data compression, test resource partitioning
16	Michael Gössel, Krishnendu Chakrabarty, Vitalij Ocheretnij, Andreas Leininger	A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	algebraic analysis, intervals of test vectors, fault diagnosis, linearity, MISR
16	Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya	Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults.	VLSI Design	2004	DBLP DOI BibTeX RDF
16	Lei Li 0036, Krishnendu Chakrabarty	Test Data Compression Using Dictionaries with Fixed-Length Indices.	VTS	2003	DBLP DOI BibTeX RDF