Search results for "flip-flops"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
173	Aliakbar Ghadiri, Hamid Mahmoodi-Meimand	Pre-capturing static pulsed flip-flops.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
168	Razak Hossain, Leszek D. Wronski, Alexander Albicki	Low power design using double edge triggered flip-flops.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
158	Jaehyun Kim, Youngsoo Shin	Minimizing leakage power in sequential circuits by using mixed Vt flip-flops.	ICCAD	2007	DBLP DOI BibTeX RDF
141	Chau-Shen Chen, TingTing Hwang	Layout Driven Selection and Chaining of Partial Scan Flip-Flops.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	design for testability, matching, placement, global routing, partial scan, digital testing, layout optimization
133	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Test sequence compaction by reduced scan shift and retiming.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	reduced scan shift, full scan designed circuits, computational complexity, logic testing, timing, transformation, design for testability, sequential circuits, sequential circuit, logic CAD, flip-flops, flip-flops, retiming, computing time, test length, test sequence generation, test sequence compaction
132	Chen Kong Teh, Mototsugu Hamada, Tetsuya Fujita, Hiroyuki Hara, N. Ikumi, Yukihito Oowaki	Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
125	Kwang-Ting Cheng	Partial scan designs without using a separate scan clock.	VTS	1995	DBLP DOI BibTeX RDF	flip-flop selection method, flip-flop test generation method, scan registers ordering, scan-shifting concept, test vector compaction, delay fault detection, cycle breaking, logic testing, delays, timing, design for testability, logic design, automatic testing, DFT, fault coverage, flip-flops, circuit optimisation, boundary scan testing, scan chain, combinatorial optimization problem, test generation algorithm, partial scan designs, system clock
124	Safar Hatami, Hamed Abrishami, Massoud Pedram	Statistical timing analysis of flip-flops considering codependent setup and hold times.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	codependency, hold time, piecewise linear, statistical static timing analysis (SSTA), probability, process variations, setup time
124	Vivek Joshi, David T. Blaauw, Dennis Sylvester	Soft-edge flip-flops for improved timing yield: design and optimization.	ICCAD	2007	DBLP DOI BibTeX RDF
124	Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy 0001	Energy recovery clocking scheme and flip-flops for ultra low-energy applications.	ISLPED	2003	DBLP DOI BibTeX RDF	flip-flop, clock, clock tree, energy recovery, adiabatic
121	Bo Fu, Paul Ampadu	Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency.	ISCAS	2007	DBLP DOI BibTeX RDF
121	Martin Hansson, Atila Alvandpour	Comparative Analysis of Process Variation Impact on Flip-Flop Power-Performance.	ISCAS	2007	DBLP DOI BibTeX RDF
116	Seiken Yano	Unified scan design with scannable memory arrays.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	unified scan design, scannable memory arrays, single scan path, scan operation time, scannable register file, fault diagnosis, design for testability, design-for-testability, automatic testing, logic CAD, flip-flops, flip-flops, arrays, shift registers, integrated memory circuits
116	Zhen Chen, Dong Xiang, Boxue Yin	A power-effective scan architecture using scan flip-flops clustering and post-generation filling.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	test, low power, design for test, scan design
111	Xiaoding Chen, Michael S. Hsiao	Energy-Efficient Logic BIST Based on State Correlation Analysis.	VTS	2003	DBLP DOI BibTeX RDF
107	Branka Medved Rogina, Bozidar Vojnovic	Metastability evaluation method by propagation delay distribution measurement.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	propagation delay distribution measurement, edge-triggered flip-flops, input signals time relationship, output signal timing characteristics, analytical representation, propagation delay density distribution function, fault events, integrated propagation delay density distribution function, flip-flop normal propagation delay, resolution time constant, automatic data acquisition, complex architecture microsystems, MTBF, latch devices, custom CMOS, VLSI, VLSI, fault diagnosis, logic testing, delays, logic design, asynchronous circuits, flip-flops, data acquisition, failure analysis, reliability analysis, graphical representation, metastability, PLD, asynchronous logic, integrated circuit reliability, statistical measurement
106	Sudipta Bhawmik, Indradeep Ghosh	A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF
105	Mohamed A. Elgamel, Tarek Darwish, Magdy A. Bayoumi	Noise Tolerant Low Power Dynamic TSPCL D Flip-Flops.	ISVLSI	2002	DBLP DOI BibTeX RDF	noise, power, flip-flop, deep submicron
104	Amir Moradi 0001, Mahmoud Salmasizadeh, Mohammad T. Manzuri Shalmani	Power Analysis Attacks on MDPL and DRSL Implementations.	ICISC	2007	DBLP DOI BibTeX RDF	DRSL, MDPL, Side-Channel Attacks, DPA, flip-flop
104	Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen	Cost-free scan: a low-overhead scan path design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
104	Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik	Integration of partial scan and built-in self-test.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	test points, built-in self-test, design for testability, partial scan
102	Jun Seomun, Jae-Hyun Kim, Youngsoo Shin	Skewed Flip-Flop and Mixed-Vt Gates for Minimizing Leakage in Sequential Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
99	Saihua Lin, Huazhong Yang, Rong Luo	A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
99	Hao Zheng, Kewal K. Saluja, Rajiv Jain	Test application time reduction for scan based sequential circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	scan based sequential circuits, single clock configuration, nonscan flip-flops, test vector length, nonatomic two-clock scan method, test generation environment, logic testing, sequential circuits, flip-flops, clocks, partial scan, boundary scan testing, test application time
99	Arun Balakrishnan, Srimat T. Chakradhar	Partial scan design for technology mapped circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	technology mapped circuits, scan flip-flops selection, multiple memory elements, library block, integer linear program formulation, production VLSI circuits, VLSI, graph theory, linear programming, design for testability, integer programming, logic design, logic CAD, VLSI design, flip-flops, integrated circuit design, circuit CAD, integrated logic circuits, functional specifications, partial scan design
99	László T. Kóczy, Rita Lovassy	Fuzzy Flip-Flops Revisited.	IFSA (2)	2007	DBLP DOI BibTeX RDF	J-K flip-flop, logical normal forms, IVFS, Fuzzy logic
99	Narendra Devta-Prasanna, Sudhakar M. Reddy, Arun Gunda, P. Krishnamurthy, Irith Pomeranz	Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
99	Sujit Dey, Srimat T. Chakradhar	Design of testable sequential circuits by repositioning flip-flops.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	cycle-breaking, flip-flop minimization, sequential redundancy, design for testability, sequential circuits, retiming, partial scan, strongly connected components, redundant fault
98	Kuo-Hsing Cheng, Yung-Hsiang Lin	A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
97	Dong Xiang, Kaiwei Li, Hideo Fujiwara	Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
96	Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, Kun-Cheng Wu	Fault modeling and testing of retention flip-flops in low power designs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
94	Hsing-Chung Liang, Chung-Len Lee	An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
94	Kee Sup Kim, Charles R. Kime	Partial scan flip-flop selection by use of empirical testability.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	scan flip-flop selection, serial scan, design for testability, testability, partial scan
92	Jason P. Hurst, Nick Kanopoulos	Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	flip-flop sharing, standard scan path, standard scan path design, two-vector test sets, VLSI, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, sequential circuits, flip-flops, integrated logic circuits, sequential machines, delay fault testing
90	Andrzej Hlawiczka, Michal Kopec	Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	serial seeding, linear hybrid cellular automata, n-cell CA register, p CdSR registers, cellular automata quasi shift register, PCASR, n-bit input sequence, logic testing, cellular automata, integrated circuit testing, automatic test pattern generation, application specific integrated circuits, polynomials, polynomial, logic CAD, cost, TPG, flip-flops, flip-flops, shift registers, pattern generators, integrated circuit economics
89	Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy 0001	Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability.	ASP-DAC	2006	DBLP DOI BibTeX RDF
89	Raúl Jiménez, Pilar Parra Fernández, Pedro Sanmartín, Antonio J. Acosta 0001	A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches.	PATMOS	2002	DBLP DOI BibTeX RDF
88	Aliakbar Ghadiri, Hamid Mahmoodi-Meimand	Dual-Edge Triggered Static Pulsed Flip-Flops.	VLSI Design	2005	DBLP DOI BibTeX RDF
86	Qingwei Wu, Michael S. Hsiao	State Variable Extraction and Partitioning to Reduce Problem Complexity for ATPG and Design Validation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
86	Qingwei Wu, Michael S. Hsiao	State Variable Extraction to Reduce Problem Complexity for ATPG and Design Validation.	ITC	2004	DBLP DOI BibTeX RDF
86	Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen	Cost-free scan: a low-overhead scan path design methodology.	ICCAD	1995	DBLP DOI BibTeX RDF	Testing, DFT, Scan design
84	Arunprasad Venkatraman, Rajesh Garg, Sunil P. Khatri	A robust, fast pulsed flip-flop design.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	flip-flop, latch
82	Krishna B. Rajan, David E. Long, Miron Abramovici	Increasing testability by clock transformation (getting rid of those darn states).	VTS	1996	DBLP DOI BibTeX RDF	clock transformation, sequential test generation, darn states, easy-to-reach states, logic testing, partitioning, design for testability, sequential circuits, DFT, fault coverage, testability, flip-flops, flip-flops, clocks, logic partitioning
82	Arun Balakrishnan, Srimat T. Chakradhar	Retiming with logic duplication transformation: theory and an application to partial scan.	VLSI Design	1996	DBLP DOI BibTeX RDF	logic duplication transformation, partial scan application, RLD configurations, RLD transformation, testability metrics, scan flip-flops, sequential circuit design, linear programming, timing, integer programming, logic design, sequential circuits, logic CAD, polynomial time algorithm, integer linear program, flip-flops, retiming, integrated circuit design, circuit CAD, integrated logic circuits, objective function
82	S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault	Test configurations to enhance the testability of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	shift operation, scan register, test operation, modified flip-flops, ISCAS89 benchmarks, multiconfiguration, triconfiguration, dynamic generation, logic testing, controllability, design for testability, design for testability, sequential circuits, sequential circuits, observability, observability, DFT, fault coverage, flip-flops, minimisation, scan designs, test application time, test vector
82	Stanley Habib, Quan Xu	Technology mapping algorithms for sequential circuits using look-up table based FPGAS.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	technology mapping algorithms, FPGAS, routing results, adjacent combinational parts, field programmable gate arrays, delays, sequential circuits, sequential circuits, logic CAD, network routing, flip-flops, flip-flops, circuit layout CAD, table lookup, time delay, look-up table
82	Kaoru Hirota	Fuzzy logic and its hardware implementation.	ANNES	1995	DBLP DOI BibTeX RDF	fuzzy logic circuit, fuzzy inference chips, fuzzy flip flops, fuzzy logic, fuzzy logic, fuzzy systems, flip-flops, logic circuits, hardware implementation
82	Sridhar Narayanan, Melvin A. Breuer	Asynchronous multiple scan chain.	VTS	1995	DBLP DOI BibTeX RDF	asynchronous multiple scan chains, scan flip-flops, control complexity, I/O pin count, DFT method, logic IC, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, flip-flops, integrated logic circuits, scan designs, boundary scan testing, test application time
81	Cheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang	Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA.	ASP-DAC	2008	DBLP DOI BibTeX RDF
81	Saihua Lin, Hongli Gao, Huazhong Yang	Low Clock Swing D Flip-Flops Design by Using Output Control and MTCMOS.	PATMOS	2006	DBLP DOI BibTeX RDF
81	Antonio G. M. Strollo, Ettore Napoli, Davide De Caro	New clock-gating techniques for low-power flip-flops.	ISLPED	2000	DBLP DOI BibTeX RDF	flip-fops, CMOS digital integrated circuits, transition probability, low-power circuits
81	Eugeniusz Eberbach	Neural Network Processing Elements as a New Generation of "Flip-Flops".	ICCI	1991	DBLP DOI BibTeX RDF
80	Jing Wang 0001, Gianluca Meloni, Gianluca Berrettini, Luca Potì, Antonella Bogoni	All-Optical Clocked Flip-Flops Exploiting SOA-Based SR Latches and Logic Gates.	OSC	2009	DBLP DOI BibTeX RDF	optical flip-flop, optical logic gate, optical signal processing, semiconductor optical amplifier (SOA)
79	Omid Sarbishei, Mohammad Maymandi-Nejad	Power-Delay Efficient Overlap-Based Charge-Sharing Free Pseudo-Dynamic D Flip-Flops.	ISCAS	2007	DBLP DOI BibTeX RDF
77	Jingye Xu, Abinash Roy, Masud H. Chowdhury	Power Consumption Analysis of Flip-flop Based Interconnect Pipelining.	ISCAS	2007	DBLP DOI BibTeX RDF
77	Varun Arora, Indranil Sengupta 0001	A Unified Approach to Partial Scan Design using Genetic Algorithm.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
77	Priyank Kalla, Maciej J. Ciesielski	A comprehensive approach to the partial scan problem using implicitstate enumeration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
73	Yinshui Xia, Lun-Yao Wang, A. E. A. Almaini	A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	multiple-valued clock, CMOS, flip-flops, multiple-valued logic
71	Raúl Jiménez, Pilar Parra Fernández, Javier Castro-Ramirez, Manuel Sanchez-Raya, Antonio J. Acosta 0001	Optimization of Master-Slave Flip-Flops for High-Performance Applications.	PATMOS	2006	DBLP DOI BibTeX RDF
69	Juanjuan Chen, Xing Wei, Yunjian Jiang, Qiang Zhou 0001	Improve clock gating through power-optimal enable function selection.	DDECS	2009	DBLP DOI BibTeX RDF
69	Hamed Abrishami, Safar Hatami, Behnam Amelifard, Massoud Pedram	NBTI-aware flip-flop characterization and design.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	device aging, setup and hold times, static timing analysis, NBTI, circuit reliability
69	Vishwanadh Tirumalashetty, Hamid Mahmoodi	Clock Gating and Negative Edge Triggering for Energy Recovery Clock.	ISCAS	2007	DBLP DOI BibTeX RDF
69	Donald A. Joy, Maciej J. Ciesielski	Clock period minimization with wave pipelining.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
68	Jun Seomun, Jaehyun Kim, Youngsoo Shin	Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits.	DAC	2007	DBLP DOI BibTeX RDF
68	Sang-Dae Shin, Hun Choi, Bai-Sun Kong	Variable sampling window flip-flop for low-power application.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
68	Subhasish Mitra, Edward J. McCluskey	Design Diversity for Concurrent Error Detection in Sequential Logic Circuts.	VTS	2001	DBLP DOI BibTeX RDF
67	Srimat T. Chakradhar	Optimum retiming of large sequential circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	optimum retiming, large sequential circuits, unit delay model, optimum clock period, path graph, VLSI, linear programming, delays, timing, integer programming, sequential circuits, logic CAD, integer linear program, flip-flops, circuit CAD, fast algorithm, integrated logic circuits, circuit optimisation, VLSI circuits, linear program relaxation
66	Marius Padure, Sorin Cotofana, Stamatis Vassiliadis	Design and experimental results of a CMOS flip-flop featuring embedded threshold logic.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
66	Bill Pontikakis, Mohamed Nekili	A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
64	Frank F. Hsu, Janak H. Patel	A distance reduction approach to design for testability.	VTS	1995	DBLP DOI BibTeX RDF	distance reduction approach, center state, test function embedding technique, SFT techniques, logic testing, finite state machines, finite state machines, design for testability, design for testability, sequential circuits, sequential circuits, flip-flops, flip-flops, synthesis for testability, test function, average distance, DFT techniques
64	Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita	Resynthesis for sequential circuits designed with a specified initial state.	VTS	1995	DBLP DOI BibTeX RDF	specified initial state, retiming method, redundancy removal method, resynthesized circuit, input sequences, logic optimisation, timing, redundancy, sequential circuits, logic CAD, flip-flops, flip-flops, circuit optimisation, synchronous sequential circuits
64	Víctor H. Champac, Joan Figueras	Testability of floating gate defects in sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	floating gate defect testability, logic detectability conditions, defective transistors, logically untestable branches, scan path cell, CMOS latch cell, scan path flip-flops, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, simulated results, flip-flops, CMOS logic circuits, integrated circuit modelling, I/sub DDQ/ testing
64	Sudhir Dhawan, Ronald C. de Vries	Design of Self-Checking Sequential Machines.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	error transmission, self-checking sequential machines, design, error detection, flip-flops, flip-flops, sequential machines, excitation, memory elements
64	Krishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie 0001	Comparative analysis of NBTI effects on low power and high performance flip-flops.	ICCD	2008	DBLP DOI BibTeX RDF
64	László T. Kóczy, Rita Lovassy	Fuzzy Flip-Flops and Neural Nets?	FUZZ-IEEE	2007	DBLP DOI BibTeX RDF
64	Ko Yoshikawa, Yasuhiko Hagihara, Keisuke Kanamaru, Yuichi Nakamura 0002, Shigeto Inui, Takeshi Yoshimura	Timing optimization by replacing flip-flops to latches.	ASP-DAC	2004	DBLP DOI BibTeX RDF
64	Mircea R. Stan, Marco Barcella	MTCMOS with outer feedback (MTOF) flip-flops.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
64	Srimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal	An exact algorithm for selecting partial scan flip-flops.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	multiway search and integer linear program, partial scan, minimum feedback vertex set
62	James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De	Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.	ISLPED	2001	DBLP DOI BibTeX RDF	dual edge, low power, flip-flops, clocking, triggered, latches
62	Dejan Markovic, Borivoje Nikolic, Robert W. Brodersen	Analysis and design of low-energy flip-flops.	ISLPED	2001	DBLP DOI BibTeX RDF	digital CMOS, VLSI, low-power design, flip-flops, low-voltage
62	Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs	Identification of unsettable flip-flops for partial scan and faster ATPG.	ICCAD	1996	DBLP DOI BibTeX RDF	ISCAS89 circuits, deterministic test generation, difficult-to-set hip-hops, hip-hops, state elements, state justification, transformed circuits, unsettable flip-flops identification, logic testing, ATPG, partial scan, sequential circuits test generation
60	Ming Zhang 0017, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, Sanjay J. Patel	Sequential Element Design With Built-In Soft Error Resilience.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
60	Puneet Gupta 0001, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma	Layout-aware scan chain synthesis for improved path delay fault coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
60	Wei Li 0023, Seongmoon Wang, Srimat T. Chakradhar, Sudhakar M. Reddy	Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage.	VLSI Design	2005	DBLP DOI BibTeX RDF
60	Puneet Gupta 0001, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma	Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage.	ICCAD	2003	DBLP DOI BibTeX RDF
60	Prashant S. Parikh, Miron Abramovici	Testability-based partial scan analysis.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	testability cost, sensitivity analysis, partial scan
59	Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai	12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics.	ISLPED	2011	DBLP BibTeX RDF
58	Motoi Inaba, Koichi Tanno, Okihiko Ishizuka	Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits.	ISMVL	2002	DBLP DOI BibTeX RDF	Multi-valued flip-flop, Down literal circuit, Analog inverter, Voltage comparator, NMIN circuit
58	Dong Xiang, Yi Xu	Partial Reset for Synchronous Sequential Circuits Using Almost Independent Reset Signals.	VTS	2001	DBLP DOI BibTeX RDF
58	Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell	On variable clock methods for path delay testing of sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
57	Chuan Lin 0002, Hai Zhou 0001	Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains.	ASP-DAC	2007	DBLP DOI BibTeX RDF	delay padding, prescribed skew domains, optimal skew scheduling algorithm, domain assignment, sequential circuit, flip-flops, memory elements, clock period, clock skew scheduling
57	Elizabeth M. Rudnick, Janak H. Patel	A genetic approach to test application time reduction for full scan and partial scan circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	partial scan circuits, design-for-testability techniques, compact test set generation, genetic algorithms, genetic algorithms, logic testing, design for testability, logic design, sequential circuits, combinational circuits, DFT, flip-flops, test application time reduction, full scan circuits
55	Antonio G. M. Strollo, Ettore Napoli, Carlo Cimino	Analysis of power dissipation in double edge-triggered flip-flops.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
55	Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa	A unified approach in the analysis of latches and flip-flops for low-power systems.	ISLPED	1998	DBLP DOI BibTeX RDF	master-slave latch, optimization, timing, flip-flop, power measurement
52	Pramod Kumar Meher, Yajun Ha, Chiou-Yng Lee	An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials.	ASP-DAC	2009	DBLP DOI BibTeX RDF
52	Uthman Alsaiari, Resve A. Saleh	Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits.	ISQED	2008	DBLP DOI BibTeX RDF	Partitioning, Redundancy, Yield, Flip-Flop
52	Jiun-Kuan Wu, Tsung-Yi Wu, Liang-Ying Lu, Kuang-Yao Chen	IR Drop Reduction via a Flip-Flop Resynthesis Technique.	ISQED	2008	DBLP DOI BibTeX RDF	Peak Current Reduction, IR Drop, Clock Skew Scheduling
52	Michael Nicolaidis, Renaud Perez, Dan Alexandrescu	Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors.	VTS	2008	DBLP DOI BibTeX RDF	radiation hardened cells, soft errors, SEUs
52	Frederic Worm, Patrick Thiran, Paolo Ienne	Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs.	ISQED	2007	DBLP DOI BibTeX RDF
52	Seongmoon Wang, Srimat T. Chakradhar	A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF