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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 3674 occurrences of 1433 keywords
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Results
Found 5812 publication records. Showing 5812 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
88 | Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Bendix |
Prediction of interconnect adjacency distribution: derivation, validation, and applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 99-106, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect adjacency, interconnect pattern density, prediction, stochastic model, probability density function |
87 | Narender Hanchate, Nagarajan Ranganathan |
A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(3), pp. 711-739, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Game theory, transmission lines, crosstalk noise, interconnect models, wire sizing, interconnect delay |
77 | Ian O'Connor |
Optical solutions for system-level interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 79-88, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect technology, optical network on chip, optical interconnect |
75 | Desmond Kirkpatrick, Peter J. Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester |
The great interconnect buffering debate: are you a chicken or an ostrich? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 61, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
73 | Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex |
Global interconnect trade-off for technology over memory modules to application level: case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 125-132, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Pareto-optimal energy/delay interconnect exploration, interconnect wire processing, intra/inter-memory interconnect |
72 | Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Wright |
Prediction of interconnect pattern density distribution: derivation, validation, and applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 85-91, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
interconnect network prediction, interconnect pattern density, Stochastic model, probability density function |
70 | Xiang Qiu, Yuchun Ma, Xiangqing He, Xianlong Hong |
IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 873-876, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
interconnect power, piecewise model, slack |
69 | Marvin Tom, David Leong, Guy G. Lemieux |
Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 680-687, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
channel width constraints, clustering, field-programmable gate arrays (FPGA), packing |
68 | Jian Liu, Meigen Shen, Li-Rong Zheng 0001, Hannu Tenhunen |
System level interconnect design for network-on-chip using interconnect IPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 117-124, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
interconnect IP, network on chip, interconnect, bandwidth optimization |
66 | Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson 0001, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi |
Predictions of CMOS compatible on-chip optical interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 13-20, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
CMOS compatible, on-chip, optical interconnect, trends |
62 | Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex |
Interconnect exploration for future wire dominated technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 105-106, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
interconnect wire processing, intra/inter-memory interconnect, pareto-optimal energy/delay interconnect exploration |
61 | Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla, Zhi Zhu, Wayne P. Burleson |
NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 69-75, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
on-chip, spice-based, network-on-chip, interconnects, signaling |
61 | Basel Halak, Santosh Shedabale, Hiran Ramakrishnan, Alexandre Yakovlev, Gordon Russell 0002 |
The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 65-72, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
cross-talk, interconnect, variability, Bit Error Rate(BER) |
61 | Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum Shamir |
Interconnect-power dissipation in a microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 7-13, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect power, wire spacing, routing, low-power design |
61 | Michael D. Hutton |
Interconnect prediction for programmable logic devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 125-131, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
interconnect prodiction, wireability, architecture, programmable logic device |
60 | Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer |
Interconnect power and delay optimization by dynamic programming in gridded design rules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 153-160, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
gridded design rules, interconnect sizing and spacing, power-delay optimization, dynamic programming, interconnect optimization |
60 | Edmund Lee 0002, Guy Lemieux, Shahriar Mirabbasi |
Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 51(1), pp. 57-76, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
routing design, FPGA, computer-aided design, interconnect design, FPGA interconnect |
60 | Narender Hanchate, Nagarajan Ranganathan |
Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(8), pp. 1011-1023, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Game theory, gate sizing, transmission lines, crosstalk noise, interconnect models, interconnect delay |
60 | Emrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi |
Time-Domain Simulation of Variational Interconnect Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 419-424, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
simulation, Interconnect, variational models, reduced order modeling |
59 | Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma |
Interconnect Tuning Strategies for High-Performance Ics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 471-478, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
56 | Wim Heirman, Joni Dambre, Jan Van Campenhout |
Synthetic traffic generation as a tool for dynamic interconnect evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 65-72, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dynamic interconnect requirements, reconfigurable interconnect, synthetic traffic generation |
56 | Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex |
Impact of interconnect resistance increase on system performance of low power and high performance designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 85-90, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
interconnect sizing, interconnect technology evaluation, power-delay trade-off, wire sizing |
56 | Jens Lienig |
Interconnect and current density stress: an introduction to electromigration-aware design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 81-88, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
interconnect, layout, physical design, electromigration, current density, interconnect reliability |
56 | Arthur Nieuwoudt, Yehia Massoud |
Investigating the Design, Performance, and Reliability of Multi-Walled Carbon Nanotube Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 691-696, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Mutli-walled carbon nanotubes, nanotube interconnect, interconnect, interconnect reliability |
56 | Boyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy |
Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 355-360, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
moment-matching methods, passive interconnect macromodeling, descriptor form, passive model order reduction, projection-based truncated balanced realization method, large RLC interconnect circuits, Lur'e equation, algebraic Riccati equations, generalized Lyapunov equations, passivity preservation, congruence transformation, large scale interconnect circuit, linear systems, structure information, Krylov-subspace methods, block structure, balanced truncation |
56 | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko |
Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 138-148, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
FPGA redundancy, interconnect faults, fault tolerance, yield enhancement, interconnect model, yield prediction, catastrophic faults, FPGA interconnect |
55 | Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topaloglu |
Is overlay error more important than interconnect variations in double patterning? ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 3-10, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
double patterning lithography, interconnect variations, overlay |
55 | Bill R. Bottoms |
Interconnect solutions for TeraScale computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 1-2, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
interconnect |
55 | Puneet Gupta 0001, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester |
Investigation of performance metrics for interconnect stack architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 23-29, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
back-end metrics, interconnect stacks, via blockage, throughput, energy, bandwidth |
55 | Md. Sajjad Rahaman, Masud H. Chowdhury |
Improved ber performance in intra-chip rf/wireless interconnect systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 303-308, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
RF interconnect, intra-chip channel, wireless interconnect, interleaver, error control coding, channel coding |
55 | Roger D. Chamberlain, Mark A. Franklin, Praveen Krishnamurthy, Abhijit Mahajan |
VLSI Photonic Ring Multicomputer Interconnect: Architecture and Signal Processing Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 40(1), pp. 57-72, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
VLSI photonics, signal processing performance, multicomputer interconnect architecture, optical interconnect |
55 | Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh |
A Scalable Communication-Centric SoC Interconnect Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 343-348, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
switch-based interconnect, butterfly fat-tree, global wire delay, System on chip, interconnect architecture, timing closure |
55 | Andrew B. Kahng, Kei Masuko, Sudhakar Muddu |
Analytical delay models for VLSI interconnects under ramp input. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 30-36, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
SPICE-computed delay, VLSI routing topologies layout, analytical delay models, arbitrary interconnect trees, interconnect transfer function, performance-driven synthesis, ramp input, source-sink delays, VLSI, Elmore delay, interconnect delays, VLSI interconnects, RLC interconnections |
54 | Yehia Massoud, Arthur Nieuwoudt |
Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 2(3), pp. 155-196, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
nanotube bundle, interconnect, inductance, Carbon nanotube, resistance |
54 | Yu Cao 0001, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester |
Improved a priori interconnect predictions and technology extrapolation in the GTX system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(1), pp. 3-14, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
54 | Jinhwan Jeon, Daehong Kim, Dongwan Shin, Kiyoung Choi |
High-level synthesis under multi-cycle interconnect delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 662, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
54 | James D. Meindl |
XXI Century Gigascale Integration (GSI) : The Interconnect Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA, pp. 88-, 1999, IEEE Computer Society, 0-7695-0056-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
53 | Jian Li 0061, Rajesh K. Gupta 0001 |
An Algorithm To Determine Mutually Exclusive Operations In Behavioral Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 457-463, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
51 | Wenyi Feng, Jonathan W. Greene |
Post-placement interconnect entropy: how many configuration bits does a programmable logic device need? ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 41-48, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
switching requirement, FPGAs, lower bound, entropy, interconnect, placement, rent's rule, programmable interconnect |
51 | N. P. van der Meijs, T. Smedes |
Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 244-251, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Physical Design Verification, Interconnect Resistance Extraction, Interconnect Capacitance Extraction, Substrate Resistance Extraction, Interconnect Modeling |
50 | Yu Hu 0002, King Ho Tam, Tong Jing, Lei He 0001 |
Fast dual-vdd buffering based on interconnect prediction and sampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 95-102, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
routing, low power, interconnect, buffer insertion, dual-Vdd |
50 | Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand |
Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 43-50, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
wire-length distribution model, routing, interconnect, rent |
50 | Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex |
Interconnect width selection for deep submicron designs using the table lookup method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 41-44, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect sizing, power-delay trade-off, wire sizing |
50 | Ajay Joshi, Jeffrey A. Davis |
A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 64-68, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect area, wire sharing, time-division multiplexing |
50 | Vikas Chandra, Anthony Xu, Herman Schmit |
A low power approach to system level pipelined interconnect design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 45-52, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
pipelined interconnect, low power, voltage scaling |
50 | Chao-Yang Yeh, Malgorzata Marek-Sadowska |
Sequential delay budgeting with interconnect prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 23-30, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
delay budgeting, sequential circuits, interconnect prediction |
50 | Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham |
A hierarchical three-way interconnect architecture for hexagonal processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 133-139, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Y architecture, Y tree, interconnect architecture |
50 | Shankar Balachandran, Dinesh Bhatia |
A-priori wirelength and interconnect estimation based on circuit characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 77-84, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
routing demand, placement, wirelength, interconnect estimation |
50 | Phillip Christie, José Pineda de Gyvez |
Pre-layout prediction of interconnect manufacturability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 167-173, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
design, reliability, interconnect, theory, yield, Rent's rule, critical areas |
50 | Chen-Huan Chiang, Sandeep K. Gupta 0001 |
BIST TPG for SRAM cluster interconnect testing at board level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 58-65, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing |
49 | Andrew B. Kahng, Bao Liu 0001, Xu Xu 0001 |
Statistical crosstalk aggressor alignment aware interconnect delay calculation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 91-97, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
49 | Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain, Rebecca Berman, Peng Liu 0016, Michael C. Huang 0001, Hui Wu, Eby G. Friedman, Gary Wicks, Duncan Moore |
An intra-chip free-space optical interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 94-105, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
free-space optical interconnect, intra-chip, 3d |
49 | Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. N. Srikant |
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 238-247, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
interconnect, energy modeling, energy-aware scheduling, clustered VLIW processors |
49 | Neal K. Bambha, Shuvra S. Bhattacharyya |
Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 16(2), pp. 99-112, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
scheduling, task graphs, interconnect synthesis, Embedded multiprocessors |
49 | Ankireddy Nalamalpu, Wayne P. Burleson |
Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001, pp. 204-211, 2001, ACM, 1-58113-347-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
methodology, timing, interconnect, buffering |
49 | Ian G. Harris, Russell Tessier |
Interconnect testing in cluster-based FPGA architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 49-54, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
field-programmable gate arrray, interconnect testing, hierarchical test |
48 | Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee 0001, Jwu E. Chen |
IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2513-2525, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
48 | Chun-Ying Lai, Shyh-Kang Jeng, Yao-Wen Chang, Chia-Chun Tsai |
Inductance extraction for general interconnect structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
48 | Geetanjali Kshirsagar, Masud H. Chowdhury |
Optical Interconnect Technology; Photons Based Signal Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1426-1429, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
48 | Fei Li 0003, Yan Lin 0001, Lei He 0001 |
Vdd programmability to reduce FPGA interconnect power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 760-765, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
48 | Navaratnasothie Selvakkumaran, Phiroze N. Parakh, George Karypis |
Perimeter-degree: a priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 53-59, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
interconnection complexity, multilevel global placement, nonhomogeneity, perimeter-degree, congestion, routability |
48 | Akis Doganis |
Interconnect Statistical Modeling: Structures and Measurement Methodologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 150, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
48 | Jianmin Li, Chung-Kuan Cheng |
Routability improvement using dynamic interconnect architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 3rd IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '95), 19-21 April 1995, Napa Valley, CA, USA, pp. 61-67, 1995, IEEE Computer Society, 0-8186-7086-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
48 | Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera |
Worst-case delay analysis considering the variability of transistors and interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007, pp. 35-42, 2007, ACM, 978-1-59593-613-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
worst-case delay, interconnect, process variation |
46 | Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand |
Impact of interconnect length changes on effective materials properties (dielectric constant). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 73-80, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
performance, routing, interconnect, cycle time, interconnect model, rent, path delay |
46 | David Yeager, Darius Chiu, Guy G. Lemieux |
Congestion estimation and localization in FPGAS: a visual tool for interconnect prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 33-40, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
congestion estimation, congestion localization, interconnect prediction, FPGA routing, FPGA interconnect |
46 | Dennis Sylvester |
Measurement techniques and interconnect estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), April 8-9, 2000, San Diego, California, USA, Proceedings, pp. 79-81, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
capacitance measurement, interconnect characterization, noise measurement, process variation, interconnect estimation |
45 | Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny |
Timing optimization in logic with interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 19-26, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
interconnect, logic circuits, timing optimization, repeaters, logical effort |
45 | Andrew B. Kahng, Rasit Onur Topaloglu |
Generation of design guarantees for interconnect matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 29-34, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
design guarantee generation, interconnect matching |
45 | Viet H. Nguyen, Phillip Christie |
The impact of interstratal interconnect density on the performance of three-dimensional integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 73-78, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
interstratal interconnect, 3D-IC, system-level |
45 | Luca Daniel, Chin Siong Ong, Sok Chay Low, Kwok Hong Lee, Jacob White 0001 |
Geometrically parameterized interconnect performance models for interconnect synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 202-207, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
parametrized model order reduction, interconnect synthesis |
45 | Ingrid Verbauwhede, M.-C. Frank Chang |
Reconfigurable interconnect for next generation systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 71-74, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
architectures, reconfiguration, interconnect, design methods, power efficiency |
45 | Qinwei Xu, Pinaki Mazumder |
Novel interconnect modeling by using high-order compact finite difference methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002, pp. 148-152, 2002, ACM, 1-58113-462-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
differential quadrature method, discrete interconnect modeling, passivity, interconnect modeling, transient simulation |
45 | Jason Cong, Lei He 0001, Cheng-Kok Koh, David Zhigang Pan |
Global interconnect sizing and spacing with consideration of coupling capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 628-633, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
GISS solutions, asymmetric wire sizing, delay reduction, fringing capacitances, global interconnect sizing and spacing, global wire sizing, interconnect delay minimization, multiple nets, optimal wire sizing, spacing solution, symmetric effective fringing properties, VLSI, coupling capacitance |
44 | Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown |
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 3-8, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
44 | N. S. Nagaraj |
Dealing with interconnect process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 39, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
44 | Joshua Hursey, Timothy Mattox, Andrew Lumsdaine |
Interconnect agnostic checkpoint/restart in open MPI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPDC ![In: Proceedings of the 18th ACM International Symposium on High Performance Distributed Computing, HPDC 2009, Garching, Germany, June 11-13, 2009, pp. 49-58, 2009, ACM, 978-1-60558-587-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
checkpoint coordination protocol, fault tolerance, MPI, shared memory, rollback-recovery, infiniband, myrinet, high speed interconnect, checkpoint/restart |
44 | Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Diederik Verkest |
Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 201-207, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Interconnect-Aware Design, Low Power, Processor Architecture, Energy-Aware Design |
44 | Frank Huebbers, Ali Dasdan, Yehea I. Ismail |
Computation of accurate interconnect process parameter values for performance corners under process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 797-800, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
sorners, delay, interconnect, STA, variations |
44 | Akshay Sharma, Katherine Compton, Carl Ebeling, Scott Hauck |
Exploration of pipelined FPGA interconnect structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 13-22, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
PipeRoute, pipelined FPGA, pipelined interconnect, registered routing, architecture explorations |
44 | Shalini Ghosh, F. Joel Ferguson |
Estimating detection probability of interconnect opens using stuck-at tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 254-259, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
break fault, interconnect open, stuck-at test |
44 | Kavel M. BĂ¼yĂ¼ksahin, Farid N. Najm |
High-level power estimation with interconnect effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 197-202, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
high-level power estimation, interconnect capacitance estimation, register transfer level (RTL) power estimation |
43 | Chiu-Wing Sham, Evangeline F. Y. Young |
Area reduction by deadspace utilization on interconnect optimized floorplan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(1), pp. 3:1-3:11, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
area reduction, Floorplanning |
43 | Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen, Narayanan Vijaykrishnan, Yehia Massoud |
Assessing carbon nanotube bundle interconnect for future FPGA architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 307-312, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David T. Blaauw |
Statistical interconnect metrics for physical-design optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7), pp. 1273-1288, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Vishal Suthar, Shantanu Dutt |
Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 36-43, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell |
Benchmarks for Interconnect Parasitic Resistance and Capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 163-168, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
43 | John Marty Emmert, Stanley Baumgart, Pankaj Kataria, Andrew M. Taylor, Charles E. Stroud, Miron Abramovici |
On-Line Fault Tolerance for FPGA Interconnect with Roving STARs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 445-454, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
43 | Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas |
Impact of interconnect variations on the clock skew of a gigahertz microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 168-171, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
43 | Frank W. Angelotti |
Generating interconnect models from prototype hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 396-403, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
43 | Jessica Qian, Satyamurthy Pullela, Lawrence T. Pillage |
Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(12), pp. 1526-1535, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
43 | Tai A. Ly, W. Lloyd Elwood, Emil F. Girczyc |
A Generalized Interconnect Model for Data Path Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 168-173, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
43 | Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley |
Efficient tiling patterns for reconfigurable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 257, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA hexagonal octagonal, tiling interconnect |
39 | Robert Fischbach, Jens Lienig, Tilo Meister |
From 3D circuit technologies and data structures to interconnect prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 77-84, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
3d floorplanning, three-dimensional circuits, data structures, 3d integration, interconnect prediction |
39 | Peng Sun, Rong Luo |
Closed-form solution for timing analysis of process variations on SWCNT interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 19-26, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
interconnect, process variation, timing analysis, carbon nanotube, closed-form |
39 | Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy 0001 |
Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 387-390, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
signal slope, interconnect, gate delay, subthreshold operation |
39 | James D. Z. Ma, Lei He 0001 |
Simultaneous signal and power routing under K model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 175-182, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
net ordering, on-chip inductance, shield insertion, interconnect estimation, interconnect design |
39 | Jianhua Shao, Richard M. M. Chen |
MCM Interconnect Design Using Two-Pole Approximation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 544-548, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Two-Pole Approximation, Interconnect Optimization, Interconnect Design |
39 | Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi |
PRIMA: passive reduced-order interconnect macromodeling algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 58-65, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
MPVL, PRIMA, RLC interconnect circuits, block Arnoldi technique, driver-load models, guaranteed passivity, macromodel passivity, macromodel stability, passive reduced-order interconnect macromodeling algorithm, path tracing algorithm, reduced order N-port models, simulation, CAD, integrated circuit layout, frequency domain, circuit stability |
39 | Steven D. Corey, Andrew T. Yang |
Automatic netlist extraction for measurement-based characterization of off-chip interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 24-29, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
MCM substrate-level interconnect circuitry, SPICE netlist, automatic netlist extraction, linear circuits, measured time domain refectometry data, measurement-based characterization, microstrip circuits, multiport system, off-chip interconnect, reflection transmission, time-domain scattering parameters, user-specified cutoff frequency, delay, crosstalk, circuit simulator, multichip modules, nonlinear circuits |
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