Search results for "retiming"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
186	Tracy C. Denk, Keshab K. Parhi	Two-dimensional retiming [VLSI design].	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
152	Deshanand P. Singh, Stephen Dean Brown	Integrated retiming and placement for field programmable gate arrays.	FPGA	2002	DBLP DOI BibTeX RDF
152	Jason Cong, Chang Wu	Optimal FPGA mapping and retiming with efficient initial state computation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
130	Naresh Maheshwari, Sachin S. Sapatnekar	Efficient retiming of large circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
108	Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha	Optimizing Nested Loops with Iterational and Instructional Retiming.	EUC	2005	DBLP DOI BibTeX RDF
102	Jia Wang 0003, Hai Zhou 0001	An efficient incremental algorithm for min-area retiming.	DAC	2008	DBLP DOI BibTeX RDF	retiming
102	Mongkol Ekpanyapong, Sung Kyu Lim	Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization.	ISPD	2006	DBLP DOI BibTeX RDF	supply and threshold voltage scaling, low power design, retiming
102	Jason Cong, Xin Yuan 0005	Multilevel global placement with retiming.	DAC	2003	DBLP DOI BibTeX RDF	physical hierarchy, placement, retiming, deep sub-micron
102	Naresh Maheshwari, Sachin S. Sapatnekar	A Practical Algorithm for Retiming Level-Clocked Circuits.	ICCD	1996	DBLP DOI BibTeX RDF	level-clocked, retiming, clock skew, timing optimization
102	Kumar N. Lalgudi, Marios C. Papaefthymiou	Efficient retiming under a general delay model.	ARVLSI	1995	DBLP DOI BibTeX RDF	retiming algorithm, general delay model, edge-triggered circuits, load-dependent gate delays, register delays, integer linear programming constraints, integer phonotonic programming formulation, linear programming, delays, timing, integer programming, logic design, logic design, logic circuits, clock skew, propagation delays, interconnect delays
102	Srimat T. Chakradhar	Optimum retiming of large sequential circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	optimum retiming, large sequential circuits, unit delay model, optimum clock period, path graph, VLSI, linear programming, delays, timing, integer programming, sequential circuits, logic CAD, integer linear program, flip-flops, circuit CAD, fast algorithm, integrated logic circuits, circuit optimisation, VLSI circuits, linear program relaxation
97	Jason Cong, Chang Wu	Optimal FPGA Mapping and Retiming with Efficient Initial State Computation.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
97	Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly	Behavior and testability preservation under the retiming transformation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
97	Kumar N. Lalgudi, Marios C. Papaefthymiou	Retiming edge-triggered circuits under general delay models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
91	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Test sequence compaction by reduced scan shift and retiming.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	reduced scan shift, full scan designed circuits, computational complexity, logic testing, timing, transformation, design for testability, sequential circuits, sequential circuit, logic CAD, flip-flops, flip-flops, retiming, computing time, test length, test sequence generation, test sequence compaction
85	Jie-Hong Roland Jiang, Wei-Lun Hung	Inductive equivalence checking under retiming and resynthesis.	ICCAD	2007	DBLP DOI BibTeX RDF
85	Jason Cong, Sung Kyu Lim	Retiming-based timing analysis with an application to mincut-based global placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
85	Andreas Kuehlmann, Jason Baumgartner	Transformation-Based Verification Using Generalized Retiming.	CAV	2001	DBLP DOI BibTeX RDF
85	Narendra V. Shenoy, Richard L. Rudell	Efficient implementation of retiming.	ICCAD	1994	DBLP DOI BibTeX RDF
80	Yu Hu 0002, Yan Lin 0001, Lei He 0001, Tim Tuan	Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction.	DAC	2006	DBLP DOI BibTeX RDF	FPGA, low power, retiming
80	Timothy W. O'Neil, Edwin Hsing-Mean Sha	Combining Extended Retiming and Unfolding for Rate-Optimal Graph Transformation.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	scheduling, graph transformation, retiming, unfolding, data-flow graphs, timing optimization
80	Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi	A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	Minimum area retiming, application of mincost network flow, longpath circuit constraints, minimum delay padding, shortpath circuit constraints
80	Naresh Maheshwari, Sachin S. Sapatnekar	Minimum area retiming with equivalent initial states.	ICCAD	1997	DBLP DOI BibTeX RDF	VLSI, Sequential Circuits, Retiming, Design Automation, Timing Optimization, Area Optimization
80	Samir Lejmi, Bozena Kaminska, Bechir Ayari	Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	segmentation cells, segmentation edges, logic testing, partitioning, timing, sequential circuits, sequential circuits, iterative methods, circuit analysis computing, retiming, iterative algorithm, circuit optimisation, logic partitioning, logic optimization, resynthesis, synchronous circuits, pseudo-exhaustive testing
78	Tracy C. Denk, Keshab K. Parhi	Lower bounds on memory requirements for statically scheduled DSP programs.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
74	Hai Zhou 0001	Retiming and resynthesis with sweep are complete for sequential transformation.	FMCAD	2009	DBLP DOI BibTeX RDF
74	Kenneth Eguro, Scott Hauck	Simultaneous Retiming and Placement for Pipelined Netlists.	FCCM	2008	DBLP DOI BibTeX RDF
74	Dennis K. Y. Tong, Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu	Wire Retiming Problem With Net Topology Optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
74	Mongkol Ekpanyapong, Xin Zhao 0001, Sung Kyu Lim	An Efficient Computation of Statistically Critical Sequential Paths Under Retiming.	ASP-DAC	2007	DBLP DOI BibTeX RDF
74	Jie-Hong Roland Jiang, Robert K. Brayton	Retiming and Resynthesis: A Complexity Perspective.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
74	Jie-Hong Roland Jiang	On Some Transformation Invariants Under Retiming and Resynthesis.	TACAS	2005	DBLP DOI BibTeX RDF
74	Maher N. Mneimneh, Karem A. Sakallah, John Moondanos	Preserving synchronizing sequences of sequential circuits after retiming.	ASP-DAC	2004	DBLP DOI BibTeX RDF
74	Ingmar Neumann, Wolfgang Kunz	Layout driven retiming using the coupled edge timing model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
74	Peter Suaris, Dongsheng Wang 0012, Pei-Ning Guo, Nan-Chi Chou	A physical retiming algorithm for field programmable gate arrays.	FPGA	2003	DBLP DOI BibTeX RDF
74	Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman	Retiming and clock scheduling for digital circuit optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
74	Klaus Eckl, Christian Legl	Retiming Sequential Circuits with Multiple Register Classes.	DATE	1999	DBLP DOI BibTeX RDF
74	Naresh Maheshwari, Sachin S. Sapatnekar	An Improved Algorithm for Minimum-Area Retiming.	DAC	1997	DBLP DOI BibTeX RDF
74	Nicholas Weaver, Yury Markovsky, Yatish Patel, John Wawrzynek	Post-placement C-slow retiming for the xilinx virtex FPGA.	FPGA	2003	DBLP DOI BibTeX RDF	C-slow retiming, FPGA CAD, FPGA optimization, retiming
70	Sachin S. Sapatnekar, Rahul B. Deokar	Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
68	In-Ho Moon	Compositional verification of retiming and sequential optimizations.	DAC	2008	DBLP DOI BibTeX RDF	conditional equivalence, retime offset, sequential equivalence, retiming, compositional verification
68	Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha	Iterational retiming: maximize iteration-level parallelism for nested loops.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	optimization, partition, retiming, nested loops
68	Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David T. Blaauw, Trevor N. Mudge	Reducing pipeline energy demands with local DVS and dynamic retiming.	ISLPED	2004	DBLP DOI BibTeX RDF	dynamic retiming with global DVS, local DVS, razor
68	Jia Wang 0003, Hai Zhou 0001	Minimal period retiming under process variations.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	process variations, retiming, statistical timing analysis
68	Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria	Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	supply voltage scaling, performance, power consumption, CMOS, retiming, digital design
68	Ingmar Neumann, Kolja Sulimma, Wolfgang Kunz	Accelerating Retiming Under the Coupled-Edge Timing Model.	ISVLSI	2002	DBLP DOI BibTeX RDF	retiming, timing optimization
68	Surendra Bommu, Niall O'Neill, Maciej J. Ciesielski	Retiming-based factorization for sequential logic optimization.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	finite stat machines, retiming, sequential synthesis
68	Zulan Huang, Yizheng Ye, Zhigang Mao	A New Algorithm for Retiming-Based Partial Scan.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	retiming, Partial scan, minimum feedback vertex set
68	Naresh Maheshwari, Sachin S. Sapatnekar	Efficient Minarea Retiming of Large Level-Clocked Circuits.	DATE	1998	DBLP DOI BibTeX RDF	Level-clocked, Optimization, Synthesis, Retiming, Area
68	Liang-Fang Chao, Edwin Hsing-Mean Sha	Scheduling Data-Flow Graphs via Retiming and Unfolding.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	scheduling, parallel processing, retiming, unfolding, Data-flow graphs, loop parallelization
68	Nelson L. Passos, Edwin Hsing-Mean Sha	Achieving Full Parallelism Using Multidimensional Retiming.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	multidimensional data-flow graphs, instruction level parallelism, VLIW, Retiming, loop transformation, superscalar, nested loops
68	Debesh Kumar Das, Bhargab B. Bhattacharya	Does retiming affect redundancy in sequential circuits?	VLSI Design	1996	DBLP DOI BibTeX RDF	combinational redundancy, sequential redundancy, fault diagnosis, logic testing, timing, redundancy, test generation, design for testability, sequential circuits, sequential circuit, fault, retiming, logic optimization, operation speed
63	Nikolaos D. Liveris, Hai Zhou 0001, Prithviraj Banerjee	Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis.	ASP-DAC	2009	DBLP DOI BibTeX RDF
63	Chuan Lin 0002, Hai Zhou 0001	Wire retiming as fixpoint computation.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
63	Noureddine Chabini, Wayne H. Wolf	Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
63	Chuan Lin 0002, Hai Zhou 0001	Wire Retiming for System-on-Chip by Fixpoint Computation.	DATE	2004	DBLP DOI BibTeX RDF
63	Ulrich Seidl, Klaus Eckl, Frank M. Johannes	Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information.	DATE	2003	DBLP DOI BibTeX RDF
63	Peichen Pan, Guohua Chen	Optimal Retiming for Initial State Computation.	VLSI Design	1999	DBLP DOI BibTeX RDF
63	Pierre-Yves Calland, Anne Mignotte, Olivier Peyran, Yves Robert, Frédéric Vivien	Retiming DAGs [direct acyclic graph].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
63	Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.	Incorporating interconnect, register, and clock distribution delays into the retiming process.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
63	Guy Even, Ilan Y. Spillinger, Leon Stok	Retiming revisited and reversed.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
63	Babette van Antwerpen-de Fluiter, Emile H. L. Aarts, Jan H. M. Korst, Wim F. J. Verhaegh, Albert van der Werf	The complexity of generalized retiming problems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
63	Brian Lockyear, Carl Ebeling	Optimal retiming of level-clocked circuits using symmetric clock schedules.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
63	Hans-Georg Martin	Retiming for Circuits with Enable Registers.	EUROMICRO	1996	DBLP DOI BibTeX RDF	enable registers, circuit retiming, combinational paths, D-Flipflops, retiming algorithm, sequential elements, high level synthesis, high level synthesis, digital circuits
61	Dennis K. Y. Tong, Evangeline F. Y. Young	Performance-driven register insertion in placement.	ISPD	2004	DBLP DOI BibTeX RDF	post-retiming, register insertion, placement
57	Smita Krishnaswamy, Igor L. Markov, John P. Hayes	Improving testability and soft-error resilience through retiming.	DAC	2009	DBLP DOI BibTeX RDF	testability, soft errors, retiming
57	Yu Hu 0002, Yan Lin 0001, Lei He 0001, Tim Tuan	Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	FPGA, Low power, retiming
57	Nikolaos D. Liveris, Chuan Lin 0002, J. Wang, Hai Zhou 0001, Prithviraj Banerjee	Retiming for Synchronous Data Flow Graphs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	cycle length, synchronous data flow graphs, retiming
57	Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton	Fast Minimum-Register Retiming via Binary Maximum-Flow.	FMCAD	2007	DBLP DOI BibTeX RDF	Sequential Verification, Retiming, Maximum Flow, State Minimization
57	Noureddine Chabini, Wayne H. Wolf	An approach for integrating basic retiming and software pipelining.	EMSOFT	2004	DBLP DOI BibTeX RDF	embedded systems, system-on-chip, timings, instruction-level parallelism, software pipelining, VLIW, retiming, superscalar processor, peak power, code size
57	Pierre-Yves Calland, Alain Darte, Yves Robert	Circuit Retiming Applied to Decomposed Software Pipelining.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	circuit retiming, Software pipelining, list scheduling, modulo scheduling, cyclic scheduling
57	Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita	Synthesis of Sequential Circuits by Redundancy Removal and Retiming.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	synthesis of sequential circuits, sequentially redundant fault, retiming, redundant fault, redundancy removal
57	Vigyan Singhal, Sharad Malik, Robert K. Brayton	The case for retiming with explicit reset circuitry.	ICCAD	1996	DBLP DOI BibTeX RDF	reset state, synchronous reset, asynchronous reset, Retiming, initial state
57	Arun Balakrishnan, Srimat T. Chakradhar	Retiming with logic duplication transformation: theory and an application to partial scan.	VLSI Design	1996	DBLP DOI BibTeX RDF	logic duplication transformation, partial scan application, RLD configurations, RLD transformation, testability metrics, scan flip-flops, sequential circuit design, linear programming, timing, integer programming, logic design, sequential circuits, logic CAD, polynomial time algorithm, integer linear program, flip-flops, retiming, integrated circuit design, circuit CAD, integrated logic circuits, objective function
57	Sven Simon 0001, Ralf Bucher, Josef A. Nossek	Retiming of synchronous circuits with variable topology.	VLSI Design	1995	DBLP DOI BibTeX RDF	variable topology, combinational elements selection, circuit graph, optimization, graph theory, linear programming, delays, timing, interconnections, logic design, network topology, logic CAD, retiming, circuit CAD, circuit optimisation, synchronous circuits
56	Dmitry Bufistov, Jordi Cortadella, Michael Kishinevsky, Sachin S. Sapatnekar	A general model for performance optimization of sequential systems.	ICCAD	2007	DBLP DOI BibTeX RDF
56	Chao-Yang Yeh, Malgorzata Marek-Sadowska	Sequential delay budgeting with interconnect prediction.	SLIP	2003	DBLP DOI BibTeX RDF	delay budgeting, sequential circuits, interconnect prediction
56	Naresh Maheshwari, Sachin S. Sapatnekar	Optimizing large multiphase level-clocked circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
52	Jia Wang 0003, Hai Zhou 0001	Risk aversion min-period retiming under process variations.	ASP-DAC	2009	DBLP DOI BibTeX RDF
52	Cristian Soviani, Olivier Tardieu, Stephen A. Edwards	Optimizing Sequential Cycles Through Shannon Decomposition and Retiming.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
52	Chuan Lin 0002, Hai Zhou 0001	Optimal wire retiming without binary search.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
52	Cristian Soviani, Olivier Tardieu, Stephen A. Edwards	Optimizing sequential cycles through Shannon decomposition and retiming.	DATE	2006	DBLP DOI BibTeX RDF
52	James McCann, Nancy S. Pollard, Siddhartha S. Srinivasa	Physics-based motion retiming.	Symposium on Computer Animation	2006	DBLP DOI BibTeX RDF
52	Peter Suaris, Dongsheng Wang 0012, Nan-Chi Chou	A practical cut-based physical retiming algorithm for field programmable gate arrays.	ASP-DAC	2005	DBLP DOI BibTeX RDF
52	Miklós Bartha	Strong Retiming Equivalence of Synchronous Schemes.	CIAA	2005	DBLP DOI BibTeX RDF
52	Hai Zhou 0001, Chuan Lin 0002	Retiming for wire pipelining in system-on-chip.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
52	Chuan Lin 0002, Hai Zhou 0001	Optimal wire retiming without binary search.	ICCAD	2004	DBLP DOI BibTeX RDF
52	Ruibing Lu, Cheng-Kok Koh	Interconnect Planning with Local Area Constrained Retiming.	DATE	2003	DBLP DOI BibTeX RDF
52	Ingmar Neumann, Wolfgang Kunz	Tight coupling of timing-driven placement and retiming.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
52	Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.	The use of carry-save representation in joint module selection and retiming.	DAC	2000	DBLP DOI BibTeX RDF
52	Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi	Marsh: min-area retiming with setup and hold constraints.	ICCAD	1999	DBLP DOI BibTeX RDF
52	Felipe Fernández, Ángel Sánchez	Application of Multidimensional Retiming and Matroid Theory to DSP Algorithm Parallelization.	EUROMICRO	1999	DBLP DOI BibTeX RDF
52	Tolga Soyata, Eby G. Friedman	Retiming with non-zero clock skew, variable register, and interconnect delay.	ICCAD	1994	DBLP DOI BibTeX RDF
50	Meilin Liu, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha	General loop fusion technique for nested loops considering timing and code size.	CASES	2004	DBLP DOI BibTeX RDF	embedded DSP, scheduling, retiming, code size, loop fusion
50	Sissades Tongsima, Edwin Hsing-Mean Sha, Chantana Chantrapornchai, David R. Surma, Nelson L. Passos	Probabilistic Loop Scheduling for Applications with Uncertain Execution Time.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	rotation scheduling, Scheduling, retiming, probabilistic approach, loop pipelining
50	Peichen Pan, C. L. Liu 0001	Optimal clock period FPGA technology mapping for sequential circuits.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, retiming, technology mapping, look-up tables, logic replication, clock period, sequential synthesis
46	Hai Zhou 0001	A new efficient retiming algorithm derived by formal manipulation.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Clockperiod minimization, algorithm derivation, retiming
46	Chuan Lin 0002, Hai Zhou 0001	An efficient retiming algorithm under setup and hold constraints.	DAC	2006	DBLP DOI BibTeX RDF	retiming
46	Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown	Incremental retiming for FPGA physical synthesis.	DAC	2005	DBLP DOI BibTeX RDF	FPGA, retiming, physical synthesis
46	Yu-Lung Hsu, Sying-Jyan Wang	Retiming-based logic synthesis for low-power.	ISLPED	2002	DBLP DOI BibTeX RDF	switching actvity, low-power, logic design, retiming
46	Farhana Sheikh, Andreas Kuehlmann, Kurt Keutzer	Minimum-power retiming for dual-supply CMOS circuits.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	dual-supply, retiming theory, low-power, synthesis, low-power design