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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1260 occurrences of 713 keywords
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Results
Found 3329 publication records. Showing 3329 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
57 | Eduardo Conrad Jr., Fernando da Rocha Paixão Cortes, Sergio Bampi, Alessandro Girardi |
Early voltage and saturation voltage improvement in deep sub-micron technologies using associations of transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 105-110, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
TAT, TST, association of transistors, measurements, device modeling |
57 | Alessandro Girardi, Fernando da Rocha Paixão Cortes, Eduardo Conrad Jr., Sergio Bampi |
T-shaped association of transistors: modeling of multiple channel lengths and regular associations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 21-26, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
associations of transistors, modeling, analog design, MOSFET |
51 | Jin-Kyu Park, Keun-Ho Lee, Chang-Sub Lee, Gi-Young Yang, Young-Kwan Park, Jeong-Taek Kong |
Characterizing the Current Degradation of Abnormally Structured MOS Transistors Using a 3D Poisson Solver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 322-325, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
CURRENT DEGRADATION, ABNORMALLY STRUCTURED MOS, MODELING |
51 | Shoujue Wang, Xunwei Wu, Hongjuan Feng |
The High-Speed Ternary Logic Gates Based on the Multiple beta Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 178-181, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high speed ternary logic gates, multiple /spl beta/ transistors, multiple emitter transistor, current gain, linear AND/OR gates, multi valued literal circuits, high speed multi valued logic circuits, multivalued logic circuits, logic gates, ternary logic, transistors |
45 | Sanjay Rekhi, J. Donald Trotter |
HAL: heuristic algorithms for layout synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 185-199, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
layout synthesis, graph theory based algorithms, leaf cells, common poly gates, 1-1/2-d layout style, common circuit nodes, transistor sets, symbolic layouts, static dual type, static CMOS circuitry, pullup network, pulldown network, dynamic logic styles, graph theory, network topology, logic CAD, heuristic algorithms, circuit layout CAD, CMOS logic circuits, CMOS circuits, GENIE, run time efficient, layout area |
45 | Sherif A. Tawfik, Volkan Kursun |
Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 855-860, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
45 | Changbo Long, Jinjun Xiong, Lei He 0001 |
On optimal physical synthesis of sleep transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 156-161, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
physical design, power-gating, sleep transistors |
44 | Takao Waho |
Resonant Tunneling Transistor and Its Application to Multiple-Valued Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 130-139, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
resonant tunnelling transistors, resonant tunneling transistors, multiple-valued logic circuits, multiple stable states, coupled-quantum-well, monostable-multistable logic circuits, multivalued logic circuits, resonant tunneling diodes, circuit stability |
44 | G. Hari Rama Krishna, Amit K. Aditya, Nirmal B. Chakrabarti, Swapna Banerjee |
Analysis of temperature dependence of Si-Ge HBT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 268-271, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
semiconductor materials, heterojunction bipolar transistors, Ge-Si alloys, heterojunction bipolar transistors, Ge mole-fraction, two dimensional device simulator, BISOF, current gain, graded HBT, 200 to 300 K, simulation, finite element method, finite element analysis, FEM, temperature dependence, SiGe, thermal analysis, semiconductor device models |
39 | Vivek De |
Leakage-tolerant design techniques for high performance processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 28-28, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
39 | Kuen-Yu Tsai, Meng-Fu You, Yi-Chang Lu, Philip C. W. Ng |
A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 286-291, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta |
Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NanoNet ![In: Nano-Net - 4th International ICST Conference, Nano-Net 2009, Lucerne, Switzerland, October 18-20, 2009. Proceedings, pp. 200-209, 2009, Springer, 978-3-642-04849-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low-energy circuits, single electron transistors, binary decision diagram logic circuits |
38 | Rafail Lashevsky, K. Takaara, M. Souma |
The efficiency of neuron-MOS transistors in threshold logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Soft Comput. ![In: Soft Comput. 3(1), pp. 20-29, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Neuron MOS-transistors, threshold gate with alterable parameters, threshold logic |
38 | Yen-Kuei Chu, Hsiu-Sheng Lin, Po-Chou Lai |
Research of a Fast High Voltage Semiconductor Switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2010, Taipei, Taiwan, 6-9 September 2010, pp. 52-56, 2010, IEEE Computer Society, 978-1-4244-8095-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Pulse Forming Networks (PFNs), Pulse Repetition Frequency (PRF), Metal Oxide Semiconductors Field Effect Transistors (MOSFETs), Insulated Gate Bipolar Transistors (IGBTs) |
38 | Lutz J. Micheel, Hans L. Hartnagel |
Interband RTDs with Nanoelectronic HBT-LED Structures for Multiple-Valued Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 80-85, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
heterojunction bipolar transistors, resonant tunnelling devices, light emitting devices, interband RTDs, resonant tunnelling devices, nanoelectronic HBT-LED structures, multiple-valued computation, nanoelectronic arrays, complex signal processing methods, HBT-LED-RTD circuitry, heterojunction bipolar transistors, light emitting devices, internal optical methods, signal summation, precision photon streams, positive-digit radix-2 MVL, A/D conversion capability, optical isolation, buried optical interconnects, microcavity lasers, signal processing, optical interconnections, optical interconnects, multiple-valued logic, multivalued logic circuits, thresholding functions, analogue-digital conversion |
38 | Hong Hao, Edward J. McCluskey |
Analysis of Gate Oxide Shorts in CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(12), pp. 1510-1516, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
resistance dependence, voltage dependence, pattern dependence, logic gate operation, p-channel transistors, n-channel transistors, CMOS integrated circuits, integrated logic circuits, CMOS circuits, logic gates, defect models, temperature dependence, gate oxide shorts, semiconductor device models |
32 | Rajesh Garg, Sunil P. Khatri |
A novel, highly SEU tolerant digital circuit design approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 14-20, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Robert J. Bonneau, George O. Ramseyer, Tom Renz, Claire Thiem |
A Mathematical Architecture for Molecular Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AIPR ![In: 36th Applied Imagery Pattern Recognition Workshop, AIPR 2007, Washington, DC, USA, October 10-12, 2007, Proceedings, pp. 80-86, 2007, IEEE Computer Society, 978-0-7695-3066-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
molecular computing |
32 | Claas Cornelius, Frank Sill, Hagen Sämrow, Jakob Salzmann, Dirk Timmermann, Diógenes Cecilio da Silva Jr. |
Encountering gate oxide breakdown with shadow transistors to increase reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 111-116, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
gate oxide breakdown, modeling, redundancy, logic design, nanotechnology, organic computing, transistor |
32 | Z. Huang, Yvon Savaria, Mohamad Sawan, R. Meinga |
High-voltage operational amplifier based on dual floating-gate transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Mustapha Chérif-Eddine Yagoub, Jing Xian Li, Farah A. Mohammadi |
Méthode Optimale de Modélisation de Transistors Haute Fréquence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 368-371, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | David W. Graham, Ethan Farquhar, Brian P. Degnan, Christal Gordon, Paul E. Hasler |
Indirect programming of floating-gate transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2172-2175, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Paula López 0001, Matthias Oberst, Harald Neubauer, Johann Hauer, Diego Cabello |
Performance analysis of high-speed MOS transistors with different layout styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3688-3691, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Alessandro Girardi, Sergio Bampi |
LIT - An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 11106-11107, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Alessandro Girardi, Fernando da Rocha Paixão Cortes, Eric E. Fabris, Sergio Bampi |
Analog IC Modules Design Using Trapezoidal Association of MOS Transistors in 0.35µm Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, pp. 311-316, 2003, IEEE Computer Society, 0-7695-2009-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | João P. B. Botelho, Leonardo Bruno de Sá, Pedro F. Vieira, Antonio Carneiro de Mesquita Filho |
An Experiment on Nonlinear Synthesis Using Evolutionary Techniques Based only on CMOS Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 5th NASA / DoD Workshop on Evolvable Hardware (EH 2003), 9-11 July 2002, Chicago, IL, USA, pp. 58, 2003, IEEE Computer Society, 0-7695-1977-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao |
Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 99-104, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Mike Sheng, Jonathan Rose |
Mixing buffers and pass transistors in FPGA routing architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 75-84, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Ming-Jiang Zhou, Herbert De Smet, Anita De Bruycker, André Van Calster |
A 2-D boundary element method approach to the simulation of DMOS transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(6), pp. 810-816, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
32 | Satoshi Sugahara, Masaaki Tanaka |
Spin MOSFETs as a basis for spintronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Storage ![In: ACM Trans. Storage 2(2), pp. 197-219, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
spin MOSFETs, spin transistors, MOSFETs, Spintronics |
32 | Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand |
Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(4), pp. 377-386, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
minimal-length transistors, fault modeling, gate oxide short |
32 | Jiann-Shiun Yuan |
Overview of SiGe Technology Modeling and Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 67-72, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
SiGe heterojunction bipolar transistors, wireless communications |
32 | Michael S. Shur, Tor A. Fjeldly, Trond Ytterdal |
Transistor Modeling for the VDSM Era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 37-44, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
field effect transistors, parameter extraction, SPICE, device modeling |
32 | Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang |
On Designing of 4-Valued Memory with Double-Gate TFT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 187-193, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
thin film transistors, 4-valued memory, double-gate TFT, 4 valued memory cell, double gate thin film transistor, double gate TFT, HSPICE simulation, resistor load, CMOS load basic block circuit, memory cell circuits, SRAM cell circuit, memory architecture, integrated circuit design, multivalued logic, SPICE, circuit design, multivalued logic circuits, SRAM chips, CMOS memory circuits, equivalent circuits, equivalent circuit |
32 | Vikas Kaushal, Quentin Diduck, Martin Margala |
Study of leakage current mechanisms in ballistic deflection transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 165-168, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
ballistic transport, current leakage mechanism, deflection transistors, silvaco simulation, geometry, monte carlo simulation |
32 | Arijit Raychowdhury, Xuanyao Fong, Qikai Chen, Kaushik Roy 0001 |
Analysis of super cut-off transistors for ultralow power digital logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 2-7, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
carbon nanotube FETs, tunneling transistors |
26 | John Keane 0001, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim |
Stack Sizing for Optimal Current Drivability in Subthreshold Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(5), pp. 598-602, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija |
Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 268-276, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Clocked storage elements, VLSI, power consumption, flip-flops, voltage scaling, clock gating, power gating, energy optimization, MTCMOS, circuit optimization, circuit tuning, circuit analysis |
26 | Sherif A. Tawfik, Volkan Kursun |
Low power and robust 7T dual-Vt SRAM circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1452-1455, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Zhiyu Liu, Volkan Kursun |
PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(12), pp. 1311-1319, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Jaume Abella 0001, Xavier Vera, Antonio González 0001 |
Penelope: The NBTI-Aware Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA, pp. 85-96, 2007, IEEE Computer Society, 0-7695-3047-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Bernabé Linares-Barranco, Teresa Serrano-Gotarredona |
A Physical Interpretation of the Distance Term in Pelgrom's Mismatch Model results in very Efficient CAD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1561-1564, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Chanseok Hwang, Peng Rong, Massoud Pedram |
Sleep transistor distribution in row-based MTCMOS designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 235-240, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
leakage minimization, placement, MTCMOS |
26 | John Keane 0001, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim |
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 425-428, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
subthreshold logic, ultra-low power design, logical effort |
26 | Andrea Lodi 0002, Luca Ciccarelli, Roberto Giansante |
Combining low-leakage techniques for FPGA routing design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 208-214, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low leakage, FPGA, power |
26 | Shouli Yan, Jingyu Hu, Tongyu Song, Edgar Sánchez-Sinencio |
A constant-gm rail-to-rail op amp input stage using dynamic current scaling technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2567-2570, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Shrirang K. Karandikar, Sachin S. Sapatnekar |
Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(6), pp. 1094-1105, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Kuo-Hsing Cheng, Yung-Hsiang Lin |
A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 425-428, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Robert W. Newcomb, Chai-Hung Yang, Angela Hodge-Miller |
Quantum dot neural network neurons. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICARCV ![In: Seventh International Conference on Control, Automation, Robotics and Vision, ICARCV 2002, Singapore, 2-5 December 2002, Proceedings, pp. 29-33, 2002, IEEE, 981-04-8364-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Andreas G. Andreou |
A general subthreshold MOS translinear theorem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 302-305, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Tak-Kwong Ng, S. Lennart Johnsson |
Generation of layouts from MOS circuit schematics: a graph theoretic approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 39-45, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
26 | Shuo Wang, Jianwei Dai, El-Sayed A. M. Hasaneen, Lei Wang 0003, Faquir C. Jain |
Utilizing quantum dot transistors with programmable threshold voltages for low-power mobile computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 5(3), pp. 15:1-15:19, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
threshold voltage and quantum dot transistor, Low power |
26 | Ratul Kumar Baruah, Santanu Mahapatra |
Concept of "Crossover Point" and its Application on Threshold Voltage Definition for Undoped-Body Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 241-246, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Aswin Sreedhar, Sandip Kundu |
Modeling and analysis of non-rectangular transistors caused by lithographic distortions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 444-449, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Shuo Wang, Jianwei Dai, El-Sayed A. M. Hasaneen, Lei Wang 0003, Faquir C. Jain |
Programmable threshold voltage using quantum dot transistors for low-power mobile computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3350-3353, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Viktor Gruev, Zheng Yang 0004, Jan Van der Spiegel |
Low power linear current mode imager with 1.5 transistors per pixel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2142-2145, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Yukiya Miura, Jiro Kato |
Diagnosis of Analog Circuits by Using Multiple Transistors and Data Sampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 491-499, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram |
Sizing and placement of charge recycling transistors in MTCMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 791-796, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Zbysek Gajda, Lukás Sekanina |
Reducing the number of transistors in digital circuits using gate-level evolutionary design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2007, Proceedings, London, England, UK, July 7-11, 2007, pp. 245-252, 2007, ACM, 978-1-59593-697-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
digital circuits, evolvable hardware, evolutionary design |
26 | Yiming Li 0005, Chih-Hong Hwang, Shao-Ming Yu |
Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science (4) ![In: Computational Science - ICCS 2007, 7th International Conference, Beijing, China, May 27 - 30, 2007, Proceedings, Part IV, pp. 227-234, 2007, Springer, 978-3-540-72589-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
computational statistics, SRAM, modeling and simulation, FinFET |
26 | Zheng Yang 0004, Viktor Gruev, Jan Van der Spiegel |
Low Fixed Pattern Noise Current-mode Imager Using Velocity Saturated Readout Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2842-2845, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | David W. Graham, Paul E. Hasler |
Run-Time Programming of Analog Circuits Using Floating-Gate Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3816-3819, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Mahdi Pourfath, Hans Kosina |
Fast Convergent Schrödinger-Poisson Solver for the Static and Dynamic Analysis of Carbon Nanotube Field Effect Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LSSC ![In: Large-Scale Scientific Computing, 5th International Conference, LSSC 2005, Sozopol, Bulgaria, June 6-10, 2005, Revised Papers, pp. 578-585, 2005, Springer, 3-540-31994-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi 0001, Yasuo Takahashi |
A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 18-21 May 2005, Calgary, Canada, pp. 32-38, 2005, IEEE Computer Society, 0-7695-2336-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Yiming Li 0005, Kuen-Yu Huang |
Numerical Simulation of Self-heating InGaP/GaAs Heterojunction Bipolar Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science (3) ![In: Computational Science - ICCS 2005, 5th International Conference, Atlanta, GA, USA, May 22-25, 2005, Proceedings, Part III, pp. 292-299, 2005, Springer, 3-540-26044-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Walid Elgharbawy, Pradeep Golconda, Ashok Kumar 0001, Magdy A. Bayoumi |
A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4697-4700, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Pedro F. Vieira, Leonardo Bruno de Sá, João P. B. Botelho, Antonio Carneiro de Mesquita Filho |
Evolutionary Synthesis of Analog Circuits Using Only MOS Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 6th NASA / DoD Workshop on Evolvable Hardware (EH 2004), 24-26 June 2004, Seattle, WA, USA, pp. 38-45, 2004, IEEE Computer Society, 0-7695-2145-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Ulf Schlichtmann |
Systems Are Made from Transistors: UDSM Technology Creates New Challenges for Library and IC Development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 2-3, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Jung Hyun Choi, Sergio Bampi |
OTA Amplifiers Design on Digital Sea-of-Transistors Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 776-777, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta 0002, Melvin A. Breuer |
An integrated system for assigning signal flow directions to CMOS transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12), pp. 1445-1458, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
26 | Yusuf Leblebici, Sung-Mo Kang |
Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(2), pp. 235-246, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
26 | M. Sytrzycki |
Modeling of gate oxide shorts in MOS transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(3), pp. 193-202, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
26 | Geoffrey M. Brown, Miriam Leeser |
From Programs to Transistors: Verifying Hardware Synthesis Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hardware Specification, Verification and Synthesis ![In: Hardware Specification, Verification and Synthesis: Mathematical Aspects, Mathematical Science Institute Workshop, Cornall University, Ithaca, New York, USA, July 5-7, 1989, Proceedings, pp. 129-151, 1989, Springer, 3-540-97226-9. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
25 | Liangpeng Guo, Yici Cai, Qiang Zhou 0001, Le Kang, Xianlong Hong |
A novel performance driven power gating based on distributed sleep transistor network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 255-260, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
physical design, power-gating, sleep transistors |
25 | Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab |
Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 86-91, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
reconfigurable instant-on system, ultralow-power reconfigurable computing, complementary nanoelectromechanical carbon nanotube switches, coplanar carbon nanotubes, low operation voltages, built-in energy storage, CNEMS, stable on-off state, latching mechanism, nonvolatile memory-mode operation, CMOS transistors, system development, leakage current |
25 | Yukiya Miura |
Proposal of Fault Diagnosis of Analog Circuits by Combining Operation-Region Model and X-Y Zoning Method: Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(4-6), pp. 411-423, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
MOS transistors, operation-region model, X-Y zoning method, fault diagnosis, analog circuits |
25 | Sergio Bermejo |
Independent Component Analysis for Solid-State Chemical Sensor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Intell. ![In: Appl. Intell. 24(1), pp. 61-73, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
chemical sensing, ion-selective field effect transistors, independent component analysis, array processing |
25 | Paul Beckett |
Exploiting multiple functionality for nano-scale reconfigurable systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 50-55, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
chalcogenide, double gate transistors, multi-valued RAM, multiple functionality, resonant tunneling, nanotechnology, reconfigurable systems, carbon nanotube, nanoelectronics, RTD |
25 | Adrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier |
Few electron devices: towards hybrid CMOS-SET integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 88-93, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Iinverter, hybrid CMOS-SET Circuits, single-Electron transistors, ultimate CMOS, low power, quantizer, nanoelectronics |
25 | Carlos Montemayor, Marie Sullivan, Jen-Tien Yen, Pete Wilson, Richard Evers, K. R. Kishore |
The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 196-203, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
PowerPC 603e microprocessor, low-power superscalar microprocessor, portable products, on-chip instruction, cache associativity, bus modes, 120 SPECint92, 105 SPECfp92, die size, software controllable power-down modes, power saving capability, 16 Kbyte, performance evaluation, performance, computer architecture, system design, power consumption, data cache, cache storage, microprocessor chips, frequency, system buses, portable computers, portable computers, transistors, 100 MHz |
25 | Alex G. Dickinson, Bryan D. Ackland, El-Sayed Eid, David A. Inglis, Eric R. Fossum |
Standard CMOS active pixel image sensors for multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 214-224, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
CMOS active pixel image sensors, single chip video cameras, color filter array, document capture, 1024 pixel, multimedia, multimedia systems, CMOS integrated circuits, image sensors, transistors, video cameras, gain |
25 | Víctor H. Champac, Joan Figueras |
Testability of floating gate defects in sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 202-207, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
floating gate defect testability, logic detectability conditions, defective transistors, logically untestable branches, scan path cell, CMOS latch cell, scan path flip-flops, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, simulated results, flip-flops, CMOS logic circuits, integrated circuit modelling, I/sub DDQ/ testing |
25 | S. C. Prasad, Kaushik Roy 0001 |
Circuit optimization for minimisation of power consumption under delay constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 305-309, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
power consumption minimisation, internal capacitances, series-connected transistors, multipass algorithm, transistor reordering, VLSI, delays, logic design, logic CAD, circuit layout CAD, CMOS logic circuits, minimisation, circuit optimisation, integrated circuit layout, VLSI circuits, logic gates, capacitance, circuit optimization, delay constraint, CMOS gates |
25 | Olivier Betschi, Ken Choi |
Novel 4-Transistors Ternary Inverter Circuit Using Carbon-Nanotube Field -Effect Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 2019 International SoC Design Conference, ISOCC 2019, Jeju, Korea (South), October 6-9, 2019, pp. 243-244, 2019, IEEE, 978-1-7281-2478-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Varvara Bezhenova, Alicja Malgorzata Michalowska-Forsyth |
Aspect ratio of radiation-hardened MOS transistors - Modelling of the equivalent channel dimensions of integrated MOS transistors in radiation-hardened enclosed layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Elektrotech. Informationstechnik ![In: Elektrotech. Informationstechnik 135(1), pp. 61-68, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Manoj Kumar 0005, Sandeep Kumar Arya, Sujata Pandey |
Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1201.1966, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
25 | Isabelle Ferain, Cynthia A. Colinge, Jean-Pierre Colinge |
Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Nat. ![In: Nat. 479(7373), pp. 310-316, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
25 | Marc Michaillat |
Paramètres matériau pour la simulation de transistors bipolaires à hétérojonctions Si/SiGe et Si/SiGeC. (Material parameters for the simulation of SiGe- and SiGeC-based heterojonction bipolar transistors). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2010 |
RDF |
|
25 | Maxime Feraille |
Etude du Transport dans les Transistors MOSFETs Contraints: Modélisation Multi-échelle. (Study of Transport Properties in Strained transistors MOSFETs: Multi-scale Approach). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2009 |
RDF |
|
25 | Karim Huet |
Modelisation du transport sous contrainte mecanique dans les transistors sub-65 nm pour la Microelectronique CMOS. (Modelling of carrier transport under mechanical strain for sub-65 nm CMOS transistors). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2008 |
RDF |
|
25 | Hao-Chung Kuo |
InP/InGaAs Heterojunction Bipolar Transistors and Field-Effect Transistors Grown by Gas -Source Molecular Beam Epitaxy ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1999 |
RDF |
|
19 | Joel S. Emer |
Accelerating architecture research. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2009, April 26-28, 2009, Boston, Massachusetts, USA, Proceedings, 2009, IEEE Computer Society, 978-1-4244-4184-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Charles Augustine, Arijit Raychowdhury, Yunfei Gao, Mark S. Lundstrom, Kaushik Roy 0001 |
PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 80-85, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Jun Seomun, Jae-Hyun Kim, Youngsoo Shin |
Skewed Flip-Flop and Mixed-Vt Gates for Minimizing Leakage in Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11), pp. 1956-1968, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Soman Purushothaman |
A simple 4 quadrant NMOS analog multiplier with input range equal to +/-VDD and very low THD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2008 IEEE International Conference on Electro/Information Technology, EIT 2008, held at Iowa State University, Ames, Iowa, USA, May 18-20, 2008, pp. 134-139, 2008, IEEE, 978-1-4244-2030-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Grant Martin |
Panel: Best ways to use billions of devices on a chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 801-802, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Hamed F. Dadgour, Vivek De, Kaustav Banerjee |
Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 270-277, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim |
Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 169-172, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Christian Peters, Fabian Henrici, Maurits Ortmanns, Yiannos Manoli |
High-bandwidth floating gate CMOS rectifiers with reduced voltage drop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2598-2601, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Baoyong Chi, Chun Zhang, Zhihua Wang 0001 |
Bandwidth extension for ultra-wideband CMOS low-noise amplifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 968-971, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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