Search results for "scan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
30	Zongjie Cao, Huaidong Chen, Jin Xue, Yuwen Wang	Ultrasonic C-scan Image Restoration Using Radial Basis Function Network.	ISNN (2)	2004	DBLP DOI BibTeX RDF
30	Baris Arslan, Ozgur Sinanoglu, Alex Orailoglu	Extending the Applicability of Parallel-Serial Scan Designs.	ICCD	2004	DBLP DOI BibTeX RDF
30	Dingrong Yi, Jeff Stainsby, Graham A. Wright	Intuitive and Efficient Control of Real-Time MRI Scan Plane Using a Six-Degree-of-Freedom Hardware Plane Navigator.	MICCAI (2)	2004	DBLP DOI BibTeX RDF
30	Nitin Parimi, Xiaoling Sun	Toggle-Masking for Test-per-Scan VLSI Circuits.	DFT	2004	DBLP DOI BibTeX RDF
30	Armin Würtenberger, Christofer S. Tautermann, Sybille Hellebrand	Data Compression for Multiple Scan Chains Using Dictionaries with Corrections.	ITC	2004	DBLP DOI BibTeX RDF
30	Bo Yang 0010, Kaijie Wu 0001, Ramesh Karri	Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard.	ITC	2004	DBLP DOI BibTeX RDF
30	Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng	Logic BIST with Scan Chain Segmentation.	ITC	2004	DBLP DOI BibTeX RDF
30	Irith Pomeranz, Sudhakar M. Reddy	On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression.	VLSI Design	2004	DBLP DOI BibTeX RDF
30	Kianosh Rahimi, Mani Soma	Layout driven synthesis of multiple scan chains.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
30	Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz	On test data volume reduction for multiple scan chain designs.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Decompressor, Don't care identification, Encoding techniques, Design for testability, Test data compression
30	Xiaochuan Pan, Yu Zou, Mark A. Anastasio	Data redundancy and reduced-scan reconstruction in reflectivity tomography.	IEEE Trans. Image Process.	2003	DBLP DOI BibTeX RDF
30	Luís Santos 0005, Mário Zenha Rela	Constraints on the Use of Boundary-Scan for Fault Injection.	LADC	2003	DBLP DOI BibTeX RDF
30	Huaxing Tang, Sudhakar M. Reddy, Irith Pomeranz	On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs.	ITC	2003	DBLP DOI BibTeX RDF
30	Yan Chen 0004, Randy H. Katz, John Kubiatowicz	SCAN: A Dynamic, Scalable, and Efficient Content Distribution Network.	Pervasive	2002	DBLP DOI BibTeX RDF
30	Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz	On Test Data Volume Reduction for Multiple Scan Chain Designs.	VTS	2002	DBLP DOI BibTeX RDF
30	Irith Pomeranz	On Pass/Fail Dictionaries for Scan Circuits .	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
30	Erik Larsson, Zebo Peng	Test Scheduling and Scan-Chain Division under Power Constraint.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
30	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
30	Irith Pomeranz, Sudhakar M. Reddy	A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
30	Srimat T. Chakradhar, Sujit Dey	Resynthesis and retiming for optimum partial scan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
30	Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara	New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
30	Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin	Partial-scan delay fault testing of asynchronous circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
30	Priyank Kalla, Maciej J. Ciesielski	A comprehensive approach to the partial scan problem using implicit state enumeration.	ITC	1998	DBLP DOI BibTeX RDF
30	Arun Balakrishnan, Srimat T. Chakradhar	Peripheral Partitioning and Tree Decomposition for Partial Scan.	VLSI Design	1998	DBLP DOI BibTeX RDF
30	Yoshinobu Higami, Kozo Kinoshita	Design of partially parallel scan chain.	ED&TC	1997	DBLP DOI BibTeX RDF
30	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
30	Zaifu Zhang, Robert D. McLeod	An Efficient Multiple Scan Chain Testing Scheme.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
30	Sridhar Narayanan, Melvin A. Breuer	Reconfiguration techniques for a single scan chain.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
30	Kwang-Ting (Tim) Cheng	Single-Clock Partial Scan.	IEEE Des. Test Comput.	1995	DBLP DOI BibTeX RDF
30	N. Parker Willis, Yoram Bresler	Optimal scan for time-varying tomography. I. Theoretical analysis and fundamental limitations.	IEEE Trans. Image Process.	1995	DBLP DOI BibTeX RDF
30	Weiwei Mao, Michael D. Ciletti	Reducing correlation to improve coverage of delay faults in scan-path design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
30	Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan	ScanBist: A Multifrequency Scan-Based BIST Method.	IEEE Des. Test Comput.	1994	DBLP DOI BibTeX RDF
30	Toshinobu Ono	Selecting partial scan flip-flops for circuit partitioning.	ICCAD	1994	DBLP DOI BibTeX RDF
30	Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer	Delay-fault test generation and synthesis for testability under a standard scan design methodology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
29	Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito	Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters.	DFT	2006	DBLP DOI BibTeX RDF
29	Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre	Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains.	DELTA	2006	DBLP DOI BibTeX RDF
29	Dilip K. Bhavsar, Richard A. Davies	Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor.	VTS	2002	DBLP DOI BibTeX RDF
29	Takuji Ogihara, K. Muroi, Genichi Yonemori, Shinichi Murai	MULTES/IS: An Effective and Reliable Test Generation System for Partial Scan and Non-Scan Synchronous Circuits.	DAC	1989	DBLP DOI BibTeX RDF
29	Hyungil Woo, Seokjun Jang, Sungho Kang 0001	A Secure Scan Architecture Protecting Scan Test and Scan Dump Using Skew-Based Lock and Key.	IEEE Access	2021	DBLP DOI BibTeX RDF
29	Mohammad Taherifard, Hakem Beitollahi, Fateme Jamali, Amin Norollah, Ahmad Patooghy	Mist-Scan: A Secure Scan Chain Architecture to Resist Scan-Based Attacks in Cryptographic Chips.	SoCC	2020	DBLP DOI BibTeX RDF
29	Efi Arvaniti, Yiorgos Tsiatouhas	Low-Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique.	J. Electron. Test.	2014	DBLP DOI BibTeX RDF
29	Hiroyuki Yotsuyanagi, Masayuki Yamamoto, Masaki Hashizume	Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops.	IEICE Trans. Inf. Syst.	2010	DBLP DOI BibTeX RDF
29	George Kurian, Narayana Rao, Virendra Patidar, V. Kamakoti 0001, Srivaths Ravi 0001	Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures.	J. Low Power Electron.	2009	DBLP DOI BibTeX RDF
26	Irith Pomeranz, Sudhakar M. Reddy	Synthesis for Broadside Testability of Transition Faults.	VTS	2008	DBLP DOI BibTeX RDF	broadside tests, standard scan, transition faults, test synthesis, full-scan circuits
26	T. M. Mak	The case for power with test.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	scan shifting, functional and scan shift speed, static and dynamic power, test, power
26	Hans A. R. Manhaeve, Stefaan Kerckenaere	An On-Chip Detection Circuit for the Verification of IC Supply Connections.	DFT	2001	DBLP DOI BibTeX RDF	IC connections, connection verification, supply current measurements, on-chip monitor, reliability, DFT, CMOS, Scan, Boundary Scan, IP core, Current monitor
26	Toshinobu Ono, Kazuo Wakui, Hitoshi Hikima, Yoshiyuki Nakamura, Masaaki Yoshida	Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	core test, design-for-testability, BIST, scan, boundary scan, test bus
26	Nur A. Touba, Bahram Pouya	Testing Embedded Cores Using Partial Isolation Rings.	VTS	1997	DBLP DOI BibTeX RDF	Intellectual Property Cores, Isolation Rings, Boundary Scan, Hill Climbing, Partial Scan, Embedded Cores, Digital Testing
26	Chauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou, Yuan-Tzu Ting	Syndrome Simulation And Syndrome Test For Unscanned Interconnects.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	unscanned interconnects, syndrome test methodology, event driven syndrome simulation, boundary scan environment, faulty syndromes, fault-free syndromes, tolerable error rate, partially scanned PCB, board level testing, test pattern generation, boundary scan testing, test length, MCM, set covering problem, simulation algorithm, weighted random patterns, test cost reduction
26	Udo Mahlstedt, Jürgen Alt, Matthias Heinitz	CURRENT: a test generation system for IDDQ testing.	VTS	1995	DBLP DOI BibTeX RDF	CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults
26	Víctor H. Champac, Joan Figueras	Testability of floating gate defects in sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	floating gate defect testability, logic detectability conditions, defective transistors, logically untestable branches, scan path cell, CMOS latch cell, scan path flip-flops, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, simulated results, flip-flops, CMOS logic circuits, integrated circuit modelling, I/sub DDQ/ testing
26	Tong Liu 0007, Fabrizio Lombardi, José Salinas	Diagnosis of interconnects and FPICs using a structured walking-1 approach.	VTS	1995	DBLP DOI BibTeX RDF	field programmable interconnect chips, structured walking-1 approach, boundary scan architectures, one-step test generation, two-step test generation, fault diagnosis, integrated circuit testing, diagnosis, automatic testing, boundary scan testing, interconnects testing, integrated circuit interconnections
26	Aamer Jaleel, Kevin B. Theobald, Simon C. Steely Jr., Joel S. Emer	High performance cache replacement using re-reference interval prediction (RRIP).	ISCA	2010	DBLP DOI BibTeX RDF	scan resistance, thrashing, shared cache, replacement
26	Rafik Bourezak, Guy Lamouche, Farida Cheriet	Artery Wall Extraction from Intravascular OCT Images.	ICIAR	2009	DBLP DOI BibTeX RDF	OCT, A-scan segmentation, intravascular imaging, image segmentation, image filtering
26	Carlos Lara 0001, Leonardo Romero, Félix Calderón	A Robust Iterative Closest Point Algorithm with Augmented Features.	MICAI	2008	DBLP DOI BibTeX RDF	Mobile Robotics, ICP, Scan Matching
26	Fernando Alfredo Auat Cheeín, Fernando di Sciascio, Teodiano Freire Bastos Filho, Ricardo O. Carelli	Towards a Probabilistic Manipulator Robot's Workspace Governed by a BCI.	BIOSTEC (Selected Papers)	2008	DBLP DOI BibTeX RDF	Probabilistic Scan Mode, Brain-Computer Interface, Robot Manipulator
26	Christian Teutsch, Dirk Berndt, Erik Trostmann, Bernhard Preim	Adaptive Real-Time Grid Generation from 3D Line Scans for fast Visualization and Data Evaluation.	IV	2007	DBLP DOI BibTeX RDF	NURBS reconstruction, scan quality evaluation, grid generation
26	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A Gated Clock Scheme for Low Power Testing of Logic Cores.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	test-per-scan, test-per-clock, low power design, low power test
26	Ahren Studer, Chenxi Wang	Adaptive Detection of Local Scanners.	ACNS	2006	DBLP DOI BibTeX RDF	Scan Detection, Security, Internet Worms
26	Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty	Test cost reduction for SOCs using virtual TAMs and lagrange multipliers.	DAC	2003	DBLP DOI BibTeX RDF	bandwidth matching, automatic test equipment (ATE), test access mechanism (TAM), scan chains, system-on-chip (SOC)
26	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPG for Combinational Cluster Interconnect Testing at Board Level.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	cluster testing, built-in self-test, BIST, boundary scan, interconnect testing
26	Prashant J. Shenoy, Harrick M. Vin	Efficient Support for Interactive Operations in Multi-Resolution Video Servers.	Multim. Syst.	1999	DBLP DOI BibTeX RDF	Multi-resolution video servers, Multi-resolution playback, Rewind, Scalable compression, Disk arrays, Fast-forward, Scan operations
26	Abhijit Jas, Nur A. Touba	Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip.	ICCD	1999	DBLP DOI BibTeX RDF	Test Vector Compression, External Testing, Built-In Self-Test, Embedded Processor, System-on-a-Chip, Automatic Test Equipment, At-Speed Testing, Scan Chains, Deterministic Testing
26	John D. Hobby	Generating Automatically Tuned Bitmaps from Outlines.	J. ACM	1993	DBLP DOI BibTeX RDF	Lova´sz basis reduction, feature recognition, fonts, scan-conversion
25	Lei Shi, Vandana Pursnani Janeja	Anomalous window discovery through scan statistics for linear intersecting paths (SSLIP).	KDD	2009	DBLP DOI BibTeX RDF	anomalous window discovery, intersecting paths, scan statistic, traffic accidents
25	David Sandberg, Krister Wolff, Mattias Wahde	A Robot Localization Method Based on Laser Scan Matching.	FIRA	2009	DBLP DOI BibTeX RDF	laser scan matching, robot pose estimation, Robot localization
25	Tsung-Ching Huang, Kwang-Ting (Tim) Cheng, Huai-Yuan Tseng, Chen-Pang Kung	Reliability analysis for flexible electronics: Case study of integrated a-Si: H TFT scan driver.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	amorphous hydrogenated silicon (a-Si:H), flexible electronics, scan driver, thin-film transistor, Reliability, threshold voltage
25	Daofang Cheng, Xiaolong Li 0001, Wenfa Qi, Bin Yang 0001	A Statistics-Based Watermarking Scheme Robust to Print-and-Scan.	ISECS	2008	DBLP DOI BibTeX RDF	print-and-scan, distribution, DCT, digital watermarking
25	Liangliang Yang, Yunfei Zhou, Haihong Pan, Wei Teng	Realization of the Synchronization Mechanism of Step and Scan Projection Lithography.	ICIRA (2)	2008	DBLP DOI BibTeX RDF	Step and scan projection lithography, state synchronization, high speed high precision motion control, synchronization control
25	Wang-Dauh Tseng	Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	transition density, switching activity during test, clique, low power testing, full scan
25	Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy 0001	Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor.	IOLTS	2006	DBLP DOI BibTeX RDF	Test-per-scan BIST, delay sensor, fault diagnosis, fault localization, test point insertion
25	Sandeep Kumar Goel, Bart Vermeulen	Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	scan-based debug, Design-for-Debug (DfD), clock gating, silicon debug, multiple-clock domains
25	Ilia Polian, Bernd Becker 0001	Multiple Scan Chain Design for Two-Pattern Testing.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	scan chain insertion, delay testing, design for test, core-based test
25	Frank te Beest, Ad M. G. Peeters, Kees van Berkel 0001, Hans G. Kerkhoff	Synchronous Full-Scan for Asynchronous Handshake Circuits.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	L1L2*, DFT, asynchronous circuits, scan design, LSSD
25	Inas Khalifa, Medhat A. Moussa, Mohamed Kamel	Range image segmentation using local approximation of scan lines with application to CAD model acquisition.	Mach. Vis. Appl.	2003	DBLP DOI BibTeX RDF	Scan lines, CAD model acquisition, Segmentation, Range images, Edge models
25	Timm Ostermann, Bernd Deutschmann	TEM-cell and surface scan to identify the electromagnetic emission of integrated circuits.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	TEM-cell method, electromagnetic emission (EME), surface scan method
25	Irith Pomeranz, Sudhakar M. Reddy	A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	scan circuits, Built-in testing, Cartesian product
25	Victor V. Zyuban, Stephen V. Kosonocky	Low power integrated scan-retention mechanism.	ISLPED	2002	DBLP DOI BibTeX RDF	balloon latch, data retention, low power, scan, leakage, latch, MTCMOS, subthreshold
25	Ilia Polian, Bernd Becker 0001	Multiple Scan Chain Design for Two-Pattern Testing.	VTS	2001	DBLP DOI BibTeX RDF	Scan chain insertion, Delay testing, Design for test, Core-based test
25	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Scan-Based Designs to Reduce Test Application Time.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	scan circuits, test application time, static test compaction
25	Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara	A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	non-scan design for testability, complete fault efficiency, controllers, at-speed test
25	Irith Pomeranz, Sudhakar M. Reddy	Test-Point Insertion to Enhance Test Compaction for Scan Designs.	DSN	2000	DBLP DOI BibTeX RDF	Scan design, test-point insertion, static test compaction
25	Peng Li 0055, Peter R. M. Jones	Automatic Editing and Curve-fitting of 3-D Surface Scan Data of the Human Body.	3DIM	1997	DBLP DOI BibTeX RDF	automatic editing, 3D surface scan data, data gap, trimming process, torso model, edge detection, curve-fitting, human body, surface approximation
25	Joseph H. Nurre	Locating Landmarks on Human Body Scan Data.	3DIM	1997	DBLP DOI BibTeX RDF	landmarks location, human body scan data, anthropometric landmarks location software, data points identification, discrete point cusp detector, cloud, anthropology, incremental approach
25	Samy Makar, Edward J. McCluskey	ATPG for scan chain latches and flip-flops.	VTS	1997	DBLP DOI BibTeX RDF	bistable element, scan chain circuit, combinational defect detection, algorithm, ATPG, automatic test pattern generation, automatic testing, stuck-at fault, flip-flop, latch, checking experiment
25	Peter Wohl, John A. Waicukauski	Using ATPG for clock rules checking in complex scan design.	VTS	1997	DBLP DOI BibTeX RDF	clock rules checking, complex scan designs, structured DFT, automated design-rules-checking, robust set of rules, clock-rule-violation detection, fast clock verification, large microprocessor design, topological circuit analysis, zero delay, user controlled verification, capture ability, port contention, cone tracing, equivalent sources, ATPG, race conditions, computer testing, timing verification
25	Wuudiann Ke	Hybrid Pin Control Using Boundary-Scan And Its Applications.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	Boundary-Scan (B-S), Hybrid Pin Control, Fault Injection, Delay Test
25	Michael Nicolaidis, O. Kebichi, Vladimir Castro Alves	Trade-offs in scan path and BIST implementations for RAMs.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	RAM test algorithms, BIST, Aliasing, signature analysis, scan path, coupling faults
25	Jung-Cheun Lien, Melvin A. Breuer	Test program synthesis for modules and chips having boundary scan.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	Board and system test, test controllers, test program synthesis, built-in self-test, design-for-test, boundary scan
25	Hyoung B. Min, William A. Rogers	A test methodology for finite state machines using partial scan design.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	loop-free circuits, test generation, ATPG, fault, partial scan
25	Don Sterba, Andy Halliday, Don McClean	ATPG and diagnostics for boards implementing boundary scan.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	1149.1, ATPG, diagnostics, boundary scan, JTAG
25	R. G. Bennetts, A. Osseyran	IEEE standard 1149.1-1990 on boundary scan: History, literature survey, and current status.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	device test, board test, 1149.1, boundary scan
25	Frans Jong, José S. Matos, José M. Ferreira	Boundary scan test, test methodology, and fault modeling.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	BST-net, PCB testing, diagnosis, fault modeling, test-pattern generation, boundary scan test
25	Colin M. Maunder, Rodham E. Tulloss	An introduction to the boundary scan standard: ANSI/IEEE Std 1149.1.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	ANSI/IEEE Std 1149.1, loaded-board test, self-test, boundary scan, JTAG
25	Yehezkel Yeshurun, Eric L. Schwartz	Shape Description with a Space-Variant Sensor: Algorithms for Scan-Path, Fusion, and Convergence Over Multiple Scans.	IEEE Trans. Pattern Anal. Mach. Intell.	1989	DBLP DOI BibTeX RDF	space-variant sensor, fixation points, multiscan view, boundary curvature, computer vision, convergence, computerised pattern recognition, fusion, machine vision, image sensors, image sensors, scan-path
25	Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee 0001, Mark Kassab	X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
25	Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	GECOM: Test data compression combined with all unknown response masking.	ASP-DAC	2008	DBLP DOI BibTeX RDF
25	Emil Gizdarski	Constructing Augmented Multimode Compactors.	VTS	2008	DBLP DOI BibTeX RDF	on-chip compression, array codes, linear codes, test data compression
25	Kaushik Dutta, Krithi Ramamritham, B. Karthik, Kamlesh Laddhad	Real-Time Event Handling in an RFID Middleware System.	DNIS	2007	DBLP DOI BibTeX RDF
25	Jing Wang, Shengbing Zhang, Zhang Meng	Testing of a 32-bit High Performance Embedded Microprocessor.	SIES	2007	DBLP DOI BibTeX RDF