Search results for "faults"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
32	Gang Chen 0011, Sudhakar M. Reddy, Irith Pomeranz	Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits.	ICCD	2003	DBLP DOI BibTeX RDF
32	Hiroshi Takahashi, Kwame Osei Boateng, Kewal K. Saluja, Yuzo Takamatsu	On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
32	Ramesh C. Tekumalla, Scott Davidson 0001	On Identifying Indistinguishable Path Delay Faults and Improving Diagnosis.	ITC	2002	DBLP DOI BibTeX RDF
32	Mikhail Nesterenko, Anish Arora	Tolerance to Unbounded Byzantine Faults.	SRDS	2002	DBLP DOI BibTeX RDF
32	R. David, Janusz A. Brzozowski, Helmut Jürgensen	Testing for Bounded Faults in RAMs.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	bounded fault, testing, Markov chain, random test, RAM, test length, deterministic test
32	Ad J. van de Goor, Georgi Gaydadjiev	Realistic Linked Memory Cell Array Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
32	Noriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima	Fault simulation for multiple faults by Boolean function manipulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
32	Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker 0001	Modeling Feedback Bridging Faults with Non-Zero Resistance.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	feedback bridging faults, resistive bridging faults, bridging fault simulation
32	Irith Pomeranz, Sudhakar M. Reddy	Vector-Based Functional Fault Models for Delay Faults.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	functional tests, delay faults, path delay faults
32	Yinong Chen, Winfried Bücken, Klaus Echtle	Efficient Algorithms for System Diagnosis with Both Processor and Comparator Faults.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	processor faults, comparison-based self-diagnosis, multiprocessorsystems, comparator faults, O(mod E mod)/sup 2/ algorithm, computational complexity, fault tolerant computing, multiprocessing systems, system diagnosis
31	Kinga Dobolyi, Westley Weimer	Modeling consumer-perceived web application fault severities for testing.	ISSTA	2010	DBLP DOI BibTeX RDF	web application, fault, severity
31	Alireza Rohani, Hamid R. Zarandi	An Analysis of Fault Effects and Propagations in AVR Microcontroller ATmega103(L).	ARES	2009	DBLP DOI BibTeX RDF
31	Gursimran Singh Walia, Jeffrey C. Carver	The Effect of the Number of Defects on Estimates Produced by Capture-Recapture Models.	ISSRE	2008	DBLP DOI BibTeX RDF
31	Raja K. K. R. Sandireddy, Vishwani D. Agrawal	Diagnostic and Detection Fault Collapsing for Multiple Output Circuits.	DATE	2005	DBLP DOI BibTeX RDF
31	Diamantino Costa, Tiago Rilho, Henrique Madeira	Joint Evaluation of Performance and Robustness of a COTS DBMS through Fault-Injection.	DSN	2000	DBLP DOI BibTeX RDF
31	Irith Pomeranz, W. Kent Fuchs	A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
31	Irith Pomeranz, Sudhakar M. Reddy	A diagnostic test generation procedure for synchronous sequential circuits based on test elimination.	ITC	1998	DBLP DOI BibTeX RDF
31	Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita	Synthesis of Sequential Circuits by Redundancy Removal and Retiming.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	synthesis of sequential circuits, sequentially redundant fault, retiming, redundant fault, redundancy removal
31	Kanad Chakraborty, Pinaki Mazumder	Technology and layout-related testing of static random-access memories.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Array layout, cell technology, Gallium Arsenide (GaAs), high electron mobility transistor (HEMT) RAMs, I DD testing, I DDQ testing
31	Jan Ploski, Matthias Rohr, Peter Schwenkenberg, Wilhelm Hasselbring	Research issues in software fault categorization.	ACM SIGSOFT Softw. Eng. Notes	2007	DBLP DOI BibTeX RDF	injection of software faults, software fault categorization, software reliability, bugs, software faults
31	Andrzej Pelc, David Peleg	Feasibility and complexity of broadcasting with random transmission failures.	PODC	2005	DBLP DOI BibTeX RDF	omission faults, random failures, broadcasting, radio networks, Byzantine faults
31	Wanlin Cao, Dhiraj K. Pradhan	Sequential redundancy identification using recursive learning.	ICCAD	1996	DBLP DOI BibTeX RDF	ISCAS benchmarks, c-cycle redundancies, c-cycle redundant faults, redundancy identification algorithm, sequential redundancy identification, state transition information, uncontrollability analysis, logic CAD, FIRES, untestable faults, recursive learning
31	Wuudiann Ke, Premachandran R. Menon	Multifault and delay-fault testability of multilevel circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	testing, testability, delay-faults, multiple stuck-at faults
31	Chunduri Rama Mohan, Partha Pratim Chakrabarti	Combined optimization of area and testability during state assignment of PLA-based FSM's.	VLSI Design	1995	DBLP DOI BibTeX RDF	combined optimization, testability optimisation, PLA-based FSM, EARTH algorithm, single cross-point faults, redundancy checker, fault diagnosis, logic testing, redundancy, finite state machines, integrated circuit testing, design for testability, fault model, logic CAD, programmable logic arrays, circuit layout CAD, circuit optimisation, integrated circuit layout, state assignment, state assignment, minimisation of switching nets, single stuck-at faults, area minimization
31	Weiwei Mao, Ravi K. Gulati	Quietest: A methodology for selecting IDDQ test vectors.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	weak faults, I DDQ testing, Leakage faults
30	Jiangang Yi, Peng Zeng	Analysis of Two Neural Networks in the Intelligent Faults Diagnosis of Metallurgic Fan Machinery.	ISNN (3)	2009	DBLP DOI BibTeX RDF	Metallurgic fan machinery, Intelligent faults diagnosis, ANN
30	Irith Pomeranz, Sudhakar M. Reddy	Synthesis for Broadside Testability of Transition Faults.	VTS	2008	DBLP DOI BibTeX RDF	broadside tests, standard scan, transition faults, test synthesis, full-scan circuits
30	Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	BIST, delay faults, look-up table
30	Carlos Arthur Lang Lisbôa, Erik Schüler, Luigi Carro	Going beyond TMR for protection against multiple faults.	SBCCI	2005	DBLP DOI BibTeX RDF	future technologies, simultaneous transient faults, fault tolerance, design techniques
30	Irene Finocchi, Giuseppe F. Italiano	Sorting and searching in the presence of memory faults (without redundancy).	STOC	2004	DBLP DOI BibTeX RDF	memory faults, searching, sorting, memory models, combinatorial algorithms
30	Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar	Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories.	VLSI Design	2004	DBLP DOI BibTeX RDF	Built-in self-test for memories, neighbourhood pattern sensitive faults, programmable BIST
30	Wei Li 0023, Sudhakar M. Reddy, Irith Pomeranz	On test generation for transition faults with minimized peak power dissipation.	DAC	2004	DBLP DOI BibTeX RDF	test generation, power dissipation, transition faults
30	Yukiya Miura, Shuichi Seno	Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	fault behavior, feedback bridging faults, IDDQ testing, CMOS circuits, fault analysis
30	Thomas J. Ostrand, Elaine J. Weyuker	The distirubtion of faults in a large industrial software system.	ISSTA	2002	DBLP DOI BibTeX RDF	software testing, empirical study, software faults, fault-prone, pareto
30	Zaid Al-Ars, Ad J. van de Goor	Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests.	MTDT	2001	DBLP DOI BibTeX RDF	detection conditions, memory testing, DRAMs, transient faults, functional fault models, defect simulation
30	Emil Gizdarski	Detection of Delay Faults in Memory Address Decoders.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	Built-In Self-Test, delay testing, stuck-open faults, RAM testing
30	Hakan Aydin, Rami G. Melhem, Daniel Mossé	Optimal scheduling of imprecise computation tasks in the presence of multiple faults.	RTCSA	2000	DBLP DOI BibTeX RDF	imprecise computation tasks, real-time computing models, nondecreasing reward function, FT Optimal framework, transient fault tolerance, scheduling, real-time systems, image processing, multimedia, software fault tolerance, multiple faults, speech processing, optimal scheduling
30	Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Toshiyuki Matsunaga	A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	marginal delay, test generation, combinational circuit, gate delay faults
30	Alvernon Walker, Algernon P. Henry, Parag K. Lala	An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring.	DFT	1997	DBLP DOI BibTeX RDF	bridging faults detection, CMOS domino logic circuits, dynamic power supply current monitoring, CMOS logic circuits, transient current
30	Sreejit Chakravarty, Paul J. Thadikaran	Algorithms to select IDDQ measurement points to detect bridging faults.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	bridging faults, test selection, I DDQ test
30	Heidrun Engel	Data flow transformations to detect results which are corrupted by hardware faults.	HASE	1996	DBLP DOI BibTeX RDF	data flow transformations, corrupt result detection, hardware fault coverage, modified instruction, diverse data representation, modified instruction sequences, assembler level, high language level, fault tolerant computing, software faults, design diversity, hardware fault detection
30	Mukund Sivaraman, Andrzej J. Strojwas	A diagnosability metric for parametric path delay faults.	VTS	1996	DBLP DOI BibTeX RDF	diagnosability metric, parametric path delay faults, test vector pairs, chip failure, fabrication process parameter variations, diagnosis framework, ISCAS'89 benchmark circuits, VLSI, fault diagnosis, logic testing, delays, timing, integrated circuit testing, failure analysis, diagnosability, delay fault testing, test set
30	Mukund Sivaraman, Andrzej J. Strojwas	Diagnosis of parametric path delay faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	parametric path delay faults, chip failure, fabrication process parameter values, path sensitization mechanism, path delay conditions, ISCAS'89 benchmark circuits, path segment, circuit failure, fault diagnosis, logic testing, logic testing, delays, probability, probability, statistical analysis, statistical analysis, integrated circuit testing, failure analysis, diagnosability, delay fault testing, IC testing, production testing
30	Hsing-Chung Liang, Chung-Len Lee 0001, Jwu E. Chen	Identifying Untestable Faults in Sequential Circuits.	IEEE Des. Test Comput.	1995	DBLP DOI BibTeX RDF	initializable, invalid states, controllability, test generation, untestable faults
30	Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu	Generation of tenacious tests for small gate delay faults in combinational circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	tenacious tests, small gate delay faults, single gate delay fault, ISCAS'85 benchmark circuits, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuits, fault coverage
30	Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey	A simple technique for locating gate-level faults in combinational circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	electron probe analysis, optical microscopy, gate-level faults, error sources, fault deduction, fault elimination, ISCAS'85 benchmark circuits, physical defect analysis, electron beam probing, light emission microscopy, computational complexity, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, digital simulation, circuit analysis computing, computation time, scanning electron microscopy, scanning electron microscopy, diagnostic resolution
30	Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal	An efficient automatic test generation system for path delay faults in combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	automatic test generation system, test pattern generation system, nonrobust tests, nine-value logic system, multiple backtrace procedure, path selection method, logic testing, delays, integrated circuit testing, fault detection, ATPG, combinational circuits, combinational circuits, automatic testing, fault location, multivalued logic, logic circuits, integrated logic circuits, path delay faults, robust tests
30	Tapan J. Chakraborty, Vishwani D. Agrawal	Robust testing for stuck-at faults.	VLSI Design	1995	DBLP DOI BibTeX RDF	logic circuit testing, d-robust tests, fault diagnosis, logic testing, delays, sequential circuits, sequential circuits, fault models, combinational circuits, combinational circuit, robust testing, single stuck-at faults, circuit models
30	Irith Pomeranz, Sudhakar M. Reddy	Fault Collapsing for Transition Faults Using Extended Transition Faults.	ETS	2006	DBLP DOI BibTeX RDF
29	Abdul-Rahman Mawlood-Yunis	Fault-tolerant semantic mappings among heterogeneous and distributed local ontologies.	ONISW	2008	DBLP DOI BibTeX RDF	consensus reaching, heterogeneous information sources, semantic conflicts, temporal faults, interoperability, ontology mapping, emergent semantics
29	Vimal K. Reddy, Eric Rotenberg, Sailashri Parthasarathy	Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance.	ASPLOS	2006	DBLP DOI BibTeX RDF	redundant multithreading, simultaneous multithreading (SMT), slipstream processor, chip multiprocessor (CMP), branch prediction, transient faults, value prediction, time redundancy
29	M. Ümit Uyar, Yu Wang 0012, Samrat S. Batth, Adriana Wise, Mariusz A. Fecko	Timing Fault Models for Systems with Multiple Timers.	TestCom	2005	DBLP DOI BibTeX RDF	Timer Constraints, Fault Modeling, Timed Automata, Conformance Testing, Multiple Faults
29	Irith Pomeranz, Sudhakar M. Reddy	A Measure of Quality for n-Detection Test Sets.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	n-detection tests, test set ordering, unmodeled faults
29	Ronald D. Blanton, John P. Hayes	On the properties of the input pattern fault model.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	fault testing, testing digital circuits, ATPG, fault models, faults, defects
29	Roger T. Alexander, James M. Bieman, Sudipto Ghosh, Bixia Ji	Mutation of Java Objects.	ISSRE	2002	DBLP DOI BibTeX RDF	Java, software testing, object-oriented programming, testability, Faults, mutation analysis, test adequacy
29	Lorenzo Alvisi, Evelyn Tumlin Pierce, Dahlia Malkhi, Michael K. Reiter, Rebecca N. Wright	Dynamic Byzantine Quorum Systems.	DSN	2000	DBLP DOI BibTeX RDF	fault tolerance, dynamic reconfiguration, quorum systems, Byzantine faults
29	Jun-Weir Lin, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen	Fault diagnosis for linear analog circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	discrete signal flow graph, equivalent faults, fault diagnosis, fault diagnosis, signal flow graphs, analogue circuits, linear analog circuits
29	Dimiter R. Avresky	Embedding and Reconfiguration of Spanning Trees in Faulty Hypercubes.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	single and multiple faults, Fault tolerance, reconfiguration, spanning trees, faulty hypercubes
29	Avinash Munshi, Fred J. Meyer, Fabrizio Lombardi	A New Method for Testing EEPLA's.	DFT	1998	DBLP DOI BibTeX RDF	EEPLA, testing, multiple faults, PLD
29	Chih Wei Hu, Chung-Len Lee 0001, Wen Ching Wu, Jwu E. Chen	Fault diagnosis of odd-even sorting networks.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	odd-even sorting networks, location tests, sorting element faults, binary search procedures, fault diagnosis, fault diagnosis, Banyan networks, switching system, ISDN
29	Sandeep S. Kulkarni, Anish Arora	Once-and-for all management protocol (OFMP).	ICNP	1997	DBLP DOI BibTeX RDF	once-and-forall management protocol, network management protocol, management information bases, fault-tolerance masking, eventually-detectable faults, protocols
29	David S. Rosenblum	A Practical Approach to Programming With Assertions.	IEEE Trans. Software Eng.	1995	DBLP DOI BibTeX RDF	Anna, APP, formal specifications, formal methods, C, programming environments, assertions, consistency checking, software faults, runtime checking
29	Steven J. Zeil	Perturbation Techniques for Detecting Domain Errors.	IEEE Trans. Software Eng.	1989	DBLP DOI BibTeX RDF	sensitivity measures, individual test points, domain errors, perturbing functions, potential faults, standard optimization techniques, novel test-data-generation method, arithmetic fault detection, perturbation techniques, software testing, error detection, error detection, program testing, test set, vector space, arithmetic expressions
29	Manoj Franklin, Kewal K. Saluja	Hypergraph Coloring and Reconfigured RAM Testing.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	hypergraph coloring, reconfigured RAM testing, RAM decoders, critical path lengths, memory chips, physical neighborhood pattern sensitive faults, reconfigured DRAMs, decoder faults, computational complexity, logic testing, redundancy, reconfigurable architectures, stuck-at faults, graph colouring, random-access storage, integrated memory circuits, test lengths, test algorithms, DRAM chips, silicon area
29	Younès Karkouri, El Mostapha Aboulhamid, Eduard Cerny, Alain Verreault	Use of Fault Dropping for Multiple Fault Analysis.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	fault dropping, multiple fault analysis, frontier faults, fault-free circuit, logic testing, stuck at faults, logic circuits, logic circuits, combinatorial circuits, benchmark circuits, gate level, fault collapsing, multiple stuck at faults
29	Tein-Hsiang Lin, Kang G. Shin	An Optimal Retry Policy Based on Fault Classification.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	optimal retry policy, fault characteristics, mission lifetime, system status, Bayesian decision problem, prior distributions, fault-related parameter updating, temporal fault type, fault parameter estimation, optimal retry period, mean task completion time minimization, fault tolerant computing, parameter estimation, fault detection, error detection, decision theory, system recovery, Bayes methods, minimisation, error recovery, transient faults, failure analysis, intermittent faults, permanent faults, fault classification
29	Che-Liang Yang, Gerald M. Masson	A New Measure for Hybrid Fault Diagnosability.	IEEE Trans. Computers	1987	DBLP DOI BibTeX RDF	test assignment, hard faults, hybrid faults, Fault diagnosis, PMC models, syndrome, soft faults
29	Kozo Kinoshita, Kewal K. Saluja	Built-In Testing of Memory Using an On-Chip Compact Testing Scheme.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	weight-sensitive faults, random- access memory (RAM), Built-in self-testing (BIST), stuck-at faults, built-in testing (BIT), pattern-sensitive faults, hardware complexity
29	Barry R. Borgerson, Richard F. Freitas	A Reliability Model for Gracefully Degrading and Standby-Sparing Systems.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	gracefully degrading, resource exhaustion, solitary faults, space-domain multiple faults, standby sparing, time-domain multiple faults, Fault tolerance, reliability, PRIME
28	Albert Meixner, Daniel J. Sorin	Detouring: Translating software to circumvent hard faults in simple cores.	DSN	2008	DBLP DOI BibTeX RDF
28	Man-Lap Li, Pradeep Ramachandran, Swarup Kumar Sahoo, Sarita V. Adve, Vikram S. Adve, Yuanyuan Zhou	Trace-based microarchitecture-level diagnosis of permanent hardware faults.	DSN	2008	DBLP DOI BibTeX RDF
28	Bogdan Tomoyuki Nassu, Kiyonobu Uehara, Takashi Nanya	Injecting Inconsistent Values Caused by Interaction Faults for Experimental Dependability Evaluation.	EDCC	2008	DBLP DOI BibTeX RDF
28	Antonio Carzaniga, Alessandra Gorla, Mauro Pezzè	Handling Software Faults with Redundancy.	WADS	2008	DBLP DOI BibTeX RDF
28	Michael Hutter, Jörn-Marc Schmidt, Thomas Plos	RFID and Its Vulnerability to Faults.	CHES	2008	DBLP DOI BibTeX RDF	Antenna Tearing, Optical Injections, RFID, Fault Analysis, Implementation Attacks, Electromagnetic Analysis
28	Fred A. Bower, Daniel J. Sorin, Sule Ozev	Online diagnosis of hard faults in microprocessors.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	Hard fault tolerance, fine-grained diagnosis, processor microarchitecture
28	Irith Pomeranz, Sudhakar M. Reddy	Diagnostic Test Generation Based on Subsets of Faults.	ETS	2007	DBLP DOI BibTeX RDF
28	Yu-Chiun Lin, Shi-Yu Huang	Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	multiple fault diagnosis, prime candidate, fault diagnosis, debugging, yield
28	David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil	Run-Time Reconfiguration for Emulating Transient Faults in VLSI Systems.	DSN	2006	DBLP DOI BibTeX RDF
28	Loganathan Lingappan, Niraj K. Jha	Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
28	Luca Schiano, Marco Ottavi, Fabrizio Lombardi, Salvatore Pontarelli, Adelio Salsano	On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories.	DATE	2005	DBLP DOI BibTeX RDF
28	Fred A. Bower, Daniel J. Sorin, Sule Ozev	A Mechanism for Online Diagnosis of Hard Faults in Microprocessors.	MICRO	2005	DBLP DOI BibTeX RDF
28	Zhigang Jiang, Sandeep K. Gupta 0001	Threshold testing: Covering bridging and other realistic faults.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
28	Daniel Gil, Joaquin Gracia, Juan Carlos Baraza, Pedro J. Gil	Impact of Faults in Combinational Logic of Commercial Microcontrollers.	EDCC	2005	DBLP DOI BibTeX RDF
28	Jin-Fu Li 0001, Chou-Kun Lin	Modeling and Testing Comparison Faults for Ternary Content Addressable Memories.	VTS	2005	DBLP DOI BibTeX RDF
28	Dubravka Ilic, Elena Troubitsyna	Formal Development of Software for Tolerating Transient Faults.	PRDC	2005	DBLP DOI BibTeX RDF
28	Yu-Chiun Lin, Shi-Yu Huang	Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
28	Henrique Madeira, João Durães, Marco Vieira	Emulation of Software Faults: Representativeness and Usefulness.	LADC	2003	DBLP DOI BibTeX RDF
28	Mohammad Gh. Mohammad, Kewal K. Saluja	Electrical Model For Program Disturb Faults in Non-Volatile Memories.	VLSI Design	2003	DBLP DOI BibTeX RDF
28	Ilia Polian, Irith Pomeranz, Bernd Becker 0001	Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	n-detection, BDDs, formal techniques, Fault dominance
28	Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri	On the Propagation of Faults and Their Detection in a Hardware Implementation of the Advanced Encryption Standard.	ASAP	2002	DBLP DOI BibTeX RDF
28	Cecilia Metra, Stefano Di Francescantonio, T. M. Mak	Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing.	ITC	2002	DBLP DOI BibTeX RDF
28	Marco Vieira, Henrique Madeira	Definition of Faultloads Based on Operator Faults for DMBS Recovery Benchmarking.	PRDC	2002	DBLP DOI BibTeX RDF
28	André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand	On the detectability of CMOS floating gate transistor faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
28	Diamantino Costa, Tiago Rilho, Marco Vieira, Henrique Madeira	ESFFI - A Novel Technique for the Emulation of Coftware Faults in COTS Components.	ECBS	2001	DBLP DOI BibTeX RDF
28	Said Hamdioui, Ad J. van de Goor, David Eastwick, Mike Rodgers	Detecting Unique Faults in Multi-port SRAMs.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
28	Chuan-Ching Sue, Sy-Yen Kuo	Restoration from Multiple Faults in WDM Networks without Wavelength Conversion.	ICN (1)	2001	DBLP DOI BibTeX RDF
28	Joan Carletta, Christos A. Papachristou, Mehrdad Nourani	Detecting Undetectable Controller Faults Using Power Analysis.	DATE	2000	DBLP DOI BibTeX RDF
28	Abderrahim Doumar, Hideo Ito	Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources.	DFT	2000	DBLP DOI BibTeX RDF
28	Jue Wu, Elizabeth M. Rudnick	A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults.	VLSI Design	1999	DBLP DOI BibTeX RDF
28	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF