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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 10002 occurrences of 3019 keywords
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Results
Found 11893 publication records. Showing 11893 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
32 | Gang Chen 0011, Sudhakar M. Reddy, Irith Pomeranz |
Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 36-41, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Hiroshi Takahashi, Kwame Osei Boateng, Kewal K. Saluja, Yuzo Takamatsu |
On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(3), pp. 362-368, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Ramesh C. Tekumalla, Scott Davidson 0001 |
On Identifying Indistinguishable Path Delay Faults and Improving Diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 993-1002, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Mikhail Nesterenko, Anish Arora |
Tolerance to Unbounded Byzantine Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SRDS ![In: 21st Symposium on Reliable Distributed Systems (SRDS 2002), 13-16 October 2002, Osaka, Japan, pp. 22-, 2002, IEEE Computer Society, 0-7695-1659-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | R. David, Janusz A. Brzozowski, Helmut Jürgensen |
Testing for Bounded Faults in RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 10(3), pp. 197-214, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
bounded fault, testing, Markov chain, random test, RAM, test length, deterministic test |
32 | Ad J. van de Goor, Georgi Gaydadjiev |
Realistic Linked Memory Cell Array Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 183-188, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
32 | Noriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima |
Fault simulation for multiple faults by Boolean function manipulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(4), pp. 531-535, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
32 | Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker 0001 |
Modeling Feedback Bridging Faults with Non-Zero Resistance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(1), pp. 57-69, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
feedback bridging faults, resistive bridging faults, bridging fault simulation |
32 | Irith Pomeranz, Sudhakar M. Reddy |
Vector-Based Functional Fault Models for Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 41-46, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
functional tests, delay faults, path delay faults |
32 | Yinong Chen, Winfried Bücken, Klaus Echtle |
Efficient Algorithms for System Diagnosis with Both Processor and Comparator Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(4), pp. 371-381, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
processor faults, comparison-based self-diagnosis, multiprocessorsystems, comparator faults, O(mod E mod)/sup 2/ algorithm, computational complexity, fault tolerant computing, multiprocessing systems, system diagnosis |
31 | Kinga Dobolyi, Westley Weimer |
Modeling consumer-perceived web application fault severities for testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSTA ![In: Proceedings of the Nineteenth International Symposium on Software Testing and Analysis, ISSTA 2010, Trento, Italy, July 12-16, 2010, pp. 97-106, 2010, ACM, 978-1-60558-823-0. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
web application, fault, severity |
31 | Alireza Rohani, Hamid R. Zarandi |
An Analysis of Fault Effects and Propagations in AVR Microcontroller ATmega103(L). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARES ![In: Proceedings of the The Forth International Conference on Availability, Reliability and Security, ARES 2009, March 16-19, 2009, Fukuoka, Japan, pp. 166-172, 2009, IEEE Computer Society, 978-1-4244-3572-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
31 | Gursimran Singh Walia, Jeffrey C. Carver |
The Effect of the Number of Defects on Estimates Produced by Capture-Recapture Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSRE ![In: 19th International Symposium on Software Reliability Engineering (ISSRE 2008), 11-14 November 2008, Seattle/Redmond, WA, USA, pp. 305-306, 2008, IEEE Computer Society, 978-0-7695-3405-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Raja K. K. R. Sandireddy, Vishwani D. Agrawal |
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 1014-1019, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Diamantino Costa, Tiago Rilho, Henrique Madeira |
Joint Evaluation of Performance and Robustness of a COTS DBMS through Fault-Injection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2000 International Conference on Dependable Systems and Networks (DSN 2000) (formerly FTCS-30 and DCCA-8), 25-28 June 2000, New York, NY, USA, pp. 251-260, 2000, IEEE Computer Society, 0-7695-0707-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
31 | Irith Pomeranz, W. Kent Fuchs |
A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 486-491, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
31 | Irith Pomeranz, Sudhakar M. Reddy |
A diagnostic test generation procedure for synchronous sequential circuits based on test elimination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 1074-1083, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
31 | Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita |
Synthesis of Sequential Circuits by Redundancy Removal and Retiming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(1), pp. 81-92, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
synthesis of sequential circuits, sequentially redundant fault, retiming, redundant fault, redundancy removal |
31 | Kanad Chakraborty, Pinaki Mazumder |
Technology and layout-related testing of static random-access memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 5(4), pp. 347-365, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
Array layout, cell technology, Gallium Arsenide (GaAs), high electron mobility transistor (HEMT) RAMs, I DD testing, I DDQ testing |
31 | Jan Ploski, Matthias Rohr, Peter Schwenkenberg, Wilhelm Hasselbring |
Research issues in software fault categorization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGSOFT Softw. Eng. Notes ![In: ACM SIGSOFT Softw. Eng. Notes 32(6), 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
injection of software faults, software fault categorization, software reliability, bugs, software faults |
31 | Andrzej Pelc, David Peleg |
Feasibility and complexity of broadcasting with random transmission failures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODC ![In: Proceedings of the Twenty-Fourth Annual ACM Symposium on Principles of Distributed Computing, PODC 2005, Las Vegas, NV, USA, July 17-20, 2005, pp. 334-341, 2005, ACM, 1-58113-994-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
omission faults, random failures, broadcasting, radio networks, Byzantine faults |
31 | Wanlin Cao, Dhiraj K. Pradhan |
Sequential redundancy identification using recursive learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 56-62, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
ISCAS benchmarks, c-cycle redundancies, c-cycle redundant faults, redundancy identification algorithm, sequential redundancy identification, state transition information, uncontrollability analysis, logic CAD, FIRES, untestable faults, recursive learning |
31 | Wuudiann Ke, Premachandran R. Menon |
Multifault and delay-fault testability of multilevel circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(3), pp. 333-336, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
testing, testability, delay-faults, multiple stuck-at faults |
31 | Chunduri Rama Mohan, Partha Pratim Chakrabarti |
Combined optimization of area and testability during state assignment of PLA-based FSM's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 408-413, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
combined optimization, testability optimisation, PLA-based FSM, EARTH algorithm, single cross-point faults, redundancy checker, fault diagnosis, logic testing, redundancy, finite state machines, integrated circuit testing, design for testability, fault model, logic CAD, programmable logic arrays, circuit layout CAD, circuit optimisation, integrated circuit layout, state assignment, state assignment, minimisation of switching nets, single stuck-at faults, area minimization |
31 | Weiwei Mao, Ravi K. Gulati |
Quietest: A methodology for selecting IDDQ test vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(4), pp. 349-357, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
weak faults, I DDQ testing, Leakage faults |
30 | Jiangang Yi, Peng Zeng |
Analysis of Two Neural Networks in the Intelligent Faults Diagnosis of Metallurgic Fan Machinery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (3) ![In: Advances in Neural Networks - ISNN 2009, 6th International Symposium on Neural Networks, ISNN 2009, Wuhan, China, May 26-29, 2009, Proceedings, Part III, pp. 755-761, 2009, Springer, 978-3-642-01512-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Metallurgic fan machinery, Intelligent faults diagnosis, ANN |
30 | Irith Pomeranz, Sudhakar M. Reddy |
Synthesis for Broadside Testability of Transition Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 221-226, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
broadside tests, standard scan, transition faults, test synthesis, full-scan circuits |
30 | Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell |
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(2), pp. 161-172, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
BIST, delay faults, look-up table |
30 | Carlos Arthur Lang Lisbôa, Erik Schüler, Luigi Carro |
Going beyond TMR for protection against multiple faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 80-85, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
future technologies, simultaneous transient faults, fault tolerance, design techniques |
30 | Irene Finocchi, Giuseppe F. Italiano |
Sorting and searching in the presence of memory faults (without redundancy). ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 36th Annual ACM Symposium on Theory of Computing, Chicago, IL, USA, June 13-16, 2004, pp. 101-110, 2004, ACM, 1-58113-852-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
memory faults, searching, sorting, memory models, combinatorial algorithms |
30 | Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar |
Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 753-756, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Built-in self-test for memories, neighbourhood pattern sensitive faults, programmable BIST |
30 | Wei Li 0023, Sudhakar M. Reddy, Irith Pomeranz |
On test generation for transition faults with minimized peak power dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 504-509, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
test generation, power dissipation, transition faults |
30 | Yukiya Miura, Shuichi Seno |
Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(2), pp. 109-120, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
fault behavior, feedback bridging faults, IDDQ testing, CMOS circuits, fault analysis |
30 | Thomas J. Ostrand, Elaine J. Weyuker |
The distirubtion of faults in a large industrial software system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSTA ![In: Proceedings of the International Symposium on Software Testing and Analysis, ISSTA 2002, Roma, Italy, July 22-24, 2002, pp. 55-64, 2002, ACM, 1-58113-562-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
software testing, empirical study, software faults, fault-prone, pareto |
30 | Zaid Al-Ars, Ad J. van de Goor |
Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 9th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2001), 6-7 August 2001, San Jose, CA, USA, pp. 59-64, 2001, IEEE Computer Society, 0-7695-1242-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
detection conditions, memory testing, DRAMs, transient faults, functional fault models, defect simulation |
30 | Emil Gizdarski |
Detection of Delay Faults in Memory Address Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(4), pp. 381-387, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Built-In Self-Test, delay testing, stuck-open faults, RAM testing |
30 | Hakan Aydin, Rami G. Melhem, Daniel Mossé |
Optimal scheduling of imprecise computation tasks in the presence of multiple faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 7th International Workshop on Real-Time Computing and Applications Symposium (RTCSA 2000), 12-14 December 2000, Cheju Island, South Korea, pp. 289-296, 2000, IEEE Computer Society, 0-7695-0930-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
imprecise computation tasks, real-time computing models, nondecreasing reward function, FT Optimal framework, transient fault tolerance, scheduling, real-time systems, image processing, multimedia, software fault tolerance, multiple faults, speech processing, optimal scheduling |
30 | Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Toshiyuki Matsunaga |
A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 320-325, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
marginal delay, test generation, combinational circuit, gate delay faults |
30 | Alvernon Walker, Algernon P. Henry, Parag K. Lala |
An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 272-280, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
bridging faults detection, CMOS domino logic circuits, dynamic power supply current monitoring, CMOS logic circuits, transient current |
30 | Sreejit Chakravarty, Paul J. Thadikaran |
Algorithms to select IDDQ measurement points to detect bridging faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(3), pp. 275-285, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
bridging faults, test selection, I DDQ test |
30 | Heidrun Engel |
Data flow transformations to detect results which are corrupted by hardware faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HASE ![In: 1st High-Assurance Systems Engineering Workshop (HASE '96), October 22, 1996, Niagara, Canada, Proceedings, pp. 279-, 1996, IEEE Computer Society, 0-8186-7629-9. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
data flow transformations, corrupt result detection, hardware fault coverage, modified instruction, diverse data representation, modified instruction sequences, assembler level, high language level, fault tolerant computing, software faults, design diversity, hardware fault detection |
30 | Mukund Sivaraman, Andrzej J. Strojwas |
A diagnosability metric for parametric path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 316-323, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
diagnosability metric, parametric path delay faults, test vector pairs, chip failure, fabrication process parameter variations, diagnosis framework, ISCAS'89 benchmark circuits, VLSI, fault diagnosis, logic testing, delays, timing, integrated circuit testing, failure analysis, diagnosability, delay fault testing, test set |
30 | Mukund Sivaraman, Andrzej J. Strojwas |
Diagnosis of parametric path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 412-417, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
parametric path delay faults, chip failure, fabrication process parameter values, path sensitization mechanism, path delay conditions, ISCAS'89 benchmark circuits, path segment, circuit failure, fault diagnosis, logic testing, logic testing, delays, probability, probability, statistical analysis, statistical analysis, integrated circuit testing, failure analysis, diagnosability, delay fault testing, IC testing, production testing |
30 | Hsing-Chung Liang, Chung-Len Lee 0001, Jwu E. Chen |
Identifying Untestable Faults in Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 12(3), pp. 14-23, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
initializable, invalid states, controllability, test generation, untestable faults |
30 | Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu |
Generation of tenacious tests for small gate delay faults in combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 332-338, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
tenacious tests, small gate delay faults, single gate delay fault, ISCAS'85 benchmark circuits, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuits, fault coverage |
30 | Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey |
A simple technique for locating gate-level faults in combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 65-70, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
electron probe analysis, optical microscopy, gate-level faults, error sources, fault deduction, fault elimination, ISCAS'85 benchmark circuits, physical defect analysis, electron beam probing, light emission microscopy, computational complexity, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, combinational circuits, digital simulation, circuit analysis computing, computation time, scanning electron microscopy, scanning electron microscopy, diagnostic resolution |
30 | Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal |
An efficient automatic test generation system for path delay faults in combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 161-165, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
automatic test generation system, test pattern generation system, nonrobust tests, nine-value logic system, multiple backtrace procedure, path selection method, logic testing, delays, integrated circuit testing, fault detection, ATPG, combinational circuits, combinational circuits, automatic testing, fault location, multivalued logic, logic circuits, integrated logic circuits, path delay faults, robust tests |
30 | Tapan J. Chakraborty, Vishwani D. Agrawal |
Robust testing for stuck-at faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 42-46, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
logic circuit testing, d-robust tests, fault diagnosis, logic testing, delays, sequential circuits, sequential circuits, fault models, combinational circuits, combinational circuit, robust testing, single stuck-at faults, circuit models |
30 | Irith Pomeranz, Sudhakar M. Reddy |
Fault Collapsing for Transition Faults Using Extended Transition Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006, pp. 173-178, 2006, IEEE Computer Society, 0-7695-2566-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Abdul-Rahman Mawlood-Yunis |
Fault-tolerant semantic mappings among heterogeneous and distributed local ontologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ONISW ![In: Proceedings of the 2nd International Workshop on Ontologies and Information Systems for the Semantic Web, ONISW 2008, Napa Valley, California, USA, October 30, 2008, pp. 31-38, 2008, ACM, 978-1-60558-255-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
consensus reaching, heterogeneous information sources, semantic conflicts, temporal faults, interoperability, ontology mapping, emergent semantics |
29 | Vimal K. Reddy, Eric Rotenberg, Sailashri Parthasarathy |
Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006, pp. 83-94, 2006, ACM, 1-59593-451-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
redundant multithreading, simultaneous multithreading (SMT), slipstream processor, chip multiprocessor (CMP), branch prediction, transient faults, value prediction, time redundancy |
29 | M. Ümit Uyar, Yu Wang 0012, Samrat S. Batth, Adriana Wise, Mariusz A. Fecko |
Timing Fault Models for Systems with Multiple Timers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TestCom ![In: Testing of Communicating Systems, 17th IFIP TC6/WG 6.1 International Conference, TestCom 2005, Montreal, Canada, May 31 - June 2, 2005, Proceedings, pp. 192-208, 2005, Springer, 3-540-26054-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Timer Constraints, Fault Modeling, Timed Automata, Conformance Testing, Multiple Faults |
29 | Irith Pomeranz, Sudhakar M. Reddy |
A Measure of Quality for n-Detection Test Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(11), pp. 1497-1503, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
n-detection tests, test set ordering, unmodeled faults |
29 | Ronald D. Blanton, John P. Hayes |
On the properties of the input pattern fault model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 8(1), pp. 108-124, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
fault testing, testing digital circuits, ATPG, fault models, faults, defects |
29 | Roger T. Alexander, James M. Bieman, Sudipto Ghosh, Bixia Ji |
Mutation of Java Objects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSRE ![In: 13th International Symposium on Software Reliability Engineering (ISSRE 2002), 12-15 November 2002, Annapolis, MD, USA, pp. 341-351, 2002, IEEE Computer Society, 0-7695-1763-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Java, software testing, object-oriented programming, testability, Faults, mutation analysis, test adequacy |
29 | Lorenzo Alvisi, Evelyn Tumlin Pierce, Dahlia Malkhi, Michael K. Reiter, Rebecca N. Wright |
Dynamic Byzantine Quorum Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2000 International Conference on Dependable Systems and Networks (DSN 2000) (formerly FTCS-30 and DCCA-8), 25-28 June 2000, New York, NY, USA, pp. 283-292, 2000, IEEE Computer Society, 0-7695-0707-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fault tolerance, dynamic reconfiguration, quorum systems, Byzantine faults |
29 | Jun-Weir Lin, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen |
Fault diagnosis for linear analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 25-30, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
discrete signal flow graph, equivalent faults, fault diagnosis, fault diagnosis, signal flow graphs, analogue circuits, linear analog circuits |
29 | Dimiter R. Avresky |
Embedding and Reconfiguration of Spanning Trees in Faulty Hypercubes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 10(3), pp. 211-222, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
single and multiple faults, Fault tolerance, reconfiguration, spanning trees, faulty hypercubes |
29 | Avinash Munshi, Fred J. Meyer, Fabrizio Lombardi |
A New Method for Testing EEPLA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 146-154, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
EEPLA, testing, multiple faults, PLD |
29 | Chih Wei Hu, Chung-Len Lee 0001, Wen Ching Wu, Jwu E. Chen |
Fault diagnosis of odd-even sorting networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 288-, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
odd-even sorting networks, location tests, sorting element faults, binary search procedures, fault diagnosis, fault diagnosis, Banyan networks, switching system, ISDN |
29 | Sandeep S. Kulkarni, Anish Arora |
Once-and-for all management protocol (OFMP). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNP ![In: 1997 International Conference on Network Protocols (ICNP '97), 28-31 October 1997, Atlanta, GA, USA, pp. 87-94, 1997, IEEE Computer Society, 0-8186-8061-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
once-and-forall management protocol, network management protocol, management information bases, fault-tolerance masking, eventually-detectable faults, protocols |
29 | David S. Rosenblum |
A Practical Approach to Programming With Assertions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 21(1), pp. 19-31, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Anna, APP, formal specifications, formal methods, C, programming environments, assertions, consistency checking, software faults, runtime checking |
29 | Steven J. Zeil |
Perturbation Techniques for Detecting Domain Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 15(6), pp. 737-746, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
sensitivity measures, individual test points, domain errors, perturbing functions, potential faults, standard optimization techniques, novel test-data-generation method, arithmetic fault detection, perturbation techniques, software testing, error detection, error detection, program testing, test set, vector space, arithmetic expressions |
29 | Manoj Franklin, Kewal K. Saluja |
Hypergraph Coloring and Reconfigured RAM Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(6), pp. 725-736, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
hypergraph coloring, reconfigured RAM testing, RAM decoders, critical path lengths, memory chips, physical neighborhood pattern sensitive faults, reconfigured DRAMs, decoder faults, computational complexity, logic testing, redundancy, reconfigurable architectures, stuck-at faults, graph colouring, random-access storage, integrated memory circuits, test lengths, test algorithms, DRAM chips, silicon area |
29 | Younès Karkouri, El Mostapha Aboulhamid, Eduard Cerny, Alain Verreault |
Use of Fault Dropping for Multiple Fault Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(1), pp. 98-103, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
fault dropping, multiple fault analysis, frontier faults, fault-free circuit, logic testing, stuck at faults, logic circuits, logic circuits, combinatorial circuits, benchmark circuits, gate level, fault collapsing, multiple stuck at faults |
29 | Tein-Hsiang Lin, Kang G. Shin |
An Optimal Retry Policy Based on Fault Classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(9), pp. 1014-1025, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
optimal retry policy, fault characteristics, mission lifetime, system status, Bayesian decision problem, prior distributions, fault-related parameter updating, temporal fault type, fault parameter estimation, optimal retry period, mean task completion time minimization, fault tolerant computing, parameter estimation, fault detection, error detection, decision theory, system recovery, Bayes methods, minimisation, error recovery, transient faults, failure analysis, intermittent faults, permanent faults, fault classification |
29 | Che-Liang Yang, Gerald M. Masson |
A New Measure for Hybrid Fault Diagnosability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 36(3), pp. 378-383, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
test assignment, hard faults, hybrid faults, Fault diagnosis, PMC models, syndrome, soft faults |
29 | Kozo Kinoshita, Kewal K. Saluja |
Built-In Testing of Memory Using an On-Chip Compact Testing Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(10), pp. 862-870, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
weight-sensitive faults, random- access memory (RAM), Built-in self-testing (BIST), stuck-at faults, built-in testing (BIT), pattern-sensitive faults, hardware complexity |
29 | Barry R. Borgerson, Richard F. Freitas |
A Reliability Model for Gracefully Degrading and Standby-Sparing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 24(5), pp. 517-525, 1975. The full citation details ...](Pics/full.jpeg) |
1975 |
DBLP DOI BibTeX RDF |
gracefully degrading, resource exhaustion, solitary faults, space-domain multiple faults, standby sparing, time-domain multiple faults, Fault tolerance, reliability, PRIME |
28 | Albert Meixner, Daniel J. Sorin |
Detouring: Translating software to circumvent hard faults in simple cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, pp. 80-89, 2008, IEEE Computer Society, 978-1-4244-2397-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Man-Lap Li, Pradeep Ramachandran, Swarup Kumar Sahoo, Sarita V. Adve, Vikram S. Adve, Yuanyuan Zhou |
Trace-based microarchitecture-level diagnosis of permanent hardware faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, pp. 22-31, 2008, IEEE Computer Society, 978-1-4244-2397-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Bogdan Tomoyuki Nassu, Kiyonobu Uehara, Takashi Nanya |
Injecting Inconsistent Values Caused by Interaction Faults for Experimental Dependability Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Seventh European Dependable Computing Conference, EDCC-7 2008, Kaunas, Lithuania, 7-9 May 2008, pp. 3-12, 2008, IEEE Computer Society, 978-0-7695-3138-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Antonio Carzaniga, Alessandra Gorla, Mauro Pezzè |
Handling Software Faults with Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WADS ![In: Architecting Dependable Systems VI, pp. 148-171, 2008, Springer, 978-3-642-10247-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Michael Hutter, Jörn-Marc Schmidt, Thomas Plos |
RFID and Its Vulnerability to Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2008, 10th International Workshop, Washington, D.C., USA, August 10-13, 2008. Proceedings, pp. 363-379, 2008, Springer, 978-3-540-85052-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Antenna Tearing, Optical Injections, RFID, Fault Analysis, Implementation Attacks, Electromagnetic Analysis |
28 | Fred A. Bower, Daniel J. Sorin, Sule Ozev |
Online diagnosis of hard faults in microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 4(2), pp. 8, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Hard fault tolerance, fine-grained diagnosis, processor microarchitecture |
28 | Irith Pomeranz, Sudhakar M. Reddy |
Diagnostic Test Generation Based on Subsets of Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 12th European Test Symposium, ETS 2007, Freiburg, Germany, May 20, 2007, pp. 151-158, 2007, IEEE Computer Society, 978-0-7695-2827-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Yu-Chiun Lin, Shi-Yu Huang |
Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(2), pp. 151-159, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
multiple fault diagnosis, prime candidate, fault diagnosis, debugging, yield |
28 | David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil |
Run-Time Reconfiguration for Emulating Transient Faults in VLSI Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2006 International Conference on Dependable Systems and Networks (DSN 2006), 25-28 June 2006, Philadelphia, Pennsylvania, USA, Proceedings, pp. 291-300, 2006, IEEE Computer Society, 0-7695-2607-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Loganathan Lingappan, Niraj K. Jha |
Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 431-436, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Luca Schiano, Marco Ottavi, Fabrizio Lombardi, Salvatore Pontarelli, Adelio Salsano |
On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 580-585, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Fred A. Bower, Daniel J. Sorin, Sule Ozev |
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain, pp. 197-208, 2005, IEEE Computer Society, 0-7695-2440-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Zhigang Jiang, Sandeep K. Gupta 0001 |
Threshold testing: Covering bridging and other realistic faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 390-397, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Daniel Gil, Joaquin Gracia, Juan Carlos Baraza, Pedro J. Gil |
Impact of Faults in Combinational Logic of Commercial Microcontrollers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Dependable Computing - EDCC-5, 5th European Dependable Computing Conference, Budapest, Hungary, April 20-22, 2005, Proceedings, pp. 379-390, 2005, Springer, 3-540-25723-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Jin-Fu Li 0001, Chou-Kun Lin |
Modeling and Testing Comparison Faults for Ternary Content Addressable Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 60-65, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Dubravka Ilic, Elena Troubitsyna |
Formal Development of Software for Tolerating Transient Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 12-14 December, 2005, Changsha, Hunan, China, pp. 140-150, 2005, IEEE Computer Society, 0-7695-2492-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Yu-Chiun Lin, Shi-Yu Huang |
Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 38-43, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Henrique Madeira, João Durães, Marco Vieira |
Emulation of Software Faults: Representativeness and Usefulness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LADC ![In: Dependable Computing, First Latin-American Symposium, LADC 2003, Sao Paulo, Brazil, October 21-24, 2003, Proceedings, pp. 137-159, 2003, Springer, 3-540-20224-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Mohammad Gh. Mohammad, Kewal K. Saluja |
Electrical Model For Program Disturb Faults in Non-Volatile Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 217-222, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Ilia Polian, Irith Pomeranz, Bernd Becker 0001 |
Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 2-14, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
n-detection, BDDs, formal techniques, Fault dominance |
28 | Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri |
On the Propagation of Faults and Their Detection in a Hardware Implementation of the Advanced Encryption Standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 13th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2002), 17-19 July 2002, San Jose, CA, USA, pp. 303-, 2002, IEEE Computer Society, 0-7695-1712-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Cecilia Metra, Stefano Di Francescantonio, T. M. Mak |
Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 100-109, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Marco Vieira, Henrique Madeira |
Definition of Faultloads Based on Operator Faults for DMBS Recovery Benchmarking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 16-18 December 2002, Tsukuba-City, Ibarski, Japan, pp. 265-274, 2002, IEEE Computer Society, 0-7695-1852-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand |
On the detectability of CMOS floating gate transistor faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1), pp. 116-128, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Diamantino Costa, Tiago Rilho, Marco Vieira, Henrique Madeira |
ESFFI - A Novel Technique for the Emulation of Coftware Faults in COTS Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 8th IEEE International Conference on Engineering of Computer-Based Systems (ECBS 2001), 17-20 April 2001, Washington, DC, USA, pp. 197-204, 2001, IEEE Computer Society, 0-7695-1086-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Said Hamdioui, Ad J. van de Goor, David Eastwick, Mike Rodgers |
Detecting Unique Faults in Multi-port SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 37-42, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Chuan-Ching Sue, Sy-Yen Kuo |
Restoration from Multiple Faults in WDM Networks without Wavelength Conversion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICN (1) ![In: Networking - ICN 2001, First International Conference, Colmar, France, July 9-13, 2001 Proceedings, Part 1, pp. 317-325, 2001, Springer, 3-540-42302-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Joan Carletta, Christos A. Papachristou, Mehrdad Nourani |
Detecting Undetectable Controller Faults Using Power Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 723-728, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Abderrahim Doumar, Hideo Ito |
Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings, pp. 134-142, 2000, IEEE Computer Society, 0-7695-0719-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Jue Wu, Elizabeth M. Rudnick |
A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 498-505, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Lan Zhao, D. M. H. Walker, Fabrizio Lombardi |
IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 47(10), pp. 1136-1152, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
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