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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6138 occurrences of 3479 keywords
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Results
Found 8586 publication records. Showing 8586 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | Neil Harrison |
A Simple via Duplication Tool for Yield Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 39-47, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Youcef Bourai, C.-J. Richard Shi |
Layout Compaction for Yield Optimization via Critical Area Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 122-125, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Massimo Conti, Paolo Crippa, Simone Orcioni, Claudio Turchetti |
Parametric yield formulation of MOS IC's affected by mismatch effect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(5), pp. 582-596, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Markus Rudack, Dirk Niggemeyer |
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 31-39, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Nohpill Park, Fabrizio Lombardi |
Stratified Testing of Multichip Module Systems under Uneven Known-Good-Yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 192-200, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Kannan Krishna, Stephen W. Director |
The linearized performance penalty (LPP) method for optimization of parametric yield and its reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12), pp. 1557-1568, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Jagannathan Narasimham, Kazuo Nakajima, Chong S. Rim, Anton T. Dahbura |
Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(8), pp. 976-986, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Jacek Wojciechowski, Jirí Vlach |
Ellipsoidal method for design centering and yield estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(10), pp. 1570-1579, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Michael Demjanenko, Shambhu J. Upadhyaya |
Yield enhancement of field programmable logic arrays by inherent component redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(8), pp. 876-884, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
19 | Chin-Long Wey |
On yield consideration for the design of redundant programmable logic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(4), pp. 528-535, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
17 | Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan |
SRAM-based NBTI/PBTI sensor system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 849-852, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
PBTI, sensor system design, sensor, redundancy, process variation, aging, yield, SRAM, NBTI |
17 | Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke |
ZerehCache: armoring cache architectures in high defect density technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 100-110, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fault-tolerant cache, process variation, manufacturing yield |
17 | Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Hanpei Koike, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa |
Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(1), pp. 3:1-3:31, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, configuration, within-die variation, timing yield |
17 | Sverre Wichlund, Frank Berntsen, Einar J. Aas |
Scan Test Response Compaction Combined with Diagnosis Capabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 235-246, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Scan compression, Diagnosis, ATPG, Yield, Design for test, ATE |
17 | Melvin A. Breuer, Haiyang (Henry) Zhu |
An Illustrated Methodology for Analysis of Error Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(2), pp. 168-177, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
telephone answering machine, defective flash memory, yield, mean opinion score, error tolerance |
17 | Ganesh Srinivasan, Friedrich Taenzler, Abhijit Chatterjee |
Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(2), pp. 150-159, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
wafer probe test, test yield, loopback test, DFT, RF test, low-cost test |
17 | Kwangok Jeong, Andrew B. Kahng, Kambiz Samadi |
Quantified Impacts of Guardband Reduction on Design Process Outcomes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 790-797, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Guardband, chip size, yield, runtime, wirelength, design iterations |
17 | Xiaochao Zhang, Xiaoan Hu, Wenhua Mao |
Development of Intelligent Equipments for Precision Agriculture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCTA ![In: Computer And Computing Technologies In Agriculture, Volume II, First IFIP TC 12 International Conference on Computer and Computing Technologies in Agriculture (CCTA 2007), Wuyishan, China, August 18-20, 2007, pp. 951-958, 2007, Springer, 978-0-387-77252-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
variable ferti-seeder, yield distribution, variable controlled, intelligent spraying, precision agriculture |
17 | Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang |
A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 8-13, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
booster circuit, low power, yield, SRAM |
17 | Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl |
Robust wiring networks for DfY considering timing constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 43-48, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
redundant wiring, timing constraint aware, open defects, design for yield |
17 | Scott Davidson 0001 |
Searching for clues: Diagnosing IC failures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(1), pp. 67-68, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
IC failures, IC manufacturing, data mining, defects, yield enhancement, failure diagnosis |
17 | Xiao Liu 0010, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran |
Efficient techniques for transition testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(2), pp. 258-278, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
test chain, test data volume reduction, transition faults, Test application time reduction, yield loss |
17 | Scott Davidson 0001 |
Guest Editor's Introduction: ITC Examines How Test Helps the Fittest Survive. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(6), pp. 565, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
X-tolerant, IC outlier, ATPG, BIST, yield, IDDQ, International Test Conference, test metrics |
17 | Xiaolang Yan, Ye Chen, Zheng Shi 0002, Yue Ma |
A new method for model based frugal OPC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 83-86, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
mask cost, yield, OPC, dissection |
17 | Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong |
Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 78-85, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
yield, buffering, design for manufacturing, wire sizing, chemical mechanical polishing (CMP) |
17 | Srivathsan Krishnamohan, Nihar R. Mahapatra |
An analysis of the robustness of CMOS delay elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 412-415, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
delay element, process variation, yield, Monte Carlo simulation |
17 | Matthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown |
Optimization objectives and models of variation for statistical gate sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 313-316, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
parametric yield optimization, robust design |
17 | Luigi Capodieci, Puneet Gupta 0001, Andrew B. Kahng, Dennis Sylvester, Jie Yang 0010 |
Toward a methodology for manufacturability-driven design rule exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 311-316, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
VLSI manufacturability, process variation, yield, OPC, lithography, RET |
17 | Minsu Choi, Noh-Jin Park, K. M. George, Byoungjae Jin, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi |
Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NCA ![In: 2nd IEEE International Symposium on Network Computing and Applications (NCA 2003), 16-18 April 2003, Cambridge, MA, USA, pp. 341-350, 2003, IEEE Computer Society, 0-7695-1938-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Built-in-self-repair (BISR), Field Reconfiguration, HW/SW Co-reliability, Reliability Assurance, Reliability, High performance computing, Yield, Massively parallel computing, Fault-tolerant memory, Modular Redundancy |
17 | Louis Scheffer |
Explicit computation of performance as a function of process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 1-8, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
static timing, process variation, yield, statistical timing |
17 | Hans T. Heineken, Wojciech Maly |
Performance - Manufacturability Tradeoffs in IC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 563-567, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
wafer productivity, design rule shrink, performance, manufacturability, yield, critical area, clock frequency |
17 | Mick Tegethoff, Tom Chen 0001 |
Simulation Techniques for the Manufacturing Test of MCMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 10(1-2), pp. 137-149, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
simulation, test, DFT, yield, DFM, SMT, MCM, board |
17 | Yves Gagnon, Yvon Savaria, Michel Meunier, Claude Thibeault |
Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 157-165, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
defect-tolerant circuit, contamination, wafer test, silicon chip, reconfiguration, redundancy, integrated circuit testing, manufacturing, yield, cost model, integrated circuit, figure of merit, fault tolerant circuit |
17 | Wojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag |
Design for manufacturability in submicron domain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 690-697, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
IC technologies, die size minimization, integrated circuit technology, submicron domain, yield, cost model, design for manufacturability, trade-offs, design rules |
17 | Kanad Chakraborty, Pinaki Mazumder |
An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 685-688, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
bus-layout, bussed driver shorts, early diagnosis, field survivability, interconnect shorts, production yield, printed circuit boards, printed circuit testing |
16 | Saraju P. Mohanty |
Unified Challenges in Nano-CMOS High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 531, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Kian Haghdad, Mohab Anis |
Design-Specific Optimization Considering Supply and Threshold Voltage Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10), pp. 1891-1901, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Feng Wang 0004, Guangyu Sun 0003, Yuan Xie 0001 |
A Variation Aware High Level Synthesis Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1063-1068, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Sudip Roy 0001, Ajit Pal |
Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 282-289, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Swaroop Ghosh, Kaushik Roy 0001 |
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 635-640, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Norma Rodriguez, Li Song, Shishir Shroff, Kuang Han Chen, Taber Smith, Wilbur Luo |
Hotspot Prevention Using CMP Model in Design Implementation Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 365-368, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
CMP modeling, CMP aware design, hotspot |
16 | Sung Ho Ha, Jong Sik Jin, Jeong Won Yang |
Predictive Performance of Clustered Feature-Weighting Case-Based Reasoning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ADMA ![In: Advanced Data Mining and Applications, 4th International Conference, ADMA 2008, Chengdu, China, October 8-10, 2008. Proceedings, pp. 469-476, 2008, Springer, 978-3-540-88191-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo A. L. Reis |
Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 94-98, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Luis Pierluissi, Claudio M. Rocco Sanseverino |
Optimal Design Centring Through a Hybrid Approach Based on Evolutionary Algorithms and Monte Carlo Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICANNGA (1) ![In: Adaptive and Natural Computing Algorithms, 8th International Conference, ICANNGA 2007, Warsaw, Poland, April 11-14, 2007, Proceedings, Part I, pp. 31-38, 2007, Springer, 978-3-540-71589-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Feng Wang 0004, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie 0001, Narayanan Vijaykrishnan |
Variation-aware task allocation and scheduling for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 598-603, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Jongyoon Jung, Taewhan Kim |
Timing variation-aware high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 424-428, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie 0001, Narayanan Vijaykrishnan |
FPGA routing architecture analysis under variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 152-157, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Shubhankar Basu, Priyanka Thakore, Ranga Vemuri |
Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 814-820, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Shyue-Kung Lu, Chih-Hsien Hsu |
Fault tolerance techniques for high capacity RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 55(2), pp. 293-306, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy 0001 |
Speed binning aware design methodology to improve profit under parameter variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 712-717, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Pongstorn Maidee, Kia Bazargan |
Defect-Tolerant FPGA Architecture Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-6, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Tanu Malik, Randal C. Burns, Amitabh Chaudhary |
Bypass Caching: Making Scientific Databases Good Network Citizens. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDE ![In: Proceedings of the 21st International Conference on Data Engineering, ICDE 2005, 5-8 April 2005, Tokyo, Japan, pp. 94-105, 2005, IEEE Computer Society, 0-7695-2285-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Yervant Zorian, Juan Antonio Carballo |
T1: Design for Manufacturability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Thomas W. Williams |
Design for Testability: The Path to Deep Submicron. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Youngshin Han, Chilgee Lee |
Automatic Classification Using Decision Tree and Support Vector Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (2) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 9th International Conference, KES 2005, Melbourne, Australia, September 14-16, 2005, Proceedings, Part II, pp. 1325-1330, 2005, Springer, 3-540-28895-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone |
Design and Analysis of Self-Repairable MEMS Accelerometer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 21-32, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Vishak Venkatraman, Wayne P. Burleson |
Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 522-527, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Alessandra Nardi, Alberto L. Sangiovanni-Vincentelli |
Logic Synthesis for Manufacturability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 21(3), pp. 192-199, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang |
Fail Pattern Identification for Memory Built-In Self-Repair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 366-371, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger |
Exploiting Microarchitectural Redundancy For Defect Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 481-488, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Meng Lu, Yvon Savaria, Bing Qiu 0003, Jacques Taillefer |
IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 18-25, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang |
Fault Pattern Oriented Defect Diagnosis for Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 29-38, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
failure analysis (FA), fault pattern, memory diagnostics, memory testing, bitmap, semiconductor memory |
16 | Emmanuel Rondey, Yann Tellier, Simone Borri |
A Silicon-Based Yiel Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy Scenarios. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, pp. 251-255, 2002, IEEE Computer Society, 0-7695-1641-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Madhuban Kishor, José Pineda de Gyvez |
Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings, pp. 349-357, 2000, IEEE Computer Society, 0-7695-0719-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Peter Feldmann, Stephen W. Director |
Integrated circuit quality optimization using surface integrals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(12), pp. 1868-1879, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
15 | Xiaojun Ma, Masoud Hashempour, Lei Wang 0003, Fabrizio Lombardi |
Manufacturing yield of QCA circuits by synthesized DNA self-assembled templates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 275-280, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
design, manufacturing, nanotechnology, defect tolerance |
15 | Caroline Concatto, Debora Matos, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Érika F. Cota, Márcio Eduardo Kreutz |
Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
reconfigurable router, fault tolerance, reliability, network-on-chip, NoC |
15 | Georg Ruß |
Data Mining of Agricultural Yield Data: A Comparison of Regression Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDM ![In: Advances in Data Mining. Applications and Theoretical Aspects, 9th Industrial Conference, ICDM 2009, Leipzig, Germany, July 20-22, 2009. Proceedings, pp. 24-37, 2009, Springer, 978-3-642-03066-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Data Mining, Modeling, Regression, Precision Agriculture |
15 | Ali Jahanian 0001, Morteza Saheb Zamani |
Improved performance and yield with chip master planning design methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 185-190, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
chip planning, highway on chip, interconnect planning |
15 | Bao Liu 0001 |
Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 430-435, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Miguel Miranda, Bart Dierickx, Paul Zuber, Petr Dobrovolný, F. Kutscherauer, Philippe Roussel, Pavel Poliakov |
Variability aware modeling of SoCs: From device variations to manufactured system yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 547-553, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Ruiming Chen, Hai Zhou 0001 |
Fast Estimation of Timing Yield Bounds for Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(3), pp. 241-248, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu |
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11), pp. 2097-2101, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Yan Li 0030, Helmut Schneider, Florian Schnabel 0002, Roland Thewes, Doris Schmitt-Landsiedel |
Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 126-135, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Georg Ruß, Rudolf Kruse, Martin Schneider 0001, Peter Wagner 0001 |
Estimation of Neural Network Parameters for Wheat Yield Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFIP AI ![In: Artificial Intelligence in Theory and Practice II, IFIP 20th World Computer Congress, TC 12: IFIP AI 2008 Stream, September 7-10, 2008, Milano, Italy, pp. 109-118, 2008, Springer, 978-0-387-09694-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Woonghee Tim Huh, Mahesh Nagarajan |
Linear inflation rules for the random yield production control problem with uncertain demand: Analysis and computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSC ![In: Proceedings of the 2008 Winter Simulation Conference, Global Gateway to Discovery, WSC 2008, InterContinental Hotel, Miami, Florida, USA, December 7-10, 2008, pp. 2237-2243, 2008, WSC, 978-1-4244-2708-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Georg Ruß, Rudolf Kruse, Martin Schneider 0001, Peter Wagner 0001 |
Data Mining with Neural Networks for Wheat Yield Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDM ![In: Advances in Data Mining. Medical Applications, E-Commerce, Marketing, and Theoretical Aspects, 8th Industrial Conference, ICDM 2008, Leipzig, Germany, July 16-18, 2008, Proceedings, pp. 47-56, 2008, Springer, 978-3-540-70717-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Data Mining, Neural Networks, Prediction, Precision Agriculture |
15 | Anne Gattiker |
Using test data to improve IC quality and yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 771-777, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Farid N. Najm, Noel Menezes, Imad A. Ferzli |
A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3), pp. 574-591, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Andreas Hofinger, Jan Valdman |
Numerical solution of the two-yield elastoplastic minimization problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computing ![In: Computing 81(1), pp. 35-52, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
AMS Subject Classifications 74C05, 49M15, 49M27 |
15 | Héctor F. Satizábal, Daniel R. Jiménez R., Andrés Pérez-Uribe |
Consequences of Data Uncertainty and Data Precision in Artificial Neural Network Sugar Cane Yield Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWANN ![In: Computational and Ambient Intelligence, 9th International Work-Conference on Artificial Neural Networks, IWANN 2007, San Sebastián, Spain, June 20-22, 2007, Proceedings, pp. 1147-1154, 2007, Springer, 978-3-540-73006-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Shubhankar Basu, Ranga Vemuri |
Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 291-298, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Narender Hanchate, Nagarajan Ranganathan |
Statistical Gate Sizing for Yield Enhancement at Post Layout Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 245-252, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Huaxing Tang, Manish Sharma, Janusz Rajski, Martin Keim, Brady Benware |
Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 12th European Test Symposium, ETS 2007, Freiburg, Germany, May 20, 2007, pp. 145-150, 2007, IEEE Computer Society, 978-0-7695-2827-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Rene Segers |
If It's All about Yield, Why Talk about Testing? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 12th European Test Symposium, ETS 2007, Freiburg, Germany, May 20, 2007, pp. 3, 2007, IEEE Computer Society, 978-0-7695-2827-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera |
A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 122-123, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
LUT-based FPGA device, simple model circuit, ring oscillators, within-die variations, placement optimization, 90 nm |
15 | Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura |
A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 878-883, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Michael Crocker, Michael T. Niemier, Xiaobo Sharon Hu |
Fault Models and Yield Analysis for QCA-based PLAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 435-440, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Sanjiv Taneja |
Accelerating Yield Ramp through Real-Time Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 11, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Arthur Nieuwoudt, Tamer Ragheb, Hamid Nejati, Yehia Massoud |
Increasing Manufacturing Yield for Wideband RF CMOS LNAs in the Presence of Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 801-806, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Ayhan A. Mutlu, Kelvin J. Le, Mustafa Celik, Dar-sun Tsien, Garry Shyu, Long-Ching Yeh |
An Exploratory Study on Statistical Timing Analysis and Parametric Yield Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 677-684, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah |
Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2376-2392, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Vineet Agarwal, Janet Meiling Wang |
Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 718-723, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera |
Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 110-111, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Lingxia Huang, Peihua Jin, Yong He 0001, Chengfu Lou, Min Huang, Mingang Chen |
Prediction of Silkworm Cocoon Yield in China Based on Grey-Markov Forecasting Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICAI ![In: MICAI 2006: Advances in Artificial Intelligence, 5th Mexican International Conference on Artificial Intelligence, Apizaco, Mexico, November 13-17, 2006, Proceedings, pp. 505-512, 2006, Springer, 3-540-49026-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Murari Mani, Ashish Kumar Singh, Michael Orshansky |
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 19-26, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Georgi I. Radulov, Patrick J. Quinn, Pieter C. W. van Beek, Johannes A. Hegt, Arthur H. M. van Roermund |
A binary-to-thermometer decoder with built-in redundancy for improved DAC yield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee |
Timing-constrained yield-driven wire sizing for critical area minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Kristian Granhaug, Snorre Aunet |
Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 20-28, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Xianlong Hong, Yici Cai, Hailong Yao, Duo Li |
DFM-aware Routing for Yield Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1091-1094, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
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