Search results for "yield"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Neil Harrison	A Simple via Duplication Tool for Yield Enhancement.	DFT	2001	DBLP DOI BibTeX RDF
19	Youcef Bourai, C.-J. Richard Shi	Layout Compaction for Yield Optimization via Critical Area Minimization.	DATE	2000	DBLP DOI BibTeX RDF
19	Massimo Conti, Paolo Crippa, Simone Orcioni, Claudio Turchetti	Parametric yield formulation of MOS IC's affected by mismatch effect.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
19	Markus Rudack, Dirk Niggemeyer	Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM.	DFT	1999	DBLP DOI BibTeX RDF
19	Nohpill Park, Fabrizio Lombardi	Stratified Testing of Multichip Module Systems under Uneven Known-Good-Yield.	DFT	1999	DBLP DOI BibTeX RDF
19	Kannan Krishna, Stephen W. Director	The linearized performance penalty (LPP) method for optimization of parametric yield and its reliability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
19	Jagannathan Narasimham, Kazuo Nakajima, Chong S. Rim, Anton T. Dahbura	Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
19	Jacek Wojciechowski, Jirí Vlach	Ellipsoidal method for design centering and yield estimation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
19	Michael Demjanenko, Shambhu J. Upadhyaya	Yield enhancement of field programmable logic arrays by inherent component redundancy.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
19	Chin-Long Wey	On yield consideration for the design of redundant programmable logic arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
17	Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan	SRAM-based NBTI/PBTI sensor system design.	DAC	2010	DBLP DOI BibTeX RDF	PBTI, sensor system design, sensor, redundancy, process variation, aging, yield, SRAM, NBTI
17	Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke	ZerehCache: armoring cache architectures in high defect density technologies.	MICRO	2009	DBLP DOI BibTeX RDF	fault-tolerant cache, process variation, manufacturing yield
17	Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Hanpei Koike, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa	Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	FPGA, configuration, within-die variation, timing yield
17	Sverre Wichlund, Frank Berntsen, Einar J. Aas	Scan Test Response Compaction Combined with Diagnosis Capabilities.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Scan compression, Diagnosis, ATPG, Yield, Design for test, ATE
17	Melvin A. Breuer, Haiyang (Henry) Zhu	An Illustrated Methodology for Analysis of Error Tolerance.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	telephone answering machine, defective flash memory, yield, mean opinion score, error tolerance
17	Ganesh Srinivasan, Friedrich Taenzler, Abhijit Chatterjee	Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	wafer probe test, test yield, loopback test, DFT, RF test, low-cost test
17	Kwangok Jeong, Andrew B. Kahng, Kambiz Samadi	Quantified Impacts of Guardband Reduction on Design Process Outcomes.	ISQED	2008	DBLP DOI BibTeX RDF	Guardband, chip size, yield, runtime, wirelength, design iterations
17	Xiaochao Zhang, Xiaoan Hu, Wenhua Mao	Development of Intelligent Equipments for Precision Agriculture.	CCTA	2007	DBLP DOI BibTeX RDF	variable ferti-seeder, yield distribution, variable controlled, intelligent spraying, precision agriculture
17	Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang	A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	booster circuit, low power, yield, SRAM
17	Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl	Robust wiring networks for DfY considering timing constraints.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	redundant wiring, timing constraint aware, open defects, design for yield
17	Scott Davidson 0001	Searching for clues: Diagnosing IC failures.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	IC failures, IC manufacturing, data mining, defects, yield enhancement, failure diagnosis
17	Xiao Liu 0010, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran	Efficient techniques for transition testing.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	test chain, test data volume reduction, transition faults, Test application time reduction, yield loss
17	Scott Davidson 0001	Guest Editor's Introduction: ITC Examines How Test Helps the Fittest Survive.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	X-tolerant, IC outlier, ATPG, BIST, yield, IDDQ, International Test Conference, test metrics
17	Xiaolang Yan, Ye Chen, Zheng Shi 0002, Yue Ma	A new method for model based frugal OPC.	ASP-DAC	2005	DBLP DOI BibTeX RDF	mask cost, yield, OPC, dissection
17	Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong	Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation.	ISPD	2005	DBLP DOI BibTeX RDF	yield, buffering, design for manufacturing, wire sizing, chemical mechanical polishing (CMP)
17	Srivathsan Krishnamohan, Nihar R. Mahapatra	An analysis of the robustness of CMOS delay elements.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	delay element, process variation, yield, Monte Carlo simulation
17	Matthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown	Optimization objectives and models of variation for statistical gate sizing.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	parametric yield optimization, robust design
17	Luigi Capodieci, Puneet Gupta 0001, Andrew B. Kahng, Dennis Sylvester, Jie Yang 0010	Toward a methodology for manufacturability-driven design rule exploration.	DAC	2004	DBLP DOI BibTeX RDF	VLSI manufacturability, process variation, yield, OPC, lithography, RET
17	Minsu Choi, Noh-Jin Park, K. M. George, Byoungjae Jin, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi	Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems.	NCA	2003	DBLP DOI BibTeX RDF	Built-in-self-repair (BISR), Field Reconfiguration, HW/SW Co-reliability, Reliability Assurance, Reliability, High performance computing, Yield, Massively parallel computing, Fault-tolerant memory, Modular Redundancy
17	Louis Scheffer	Explicit computation of performance as a function of process variation.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	static timing, process variation, yield, statistical timing
17	Hans T. Heineken, Wojciech Maly	Performance - Manufacturability Tradeoffs in IC Design.	DATE	1998	DBLP DOI BibTeX RDF	wafer productivity, design rule shrink, performance, manufacturability, yield, critical area, clock frequency
17	Mick Tegethoff, Tom Chen 0001	Simulation Techniques for the Manufacturing Test of MCMs.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	simulation, test, DFT, yield, DFM, SMT, MCM, board
17	Yves Gagnon, Yvon Savaria, Michel Meunier, Claude Thibeault	Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model.	DFT	1997	DBLP DOI BibTeX RDF	defect-tolerant circuit, contamination, wafer test, silicon chip, reconfiguration, redundancy, integrated circuit testing, manufacturing, yield, cost model, integrated circuit, figure of merit, fault tolerant circuit
17	Wojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag	Design for manufacturability in submicron domain.	ICCAD	1996	DBLP DOI BibTeX RDF	IC technologies, die size minimization, integrated circuit technology, submicron domain, yield, cost model, design for manufacturability, trade-offs, design rules
17	Kanad Chakraborty, Pinaki Mazumder	An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards.	ICCAD	1996	DBLP DOI BibTeX RDF	bus-layout, bussed driver shorts, early diagnosis, field survivability, interconnect shorts, production yield, printed circuit boards, printed circuit testing
16	Saraju P. Mohanty	Unified Challenges in Nano-CMOS High-Level Synthesis.	VLSI Design	2009	DBLP DOI BibTeX RDF
16	Kian Haghdad, Mohab Anis	Design-Specific Optimization Considering Supply and Threshold Voltage Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
16	Feng Wang 0004, Guangyu Sun 0003, Yuan Xie 0001	A Variation Aware High Level Synthesis Framework.	DATE	2008	DBLP DOI BibTeX RDF
16	Sudip Roy 0001, Ajit Pal	Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations?	DSD	2008	DBLP DOI BibTeX RDF
16	Swaroop Ghosh, Kaushik Roy 0001	Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching.	ASP-DAC	2008	DBLP DOI BibTeX RDF
16	Norma Rodriguez, Li Song, Shishir Shroff, Kuang Han Chen, Taber Smith, Wilbur Luo	Hotspot Prevention Using CMP Model in Design Implementation Flow.	ISQED	2008	DBLP DOI BibTeX RDF	CMP modeling, CMP aware design, hotspot
16	Sung Ho Ha, Jong Sik Jin, Jeong Won Yang	Predictive Performance of Clustered Feature-Weighting Case-Based Reasoning.	ADMA	2008	DBLP DOI BibTeX RDF
16	Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo A. L. Reis	Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
16	Luis Pierluissi, Claudio M. Rocco Sanseverino	Optimal Design Centring Through a Hybrid Approach Based on Evolutionary Algorithms and Monte Carlo Simulation.	ICANNGA (1)	2007	DBLP DOI BibTeX RDF
16	Feng Wang 0004, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie 0001, Narayanan Vijaykrishnan	Variation-aware task allocation and scheduling for MPSoC.	ICCAD	2007	DBLP DOI BibTeX RDF
16	Jongyoon Jung, Taewhan Kim	Timing variation-aware high-level synthesis.	ICCAD	2007	DBLP DOI BibTeX RDF
16	Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie 0001, Narayanan Vijaykrishnan	FPGA routing architecture analysis under variations.	ICCD	2007	DBLP DOI BibTeX RDF
16	Shubhankar Basu, Priyanka Thakore, Ranga Vemuri	Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques.	ISQED	2007	DBLP DOI BibTeX RDF
16	Shyue-Kung Lu, Chih-Hsien Hsu	Fault tolerance techniques for high capacity RAM.	IEEE Trans. Reliab.	2006	DBLP DOI BibTeX RDF
16	Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy 0001	Speed binning aware design methodology to improve profit under parameter variations.	ASP-DAC	2006	DBLP DOI BibTeX RDF
16	Pongstorn Maidee, Kia Bazargan	Defect-Tolerant FPGA Architecture Exploration.	FPL	2006	DBLP DOI BibTeX RDF
16	Tanu Malik, Randal C. Burns, Amitabh Chaudhary	Bypass Caching: Making Scientific Databases Good Network Citizens.	ICDE	2005	DBLP DOI BibTeX RDF
16	Yervant Zorian, Juan Antonio Carballo	T1: Design for Manufacturability.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
16	Thomas W. Williams	Design for Testability: The Path to Deep Submicron.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
16	Youngshin Han, Chilgee Lee	Automatic Classification Using Decision Tree and Support Vector Machine.	KES (2)	2005	DBLP DOI BibTeX RDF
16	Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone	Design and Analysis of Self-Repairable MEMS Accelerometer.	DFT	2005	DBLP DOI BibTeX RDF
16	Vishak Venkatraman, Wayne P. Burleson	Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations.	ISQED	2005	DBLP DOI BibTeX RDF
16	Alessandra Nardi, Alberto L. Sangiovanni-Vincentelli	Logic Synthesis for Manufacturability.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
16	Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang	Fail Pattern Identification for Memory Built-In Self-Repair.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
16	Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger	Exploiting Microarchitectural Redundancy For Defect Tolerance.	ICCD	2003	DBLP DOI BibTeX RDF
16	Meng Lu, Yvon Savaria, Bing Qiu 0003, Jacques Taillefer	IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration.	DFT	2003	DBLP DOI BibTeX RDF
16	Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang	Fault Pattern Oriented Defect Diagnosis for Memories.	ITC	2003	DBLP DOI BibTeX RDF	failure analysis (FA), fault pattern, memory diagnostics, memory testing, bitmap, semiconductor memory
16	Emmanuel Rondey, Yann Tellier, Simone Borri	A Silicon-Based Yiel Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy Scenarios.	IOLTW	2002	DBLP DOI BibTeX RDF
16	Madhuban Kishor, José Pineda de Gyvez	Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families.	DFT	2000	DBLP DOI BibTeX RDF
16	Peter Feldmann, Stephen W. Director	Integrated circuit quality optimization using surface integrals.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
15	Xiaojun Ma, Masoud Hashempour, Lei Wang 0003, Fabrizio Lombardi	Manufacturing yield of QCA circuits by synthesized DNA self-assembled templates.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	design, manufacturing, nanotechnology, defect tolerance
15	Caroline Concatto, Debora Matos, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Érika F. Cota, Márcio Eduardo Kreutz	Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router.	SBCCI	2009	DBLP DOI BibTeX RDF	reconfigurable router, fault tolerance, reliability, network-on-chip, NoC
15	Georg Ruß	Data Mining of Agricultural Yield Data: A Comparison of Regression Models.	ICDM	2009	DBLP DOI BibTeX RDF	Data Mining, Modeling, Regression, Precision Agriculture
15	Ali Jahanian 0001, Morteza Saheb Zamani	Improved performance and yield with chip master planning design methodology.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	chip planning, highway on chip, interconnect planning
15	Bao Liu 0001	Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution.	ISQED	2009	DBLP DOI BibTeX RDF
15	Miguel Miranda, Bart Dierickx, Paul Zuber, Petr Dobrovolný, F. Kutscherauer, Philippe Roussel, Pavel Poliakov	Variability aware modeling of SoCs: From device variations to manufactured system yield.	ISQED	2009	DBLP DOI BibTeX RDF
15	Ruiming Chen, Hai Zhou 0001	Fast Estimation of Timing Yield Bounds for Process Variations.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
15	Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu	Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
15	Yan Li 0030, Helmut Schneider, Florian Schnabel 0002, Roland Thewes, Doris Schmitt-Landsiedel	Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization.	PATMOS	2008	DBLP DOI BibTeX RDF
15	Georg Ruß, Rudolf Kruse, Martin Schneider 0001, Peter Wagner 0001	Estimation of Neural Network Parameters for Wheat Yield Prediction.	IFIP AI	2008	DBLP DOI BibTeX RDF
15	Woonghee Tim Huh, Mahesh Nagarajan	Linear inflation rules for the random yield production control problem with uncertain demand: Analysis and computations.	WSC	2008	DBLP DOI BibTeX RDF
15	Georg Ruß, Rudolf Kruse, Martin Schneider 0001, Peter Wagner 0001	Data Mining with Neural Networks for Wheat Yield Prediction.	ICDM	2008	DBLP DOI BibTeX RDF	Data Mining, Neural Networks, Prediction, Precision Agriculture
15	Anne Gattiker	Using test data to improve IC quality and yield.	ICCAD	2008	DBLP DOI BibTeX RDF
15	Farid N. Najm, Noel Menezes, Imad A. Ferzli	A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
15	Andreas Hofinger, Jan Valdman	Numerical solution of the two-yield elastoplastic minimization problem.	Computing	2007	DBLP DOI BibTeX RDF	AMS Subject Classifications 74C05, 49M15, 49M27
15	Héctor F. Satizábal, Daniel R. Jiménez R., Andrés Pérez-Uribe	Consequences of Data Uncertainty and Data Precision in Artificial Neural Network Sugar Cane Yield Prediction.	IWANN	2007	DBLP DOI BibTeX RDF
15	Shubhankar Basu, Ranga Vemuri	Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs.	ISVLSI	2007	DBLP DOI BibTeX RDF
15	Narender Hanchate, Nagarajan Ranganathan	Statistical Gate Sizing for Yield Enhancement at Post Layout Level.	ISVLSI	2007	DBLP DOI BibTeX RDF
15	Huaxing Tang, Manish Sharma, Janusz Rajski, Martin Keim, Brady Benware	Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement.	ETS	2007	DBLP DOI BibTeX RDF
15	Rene Segers	If It's All about Yield, Why Talk about Testing?	ETS	2007	DBLP DOI BibTeX RDF
15	Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera	A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations.	ASP-DAC	2007	DBLP DOI BibTeX RDF	LUT-based FPGA device, simple model circuit, ring oscillators, within-die variations, placement optimization, 90 nm
15	Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura	A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation.	ASP-DAC	2007	DBLP DOI BibTeX RDF
15	Michael Crocker, Michael T. Niemier, Xiaobo Sharon Hu	Fault Models and Yield Analysis for QCA-based PLAs.	FPL	2007	DBLP DOI BibTeX RDF
15	Sanjiv Taneja	Accelerating Yield Ramp through Real-Time Testing.	IOLTS	2007	DBLP DOI BibTeX RDF
15	Arthur Nieuwoudt, Tamer Ragheb, Hamid Nejati, Yehia Massoud	Increasing Manufacturing Yield for Wideband RF CMOS LNAs in the Presence of Process Variations.	ISQED	2007	DBLP DOI BibTeX RDF
15	Ayhan A. Mutlu, Kelvin J. Le, Mustafa Celik, Dar-sun Tsien, Garry Shyu, Long-Ching Yeh	An Exploratory Study on Statistical Timing Analysis and Parametric Yield Optimization.	ISQED	2007	DBLP DOI BibTeX RDF
15	Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah	Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
15	Vineet Agarwal, Janet Meiling Wang	Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA).	ASP-DAC	2006	DBLP DOI BibTeX RDF
15	Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera	Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices.	ASP-DAC	2006	DBLP DOI BibTeX RDF
15	Lingxia Huang, Peihua Jin, Yong He 0001, Chengfu Lou, Min Huang, Mingang Chen	Prediction of Silkworm Cocoon Yield in China Based on Grey-Markov Forecasting Model.	MICAI	2006	DBLP DOI BibTeX RDF
15	Murari Mani, Ashish Kumar Singh, Michael Orshansky	Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization.	ICCAD	2006	DBLP DOI BibTeX RDF
15	Georgi I. Radulov, Patrick J. Quinn, Pieter C. W. van Beek, Johannes A. Hegt, Arthur H. M. van Roermund	A binary-to-thermometer decoder with built-in redundancy for improved DAC yield.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee	Timing-constrained yield-driven wire sizing for critical area minimization.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Kristian Granhaug, Snorre Aunet	Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates.	DFT	2006	DBLP DOI BibTeX RDF
15	Xianlong Hong, Yici Cai, Hailong Yao, Duo Li	DFM-aware Routing for Yield Enhancement.	APCCAS	2006	DBLP DOI BibTeX RDF