Search results for "delays"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
13	Pierluigi Salvo Rossi, Gianmarco Romano, Francesco Palmieri 0001, Giulio Iannello	Bayesian Modelling for Packet Channels.	WIRN	2003	DBLP DOI BibTeX RDF
13	Rodica Branzei, Giulio Ferrari, Vito Fragnelli, Stef Tijs	Two Approaches to the Problem of Sharing Delay Costs in Joint Projects.	Ann. Oper. Res.	2002	DBLP DOI BibTeX RDF	activity graph, delay cost, taxation, serial cost sharing, bankruptcy
13	Constantinos Dovrolis, Dimitrios Stiliadis, Parameswaran Ramanathan	Proportional differentiated services: delay differentiation and packet scheduling.	IEEE/ACM Trans. Netw.	2002	DBLP DOI BibTeX RDF	Dynamic priorities, resource management algorithms, quality of service
13	Roland E. Suri, Terrence J. Sejnowski	Spike propagation synchronized by temporally asymmetric Hebbian learning.	Biol. Cybern.	2002	DBLP DOI BibTeX RDF
13	Manish Jain, Constantinos Dovrolis	End-to-end available bandwidth: measurement methodology, dynamics, and relation with TCP throughput.	SIGCOMM	2002	DBLP DOI BibTeX RDF	bulk transfer capacity, network capacity, active probing, bottleneck bandwidth, packet pair dispersion
13	Anindya Datta, Kaushik Dutta, Helen M. Thomas, Debra E. VanderMeer, Suresha, Krithi Ramamritham	Proxy-based acceleration of dynamically generated content on the world wide web: an approach and implementation.	SIGMOD Conference	2002	DBLP DOI BibTeX RDF	proxy-based caching, dynamic content, edge caching
13	Anindya Datta, Kaushik Dutta, Helen M. Thomas, Debra E. VanderMeer, Krithi Ramamritham, Suresha	A Proxy-Based Approach for Dynamic Content Acceleration on the WWW.	WECWIS	2002	DBLP DOI BibTeX RDF
13	Kasper Støy, Wei-Min Shen, Peter M. Will	How to make a self-reconfigurable robot run.	AAMAS	2002	DBLP DOI BibTeX RDF
13	Masahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori	A high-speed dynamic instruction scheduling scheme for superscalar processors.	MICRO	2001	DBLP DOI BibTeX RDF
13	David W. Hutchison, Stacy D. Hill	Airline and airport applications: simulation optimization of airline delay with constraints.	WSC	2001	DBLP DOI BibTeX RDF
13	Hayder Radha, Dmitri Loguinov	Encoder Buffer Constraints for Video Transmission Over Networks with No Quality-of-Service Guarantees.	ISCC	2001	DBLP DOI BibTeX RDF
13	Aman Shaikh, Albert G. Greenberg	Experience in black-box OSPF measurement.	Internet Measurement Workshop	2001	DBLP DOI BibTeX RDF	SPF calculation, black-box measurements, routing, OSPF
13	Ioannis Anagnostakis, John-Paul Clarke, Dietmar Böhme, Uwe Völckers	Runway Operations Planning and Control - Sequencing and Scheduling.	HICSS	2001	DBLP DOI BibTeX RDF
13	David W. Hutchison, Stacy D. Hill	Simulation Optimization of Airline Delay Using Simultaneous Perturbation Stochastic Approximation.	Annual Simulation Symposium	2000	DBLP DOI BibTeX RDF	constrained optimization, nonlinear, stochastic approximation, discrete simulation, aerospace industry
13	Aman Shaikh, Anujan Varma, Lampros Kalampoukas, Rohit Dube	Routability stability in congested networks: experimentation and analysis.	SIGCOMM	2000	DBLP DOI BibTeX RDF
13	William T. Zaumen, Srinivas Vutukury, J. J. Garcia-Luna-Aceves	Load-Balanced Anycast Routing in Computer Networks.	ISCC	2000	DBLP DOI BibTeX RDF	Internet, Routing, Load Balancing, Anycasting
13	Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng	Dynamic Timing Analysis Considering Power Supply Noise Effects.	ISQED	2000	DBLP DOI BibTeX RDF	dynamic timing analysis, input pattern dependent, power supply noise, deep submicron designs
13	Ivan S. Kourtev, Eby G. Friedman	Clock skew scheduling for improved reliability via quadratic programming.	ICCAD	1999	DBLP DOI BibTeX RDF
13	Michael H. Kalantar, Kenneth P. Birman	Causally Ordered Multicast: the Conservative Approach.	ICDCS	1999	DBLP DOI BibTeX RDF	causally ordered multicast, performance, ISIS, process group
13	Srividhya Subramanian, Mukesh Singhal	A Real-Time Protocol for Stock Market Transactions.	WECWIS	1999	DBLP DOI BibTeX RDF
13	Pradeep Prabhakaran, Prithviraj Banerjee	Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis.	VLSI Design	1998	DBLP DOI BibTeX RDF	timing driven synthesis, High-level synthesis, floorplanning
13	James H. Anderson, Mark Moir	Using Local-Spin k-Exclusion Algorithms to Improve Wait-Free Object Implementations.	Distributed Comput.	1997	DBLP DOI BibTeX RDF	k -Assignment, k -Exclusion, Shared subjects, Shared-memory multiprocessors, Resiliency, Wait-free, Local spinning
13	Peter A. Walker, Sumit Ghosh	On the nature and inadequacies of transport timing delay constructs in VHDL descriptions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
13	Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel	Effects of delay models on peak power estimation of VLSI sequential circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	variable delay, sustainable power, n-cycle power, peak power, genetic optimization
13	Hans Hansson, Mikael Sjödin, Ken Tindell	Guaranteeing Real-Time Traffic Through an ATM Network.	HICSS (5)	1997	DBLP DOI BibTeX RDF
13	John R. Feehrer, Lars H. Ramfelt	Packet Synchronization for Synchronous Optical Deflection-Routed Interconnection Networks.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	synchronization, interconnection networks, integer programming, packet switching, constrained optimization, optical interconnects, propagation delay, Deflection routing
13	Ching-Yi Wang, Keshab K. Parhi	High-level DSP synthesis using concurrent transformations, scheduling, and allocation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
13	Charles U. Martel, Vojin G. Oklobdzija, R. Ravi 0001, Paul F. Stelling	Design Strategies for Optimal Multiplier Circuits.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	Algorithms, Circuit design, Partial product reduction, Multiplier design
13	Tanay Karnik, Sung-Mo Kang	An empirical model for accurate estimation of routing delay in FPGAs.	ICCAD	1995	DBLP DOI BibTeX RDF	Routing Delay, Modeling, FPGA, Estimation, Statistics
13	Shailender Chaudhry, Mohammed Raziuddin, Alok N. Choudhary	On guaranteed bandwidth channels.	ICNP	1995	DBLP DOI BibTeX RDF
13	Syed A. Aftab, M. A. Styblinski	A new efficient approach to statistical delay modeling of CMOS digital combinational circuits.	ICCAD	1994	DBLP DOI BibTeX RDF
13	Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage	RC interconnect synthesis-a moment fitting approach.	ICCAD	1994	DBLP DOI BibTeX RDF
13	Donald A. Joy, Maciej J. Ciesielski	Clock period minimization with wave pipelining.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
13	David C. Ku, Giovanni De Micheli	Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
13	Anthonie B. Ruighaver	A Decoupled Multicomputer Architecture with Optical Full Interconnection.	CONPAR	1992	DBLP DOI BibTeX RDF
13	Mark R. Greenstreet, Kenneth Steiglitz	Bubbles can make self-timed pipelines fast.	J. VLSI Signal Process.	1990	DBLP DOI BibTeX RDF
13	Marco Ajmone Marsan, Giovanni Chiola	On Petri nets with deterministic and exponentially distributed firing times.	European Workshop on Applications and Theory of Petri Nets	1986	DBLP DOI BibTeX RDF
13	Rami R. Razouk	The derivation of performance expressions for communication protocols from timed petri net models.	Comput. Commun. Rev.	1984	DBLP DOI BibTeX RDF
13	Stephen William Edge	An adaptive timeout algorithm for retransmission across a packet switching network.	Comput. Commun. Rev.	1984	DBLP DOI BibTeX RDF
12	Jörg Liebeherr, Yashar Ghiassi-Farrokhfal, Almut Burchard	Does Link Scheduling Matter on Long Paths?.	ICDCS	2010	DBLP DOI BibTeX RDF	Computer Networks, network calculus, end-to-end delays, link scheduling
12	Rachna Dhand, Gareth Lee, Graeme Cole	Analytical Temporal Specification Issues for Industrial Control Systems.	AINA Workshops	2010	DBLP DOI BibTeX RDF	RT-Java, Giotto, DataSocket Transport Protocol (DSTP), Publish-Subscribe, Network Delays, Discrete-Time Systems, Industrial Control Systems
12	Arijit Mondal, Partha Pratim Chakrabarti, Pallab Dasgupta	Accelerating Synchronous Sequential Circuits Using an Adaptive Clock.	VLSI Design	2010	DBLP DOI BibTeX RDF	VLSI, CAD, delays, Timing, sequential circuits, Timing optimization
12	I-Hong Hou, P. R. Kumar 0001	Admission control and scheduling for QoS guarantees for variable-bit-rate applications on wireless channels.	MobiHoc	2009	DBLP DOI BibTeX RDF	scheduling, real-time, delays, admission control, deadlines, qos
12	Haiyan Yan, Bo Xu	Using of Interactive Learning Environment in Experimental Study.	NCM	2009	DBLP DOI BibTeX RDF	Interactive Learning Environment (ILE), information delays, system dynamics
12	Quanjun Wu, Lan Xiang 0001, Jin Zhou	Average Consensus in Delayed Networks of Dynamic Agents with Impulsive Effects.	Complex (1)	2009	DBLP DOI BibTeX RDF	average consensus, undirected network, impulsive effects, multi-agent systems, time-delays
12	Benjamin M. Lambeth, James LaPlant, Elena Clapan, Felix G. Hamza-Lup	The effects of network delay on task performance in a visual-haptic collaborative environment.	ACM Southeast Regional Conference	2009	DBLP DOI BibTeX RDF	haptics, collaborative virtual environments, network delays
12	Yan Li	Evolution Differential Systems with Impulse and Delay.	ISNN (1)	2009	DBLP DOI BibTeX RDF	Evolution differential systems, Delays, Impulses, Existence
12	Junhao Hu, Huafeng Chen	Neutral Differential Systems with Impulse and Delay.	ISNN (1)	2009	DBLP DOI BibTeX RDF	Neutral differential systems, Delays, Impulses, existence
12	Jianli Ding, Xuesen Li, Guansheng Tong	The Dynamic Immune Forecasting Method of the Airdrome Flight Delay under Considering the Stochastic Factors.	HIS (3)	2009	DBLP DOI BibTeX RDF	flight delays, stochastic factors, negative selection algorithm, dynamic forecasting
12	Atif Nazir, Saqib Raza, Dhruv Gupta 0001, Chen-Nee Chuah, Balachander Krishnamurthy	Network level footprints of facebook applications.	Internet Measurement Conference	2009	DBLP DOI BibTeX RDF	delays, applications, platform, facebook, online social networks, social games
12	Bharadwaj Veeravalli, Jingxi Jia	Design, Analysis, and Performance Evaluation of an Efficient Resource Unaware Scheduling Strategy for Processing Divisible Loads on Distributed Linear Daisy Chain Networks.	HiPC	2008	DBLP DOI BibTeX RDF	communication delays, Divisible Loads, processing time, Linear Networks
12	Wenwu Yu, Jinde Cao	Robust Control of Uncertain Stochastic Recurrent Neural Networks with Time-varying Delay.	Neural Process. Lett.	2007	DBLP DOI BibTeX RDF	LMI approach, Robust control, Lyapunov functional, Time-varying delays, Global asymptotical stability, Stochastic neural networks
12	Ruchir Shah, Bharadwaj Veeravalli, Manoj Misra	On the Design of Adaptive and Decentralized Load Balancing Algorithms with Load Estimation for Computational Grid Environments.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	load balancing, migration, communication delays, Grid systems, average response time
12	Maria Spyropoulou, Konstantinos Yiannopoulos, Stelios Sygletos, Kyriakos Vlachos, Ioannis Tomkos	160 Gbps Simulation of a Quantum Dot Semiconductor Optical Amplifier Based Optical Buffer.	ONDM	2007	DBLP DOI BibTeX RDF	Quantum Dot Semiconductor Optical Amplifiers, Programmable Delays, Optical packet switching, Optical buffers, Wavelength Converters
12	Bharadwaj Veeravalli, Wong Han Min	Scheduling Divisible Loads on Heterogeneous Linear Daisy Chain Networks with Arbitrary Processor Release Times.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	finish times, communication delays, divisible loads, processing times, release times, Linear networks
12	Jingnan Yao, Bharadwaj Veeravalli	Design and Performance Analysis of Divisible Load Scheduling Strategies on Arbitrary Graphs.	Clust. Comput.	2004	DBLP DOI BibTeX RDF	arbitrary graphs, spanning tree networks, communication delays, divisible loads, load distribution, processing time
12	Maciej Drozdowski, Pawel Wolniewicz	Out-of-Core Divisible Load Processing.	IEEE Trans. Parallel Distributed Syst.	2003	DBLP DOI BibTeX RDF	scheduling, performance evaluation, memory hierarchy, communication delays, Divisible load theory
12	Zohreh Nazeri, Jianping Zhang	Mining Aviation Data to Understand Impacts of Severe Weather On Airspace System Performance.	ITCC	2002	DBLP DOI BibTeX RDF	Flight Delays, Severe Weather Analysis, NAS performance, Data Mining, Aviation
12	Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang	Charge sharing fault analysis and testing for CMOS domino logic circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	charge sharing fault analysis, CMOS domino logic circuits, domino logic design, sensitivity measurement, domino gate, fault diagnosis, logic testing, delays, delay, automatic testing, CMOS logic circuits, logic gates, test vectors
12	Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen	Peak-power reduction for multiple-scan circuits during test application.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	peak-power reduction, multiple scan chain based circuits, peak periodicity, peak width, power waveforms, scan-based circuits, delay buffers, interleaving scan technique, data output, logic testing, logic testing, delays, integrated circuit testing, application specific integrated circuits, SOC, boundary scan testing
12	Liang-Chi Chen, Sandeep K. Gupta 0001, Melvin A. Breuer	A new framework for static timing analysis, incremental timing refinement, and timing simulation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	incremental timing refinement, signal arrival, target fault, test generation efficiency, logic testing, delays, timing, test generation, integrated circuit testing, computation, automatic test pattern generation, ATPG, static timing analysis, delay model, timing simulation
12	Abderrahim Doumar, Hideo Ito	Testing approach within FPGA-based fault tolerant systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase
12	Libin Dong, Rami G. Melhem, Daniel Mossé	Effect of scheduling jitter on end-to-end delay in TDMA protocols.	RTCSA	2000	DBLP DOI BibTeX RDF	scheduling jitter, TDMA protocols, time slot allocation algorithm, transmission rate, ETE delay bound, simulations, scheduling, distributed system, real-time systems, delays, time division multiple access, time division multiple access, jitter, real time communication, end-to-end delay, packet delay, destination node
12	Song Wang, Yu-Chung Wang, Kwei-Jay Lin	Integrating the fixed priority scheduling and the total bandwidth server for aperiodic tasks.	RTCSA	2000	DBLP DOI BibTeX RDF	total bandwidth server, aperiodic job scheduling, priority-based weighted fair queueing schedule, session delay, leaky bucket model, scheduling, real-time systems, delays, computer networks, queueing theory, bandwidth, response time, bandwidth allocation, sliding window, fixed priority scheduling, real-time networks
12	Cumbur Aksoy, Abdelsalam Helal	Optimising thin clients for wireless active-media applications.	WMCSA	2000	DBLP DOI BibTeX RDF	thin client optimization, wireless active media applications, low-bandwidth mobile environments, resource-poor devices, critical applications, thin client performance, mobile computing, wireless networks, localization, wireless LAN, delays, case studies, optimisation, network computers, network latency
12	Abby A. Ilumoka	Efficient prediction of interconnect crosstalk using neural networks.	ICTAI	2000	DBLP DOI BibTeX RDF	interconnect crosstalk prediction, deep submicron downscaling, wirecells, modular artificial neural networks, multiparadigm prototyping system, equicoupling contours, isocouples, transconductance amplifier, neural networks, delays, delay, finite element method, neural nets, crosstalk, experimental results, circuit CAD, finite element analysis, circuit simulation, circuit simulator, integrated circuit interconnections, wafer-scale integration, wafer scale integration
12	Matthew K. H. Leung, John C. S. Lui, David K. Y. Yau	Characterization and Performance Evaluation for Proportional Delay Differentiated Services.	ICNP	2000	DBLP DOI BibTeX RDF	proportional delay differentiated services, Internet differentiated services, traffic classes, tariff rate, time-dependent priority scheduling, proportional delay model, delay ratios, scheduling parameters, efficient control algorithm, relative waiting time, performance evaluation, performance evaluation, Internet, delays, telecommunication traffic, waiting times, telecommunication services, ISP, feasible regions, average waiting time, service classes
12	Samuel T. Chanson, Wantao Deng, Chi-Chung Hui, Xueyan Tang, Ming Yan To	Multidomain Load Balancing.	ICNP	2000	DBLP DOI BibTeX RDF	multidomain load balancing, Internet communication speed, lag time, load information updating, job transfer, least load scheduler, update techniques, machine load, BALANCE testbed, performance evaluation, Internet, delays, local area networks, system performance, hierarchical structure, LAN interconnection, LAN interconnection, network cost, load balancing algorithms, limited bandwidth
12	Song Ci, Hamid Sharif	Adaptive Approaches to Enhance Throughput of IEEE 802.11 Wireless LAN with Bursty Channel.	LCN	2000	DBLP DOI BibTeX RDF	bursty channel, back-off based fragment adaptive algorithms, channel throughput, system end-to-end delay reduction, wireless LAN, delays, throughput, noise, adaptive systems, simulation results, telecommunication standards, IEEE standards, telecommunication channels, IEEE 802.11 wireless LAN, noisy channel
12	Markus Albrecht, Michael Köster, Peter Martini, Matthias Frank 0001	End-to-End QoS Management for Delay-Sensitive Scalable Multimedia Streams over DiffServ.	LCN	2000	DBLP DOI BibTeX RDF	delay-sensitive scalable multimedia streams, network-level service, application level data streams, QoS management system, scaling properties, layered media streams, quality of service, quality of service, Internet, Internet, delays, multimedia communication, multimedia applications, Differentiated Services, DiffServ, real-time communication, computer network management, multimedia servers, multimedia servers, computer communication, network resources
12	Yutaka Ishibashi, Shuji Tasaka	A Comparative Survey of Sychronization Algorithms for Continuous Media in Network Environments.	LCN	2000	DBLP DOI BibTeX RDF	comparative survey, media synchronization control techniques, basic control, preventive control, common control, network delay bounds, delays, multimedia systems, synchronisation, clocks, clocks, reviews, continuous media, telecommunication networks, algorithm design, telecommunication control, network environments, synchronization algorithms, reactive control
12	King-Shan Lui, Klara Nahrstedt, Shigang Chen	Hierarchical QoS Routing in Delay-Bandwidth Sensitive Networks.	LCN	2000	DBLP DOI BibTeX RDF	hierarchical QoS routing, delay-bandwidth sensitive networks, scaling problem, topology information, hierarchical routing protocols, QoS-aware topology aggregation, aggregated network state, end-to-end route, aggregated information, network QoS representation, distributed routing mechanism, quality of service, delays, network topology, simulation results, telecommunication network routing, line segments, network nodes, topology aggregation, routing performance
12	Jorge Arellano-Cid, Horst H. von Brand	Network Programming Internals of the Dillo Web Browser.	SCCC	2000	DBLP DOI BibTeX RDF	Dillo, delay sources, signal driven input output, nonblocking main thread, overlapping waiting times, Internet, delays, programming, threads, Web browser, multi-threading, network programming, input-output programs, online front-ends
12	Michael Dahlin	Interpreting Stale Load Information.	ICDCS	1999	DBLP DOI BibTeX RDF	load interpretation, distributed systems, load balancing, queueing models, communication delays
12	Abdel Krim Amoura, Evripidis Bampis, Jean-Claude König	Scheduling Algorithms for Parallel Gaussian Elimination With Communication Costs.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	Gaussian elimination method, scheduling, partitioning, mapping, Distributed architectures, communication delays
12	Guy E. Blelloch, Phillip B. Gibbons, Yossi Matias, Marco Zagha	Accounting for Memory Bank Contention and Delay in High-Bandwidth Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	Memory bank contention, memory delays, parallel machine models, parallel algorithms, performance analysis, multiprocessors, shared memory
12	Xiaohua Jia, Niki Pissinou, Kia Makki	A distributed algorithm of delay bounded multicast routing for multimedia applications.	ICCCN	1997	DBLP DOI BibTeX RDF	delay bounded multicast routing, source node, multicast destinations, distributed heuristic algorithm, sub-optimal network cost, delay bound constraint, multicast membership changes, simulations, delays, multimedia applications, routing trees
12	Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch	An optimized BIST test pattern generator for delay testing.	VTS	1997	DBLP DOI BibTeX RDF	BIST test pattern generator, robust delay fault coverage, single input change test sequence, compatible inputs, optimization, delays, built-in self-test, fault detection, delay testing, test length, area overhead, circuit under test
12	Jong Kim 0001, Kang G. Shin	Execution Time Analysis of Communicating Tasks in Distributed Systems.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	Task-execution time, communication and synchronization delays, distributed systems, queuing analysis
12	Byungho Kim, Boseob Kwon, Hyunsoo Yoon, Seungryul Maeng, Jung Wan Cho	Performance Analysis of Multipath Multistage Interconnection Networks with Nonuniform Output Traffic Distribution.	PDP	1996	DBLP DOI BibTeX RDF	buffer circuits, multipath multistage interconnection networks, nonuniform output traffic distribution, delay-throughput performance, packet arrival rates, output module., performance evaluation, performance analysis, delays, probability, packet switching, multistage interconnection networks, telecommunication traffic, packet delay, losses, output buffers, packet loss probability
12	Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal	Segment delay faults: a new fault model.	VTS	1996	DBLP DOI BibTeX RDF	segment delay faults, delay defect, distributed defect, rising transitions, falling transitions, transition tests, nonrobust tests, VLSI, fault diagnosis, logic testing, delays, integrated circuit testing, fault model, automatic testing, circuit analysis computing, robust tests, integrated circuit modelling, production testing, spot defect, manufacturing defects
12	S. Crepaux-Motte, Mireille Jacomino, Rene David	An algebraic method for delay fault testing.	VTS	1996	DBLP DOI BibTeX RDF	input values, output function, robustly testable fault, nonrobustly testable fault, weakly verifiable, fault diagnosis, logic testing, delays, timing, Markov processes, random testing, delay fault testing, state transition, input vectors, algebraic method
12	S. Cremoux, Christophe Fagot, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch	A new test pattern generation method for delay fault testing.	VTS	1996	DBLP DOI BibTeX RDF	test pattern generation method, directed random generation technique, random test vectors, test sequence length, delay fault coverage, learning (artificial intelligence), VLSI, logic testing, delays, built-in self test, integrated circuit testing, BIST, automatic testing, delay fault testing, digital integrated circuits, learning tool, high speed circuits
12	Mukund Sivaraman, Andrzej J. Strojwas	A diagnosability metric for parametric path delay faults.	VTS	1996	DBLP DOI BibTeX RDF	diagnosability metric, parametric path delay faults, test vector pairs, chip failure, fabrication process parameter variations, diagnosis framework, ISCAS'89 benchmark circuits, VLSI, fault diagnosis, logic testing, delays, timing, integrated circuit testing, failure analysis, diagnosability, delay fault testing, test set
12	Prasanti Uppaluri, Uwe Sparmann, Irith Pomeranz	On minimizing the number of test points needed to achieve complete robust path delay fault testability.	VTS	1996	DBLP DOI BibTeX RDF	robust path delay fault testability, RD fault identification, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuit, test point insertion
12	Yuyun Liao, D. M. H. Walker	Optimal voltage testing for physically-based faults.	VTS	1996	DBLP DOI BibTeX RDF	optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise
12	Valery A. Vardanian	On completely robust path delay fault testable realization of logic functions.	VTS	1996	DBLP DOI BibTeX RDF	robust path delay fault testable realization, two-level completely RPDFT realization, RPDFT-extension, input variables, VLSI, VLSI, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, integrated circuit testing, combinational circuits, combinational circuits, multivalued logic circuits, symmetric functions
12	Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal	Improving accuracy in path delay fault coverage estimation.	VLSI Design	1996	DBLP DOI BibTeX RDF	fault coverage estimation, simulated vector pair, exact fault simulation, fixed-length path-segments, fan-in branches, fan-out branches, flagged path-segments, segment lengths, combinational paths, graph theory, fault diagnosis, logic testing, delays, combinational circuits, logic CAD, circuit analysis computing, path delay fault, approximate methods, CPU time
12	Prathima Agrawal, Balakrishnan Narendran, Narayanan Shivakumar	Multi-way partitioning of VLSI circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	multi-way partitioning, hierarchical design processes, nets cut metric, VLSI, delays, economics, logic CAD, VLSI layout, integrated circuit layout, VLSI circuits, logic partitioning, minimisation of switching nets, average delay, integrated circuit manufacture, cost metric
12	S. Ramanathan, V. Visvanathan	A systolic architecture for LMS adaptive filtering with minimal adaptation delay.	VLSI Design	1996	DBLP DOI BibTeX RDF	LMS adaptive filtering, minimal adaptation delay, convergence behaviour, function preserving transformations, SFG representation, carry-save arithmetic, systolic folded pipelined architecture, VLSI, delays, systolic arrays, pipeline processing, adaptive filters, digital filters, digital signal processing chips, convergence of numerical methods, systolic architecture, signal flow graphs, signal flow graph, least mean squares methods, LMS algorithm
12	Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal	Parallel concurrent path-delay fault simulation using single-input change patterns.	VLSI Design	1996	DBLP DOI BibTeX RDF	concurrent path-delay fault simulation, single-input change patterns, singly-testable path-delay faults, random values, rising transitions, falling transitions, sixteen-valued algebra, machine word parallelism, ISCAS '85 benchmarks, ISCAS '89 benchmarks, parallel algorithms, fault diagnosis, logic testing, delays, Boolean functions, sequential circuits, logic CAD, circuit analysis computing, flip-flops, Boolean operations
12	G. Enrique Fernandez, R. Sridhar	Dual rail static CMOS architecture for wave pipelining.	VLSI Design	1996	DBLP DOI BibTeX RDF	dual rail static CMOS architecture, gate capacitance, storage elements, DRSCMOS, multi-functional basic building blocks, combinational logic block, delays, timing, throughput, combinational circuits, power consumption, pipeline processing, CMOS logic circuits, digital systems, capacitance, wave pipelining, delay variations
12	Mukund Sivaraman, Andrzej J. Strojwas	Diagnosis of parametric path delay faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	parametric path delay faults, chip failure, fabrication process parameter values, path sensitization mechanism, path delay conditions, ISCAS'89 benchmark circuits, path segment, circuit failure, fault diagnosis, logic testing, logic testing, delays, probability, probability, statistical analysis, statistical analysis, integrated circuit testing, failure analysis, diagnosability, delay fault testing, IC testing, production testing
12	Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal	On test coverage of path delay faults.	VLSI Design	1996	DBLP DOI BibTeX RDF	two-pass test generation method, falling transition, line delay test, longest sensitizable path, decreasing length, redundant stuck-at fault, computational complexity, fault diagnosis, logic testing, delays, redundancy, combinational circuits, fault simulation, circuit analysis computing, test coverage, path delay faults, benchmark circuits, coverage metric, combinational logic circuits, longest paths
12	Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas	Statistical path delay fault coverage estimation for synchronous sequential circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	path delay fault coverage estimation, multi-valued algebra, signal statistics, latch updating, fault diagnosis, logic testing, delays, probability, controllability, controllability, statistical analysis, sequential circuits, observability, observabilities, logic simulation, synchronous sequential circuits, statistical estimation
12	Nuno Vasconcelos, Andrew Lippman	Spatiotemporal model-based optic flow estimation.	ICIP	1995	DBLP DOI BibTeX RDF	spatiotemporal model based estimation, spatiotemporal model based algorithm, spatiotemporal motion model, quadratic constraint, affine constraint, space constraint, delayed decision process, classification, motion estimation, delays, interpolation, interpolation, data compression, image sequences, parameter estimation, video coding, video stream, image classification, time constraint, video compression, least squares approximations, correlation methods, temporal coherence, least squares fit, video frames, image correlation, optic flow estimation, interactive access
12	Baruch Awerbuch, Yossi Azar, Edward F. Grove, Ming-Yang Kao, P. Krishnan, Jeffrey Scott Vitter	Load Balancing in the Lp Norm.	FOCS	1995	DBLP DOI BibTeX RDF	L/sub p/ norm, job assignment, L/sub /spl infin// norm, maximum load, greedy load balancing algorithm, offline optimal, average job delay, sum of the squares, load balancing, resource allocation, delays, queueing theory, deterministic algorithms, deterministic algorithm, competitive algorithms, competitive algorithms, online operation, online operation, Euclidean norm
12	Meng-Lieh Sheu, Chung-Len Lee 0001	A programmable multiple-sequence generator for BIST applications.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	programmable multiple-sequence generator, BIST applications, two-dimension-like feedback shift register, deterministic sequence, pseudo-random vectors, sequence segmentation method, stuck-open fault testing, logic testing, delays, built-in self test, sequential circuits, shift registers, delay fault testing, binary sequences, sequential circuit testing, regular structure, MCM testing
12	Branka Medved Rogina, Bozidar Vojnovic	Metastability evaluation method by propagation delay distribution measurement.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	propagation delay distribution measurement, edge-triggered flip-flops, input signals time relationship, output signal timing characteristics, analytical representation, propagation delay density distribution function, fault events, integrated propagation delay density distribution function, flip-flop normal propagation delay, resolution time constant, automatic data acquisition, complex architecture microsystems, MTBF, latch devices, custom CMOS, VLSI, VLSI, fault diagnosis, logic testing, delays, logic design, asynchronous circuits, flip-flops, data acquisition, failure analysis, reliability analysis, graphical representation, metastability, PLD, asynchronous logic, integrated circuit reliability, statistical measurement
12	Jason P. Hurst, Nick Kanopoulos	Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	flip-flop sharing, standard scan path, standard scan path design, two-vector test sets, VLSI, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, sequential circuits, flip-flops, integrated logic circuits, sequential machines, delay fault testing