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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 5912 occurrences of 2755 keywords
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Results
Found 14022 publication records. Showing 14022 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
13 | Pierluigi Salvo Rossi, Gianmarco Romano, Francesco Palmieri 0001, Giulio Iannello |
Bayesian Modelling for Packet Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WIRN ![In: Neural Nets, 14th Italian Workshop on Neural Nets, WIRN VIETRI 2003, Vietri sul Mare, Italy, June 4-7, 2003, Revised Papers, pp. 218-225, 2003, Springer, 3-540-20227-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
13 | Rodica Branzei, Giulio Ferrari, Vito Fragnelli, Stef Tijs |
Two Approaches to the Problem of Sharing Delay Costs in Joint Projects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 109(1-4), pp. 359-374, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
activity graph, delay cost, taxation, serial cost sharing, bankruptcy |
13 | Constantinos Dovrolis, Dimitrios Stiliadis, Parameswaran Ramanathan |
Proportional differentiated services: delay differentiation and packet scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 10(1), pp. 12-26, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Dynamic priorities, resource management algorithms, quality of service |
13 | Roland E. Suri, Terrence J. Sejnowski |
Spike propagation synchronized by temporally asymmetric Hebbian learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Biol. Cybern. ![In: Biol. Cybern. 87(5-6), pp. 440-445, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
13 | Manish Jain, Constantinos Dovrolis |
End-to-end available bandwidth: measurement methodology, dynamics, and relation with TCP throughput. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCOMM ![In: Proceedings of the ACM SIGCOMM 2002 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication, August 19-23, 2002, Pittsburgh, PA, USA, pp. 295-308, 2002, ACM, 1-58113-570-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
bulk transfer capacity, network capacity, active probing, bottleneck bandwidth, packet pair dispersion |
13 | Anindya Datta, Kaushik Dutta, Helen M. Thomas, Debra E. VanderMeer, Suresha, Krithi Ramamritham |
Proxy-based acceleration of dynamically generated content on the world wide web: an approach and implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Conference ![In: Proceedings of the 2002 ACM SIGMOD International Conference on Management of Data, Madison, Wisconsin, USA, June 3-6, 2002, pp. 97-108, 2002, ACM, 1-58113-497-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
proxy-based caching, dynamic content, edge caching |
13 | Anindya Datta, Kaushik Dutta, Helen M. Thomas, Debra E. VanderMeer, Krithi Ramamritham, Suresha |
A Proxy-Based Approach for Dynamic Content Acceleration on the WWW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WECWIS ![In: Fourth IEEE International Workshop on Advanced Issues of E-Commerce and Web-Based Information Systems (WECWIS'02), Newport Beach, California, USA, June 26-28, 2002, pp. 159-164, 2002, IEEE Computer Society, 0-7695-1567-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
13 | Kasper Støy, Wei-Min Shen, Peter M. Will |
How to make a self-reconfigurable robot run. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AAMAS ![In: The First International Joint Conference on Autonomous Agents & Multiagent Systems, AAMAS 2002, July 15-19, 2002, Bologna, Italy, Proceedings, pp. 813-820, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
13 | Masahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori |
A high-speed dynamic instruction scheduling scheme for superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001, pp. 225-236, 2001, ACM/IEEE Computer Society, 0-7695-1369-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
13 | David W. Hutchison, Stacy D. Hill |
Airline and airport applications: simulation optimization of airline delay with constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSC ![In: Proceedings of the 33nd conference on Winter simulation, WSC 2001, Arlington, VA, USA, December 9-12, 2001, pp. 1017-1022, 2001, WSC, 0-7803-7309-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
13 | Hayder Radha, Dmitri Loguinov |
Encoder Buffer Constraints for Video Transmission Over Networks with No Quality-of-Service Guarantees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCC ![In: Proceedings of the Sixth IEEE Symposium on Computers and Communications (ISCC 2001), 3-5 July 2001, Hammamet, Tunisia, pp. 359-363, 2001, IEEE Computer Society, 0-7695-1177-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
13 | Aman Shaikh, Albert G. Greenberg |
Experience in black-box OSPF measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Internet Measurement Workshop ![In: Proceedings of the 1st ACM SIGCOMM Internet Measurement Workshop, IMW 2001, San Francisco, California, USA, November 1-2, 2001, pp. 113-125, 2001, ACM, 1-58113-435-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
SPF calculation, black-box measurements, routing, OSPF |
13 | Ioannis Anagnostakis, John-Paul Clarke, Dietmar Böhme, Uwe Völckers |
Runway Operations Planning and Control - Sequencing and Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 34th Annual Hawaii International Conference on System Sciences (HICSS-34), January 3-6, 2001, Maui, Hawaii, USA, 2001, IEEE Computer Society, 0-7695-0981-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
13 | David W. Hutchison, Stacy D. Hill |
Simulation Optimization of Airline Delay Using Simultaneous Perturbation Stochastic Approximation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 33th Annual Simulation Symposium (SS 2000), 16-22 April 2000, Washington, DC, USA, pp. 253-258, 2000, IEEE Computer Society, 0-7695-0598-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
constrained optimization, nonlinear, stochastic approximation, discrete simulation, aerospace industry |
13 | Aman Shaikh, Anujan Varma, Lampros Kalampoukas, Rohit Dube |
Routability stability in congested networks: experimentation and analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCOMM ![In: Proceedings of the ACM SIGCOMM 2000 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication, August 28 - September 1, 2000, Stockholm, Sweden, pp. 163-174, 2000, ACM, 1-58113-223-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | William T. Zaumen, Srinivas Vutukury, J. J. Garcia-Luna-Aceves |
Load-Balanced Anycast Routing in Computer Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCC ![In: Proceedings of the Fifth IEEE Symposium on Computers and Communications (ISCC 2000), 4-6 July 2000, Antibes, France, pp. 566-574, 2000, IEEE Computer Society, 0-7695-0722-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Internet, Routing, Load Balancing, Anycasting |
13 | Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng |
Dynamic Timing Analysis Considering Power Supply Noise Effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 137-144, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
dynamic timing analysis, input pattern dependent, power supply noise, deep submicron designs |
13 | Ivan S. Kourtev, Eby G. Friedman |
Clock skew scheduling for improved reliability via quadratic programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 239-243, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Michael H. Kalantar, Kenneth P. Birman |
Causally Ordered Multicast: the Conservative Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS ![In: Proceedings of the 19th International Conference on Distributed Computing Systems, Austin, TX, USA, May 31 - June 4, 1999, pp. 36-44, 1999, IEEE Computer Society, 0-7695-0222-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
causally ordered multicast, performance, ISIS, process group |
13 | Srividhya Subramanian, Mukesh Singhal |
A Real-Time Protocol for Stock Market Transactions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WECWIS ![In: Proceedings of the First International Workshop on Advance Issues of E-Commerce and Web-Based Information Systems, Santa Clara, California, USA, April 8-9, 1999, pp. 2-10, 1999, IEEE Computer Society, 0-7695-0334-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Pradeep Prabhakaran, Prithviraj Banerjee |
Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 428-434, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
timing driven synthesis, High-level synthesis, floorplanning |
13 | James H. Anderson, Mark Moir |
Using Local-Spin k-Exclusion Algorithms to Improve Wait-Free Object Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 11(1), pp. 1-20, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
k -Assignment, k -Exclusion, Shared subjects, Shared-memory multiprocessors, Resiliency, Wait-free, Local spinning |
13 | Peter A. Walker, Sumit Ghosh |
On the nature and inadequacies of transport timing delay constructs in VHDL descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(8), pp. 894-915, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
13 | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel |
Effects of delay models on peak power estimation of VLSI sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 45-51, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
variable delay, sustainable power, n-cycle power, peak power, genetic optimization |
13 | Hans Hansson, Mikael Sjödin, Ken Tindell |
Guaranteeing Real-Time Traffic Through an ATM Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (5) ![In: 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 7-10 January 1997, Maui, Hawaii, USA, pp. 44-53, 1997, IEEE Computer Society, 0-8186-7734-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
13 | John R. Feehrer, Lars H. Ramfelt |
Packet Synchronization for Synchronous Optical Deflection-Routed Interconnection Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(6), pp. 605-611, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
synchronization, interconnection networks, integer programming, packet switching, constrained optimization, optical interconnects, propagation delay, Deflection routing |
13 | Ching-Yi Wang, Keshab K. Parhi |
High-level DSP synthesis using concurrent transformations, scheduling, and allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3), pp. 274-295, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
13 | Charles U. Martel, Vojin G. Oklobdzija, R. Ravi 0001, Paul F. Stelling |
Design Strategies for Optimal Multiplier Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 42-49, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Algorithms, Circuit design, Partial product reduction, Multiplier design |
13 | Tanay Karnik, Sung-Mo Kang |
An empirical model for accurate estimation of routing delay in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 328-331, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Routing Delay, Modeling, FPGA, Estimation, Statistics |
13 | Shailender Chaudhry, Mohammed Raziuddin, Alok N. Choudhary |
On guaranteed bandwidth channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNP ![In: 1995 International Conference on Network Protocols, ICNP 1995, November 7-10, 1995, Tokyo, Japan, pp. 47-, 1995, IEEE Computer Society, 0-8186-7216-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
13 | Syed A. Aftab, M. A. Styblinski |
A new efficient approach to statistical delay modeling of CMOS digital combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 200-203, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
13 | Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage |
RC interconnect synthesis-a moment fitting approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 418-425, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
13 | Donald A. Joy, Maciej J. Ciesielski |
Clock period minimization with wave pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(4), pp. 461-472, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
13 | David C. Ku, Giovanni De Micheli |
Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(6), pp. 696-718, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
13 | Anthonie B. Ruighaver |
A Decoupled Multicomputer Architecture with Optical Full Interconnection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 92 - VAPP V, Second Joint International Conference on Vector and Parallel Processing, Lyon, France, September 1-4, 1992, Proceedings, pp. 405-410, 1992, Springer, 3-540-55895-0. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
13 | Mark R. Greenstreet, Kenneth Steiglitz |
Bubbles can make self-timed pipelines fast. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 2(3), pp. 139-148, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
13 | Marco Ajmone Marsan, Giovanni Chiola |
On Petri nets with deterministic and exponentially distributed firing times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
European Workshop on Applications and Theory of Petri Nets ![In: Advances in Petri Nets 1987, covers the 7th European Workshop on Applications and Theory of Petri Nets, Oxford, UK, June 1986, pp. 132-145, 1986, Springer, 3-540-18086-9. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
13 | Rami R. Razouk |
The derivation of performance expressions for communication protocols from timed petri net models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Commun. Rev. ![In: Comput. Commun. Rev. 14(2), pp. 210-217, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
|
13 | Stephen William Edge |
An adaptive timeout algorithm for retransmission across a packet switching network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Commun. Rev. ![In: Comput. Commun. Rev. 14(2), pp. 248-255, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
|
12 | Jörg Liebeherr, Yashar Ghiassi-Farrokhfal, Almut Burchard |
Does Link Scheduling Matter on Long Paths?. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS ![In: 2010 International Conference on Distributed Computing Systems, ICDCS 2010, Genova, Italy, June 21-25, 2010, pp. 199-208, 2010, IEEE Computer Society, 978-0-7695-4059-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Computer Networks, network calculus, end-to-end delays, link scheduling |
12 | Rachna Dhand, Gareth Lee, Graeme Cole |
Analytical Temporal Specification Issues for Industrial Control Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA Workshops ![In: 24th IEEE International Conference on Advanced Information Networking and Applications Workshops, WAINA 2010, Perth, Australia, 20-13 April 2010, pp. 68-74, 2010, IEEE Computer Society, 978-0-7695-4019-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
RT-Java, Giotto, DataSocket Transport Protocol (DSTP), Publish-Subscribe, Network Delays, Discrete-Time Systems, Industrial Control Systems |
12 | Arijit Mondal, Partha Pratim Chakrabarti, Pallab Dasgupta |
Accelerating Synchronous Sequential Circuits Using an Adaptive Clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010, pp. 176-181, 2010, IEEE Computer Society, 978-0-7695-3928-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
VLSI, CAD, delays, Timing, sequential circuits, Timing optimization |
12 | I-Hong Hou, P. R. Kumar 0001 |
Admission control and scheduling for QoS guarantees for variable-bit-rate applications on wireless channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MobiHoc ![In: Proceedings of the 10th ACM Interational Symposium on Mobile Ad Hoc Networking and Computing, MobiHoc 2009, New Orleans, LA, USA, May 18-21, 2009, pp. 175-184, 2009, ACM, 978-1-60558-531-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
scheduling, real-time, delays, admission control, deadlines, qos |
12 | Haiyan Yan, Bo Xu |
Using of Interactive Learning Environment in Experimental Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NCM ![In: International Conference on Networked Computing and Advanced Information Management, NCM 2009, Fifth International Joint Conference on INC, IMS and IDC: INC 2009: International Conference on Networked Computing, IMS 2009: International Conference on Advanced Information Management and Service, IDC 2009: International Conference on Digital Content, Multimedia Technology and its Applications, Seoul, Korea, August 25-27, 2009, pp. 1747-1751, 2009, IEEE Computer Society, 978-0-7695-3769-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Interactive Learning Environment (ILE), information delays, system dynamics |
12 | Quanjun Wu, Lan Xiang 0001, Jin Zhou |
Average Consensus in Delayed Networks of Dynamic Agents with Impulsive Effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Complex (1) ![In: Complex Sciences, First International Conference, Complex 2009, Shanghai, China, February 23-25, 2009. Revised Papers, Part 1, pp. 1124-1138, 2009, Springer, 978-3-642-02465-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
average consensus, undirected network, impulsive effects, multi-agent systems, time-delays |
12 | Benjamin M. Lambeth, James LaPlant, Elena Clapan, Felix G. Hamza-Lup |
The effects of network delay on task performance in a visual-haptic collaborative environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference ![In: Proceedings of the 47th Annual Southeast Regional Conference, 2009, Clemson, South Carolina, USA, March 19-21, 2009, 2009, ACM, 978-1-60558-421-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
haptics, collaborative virtual environments, network delays |
12 | Yan Li |
Evolution Differential Systems with Impulse and Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (1) ![In: Advances in Neural Networks - ISNN 2009, 6th International Symposium on Neural Networks, ISNN 2009, Wuhan, China, May 26-29, 2009, Proceedings, Part I, pp. 532-541, 2009, Springer, 978-3-642-01506-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Evolution differential systems, Delays, Impulses, Existence |
12 | Junhao Hu, Huafeng Chen |
Neutral Differential Systems with Impulse and Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (1) ![In: Advances in Neural Networks - ISNN 2009, 6th International Symposium on Neural Networks, ISNN 2009, Wuhan, China, May 26-29, 2009, Proceedings, Part I, pp. 512-521, 2009, Springer, 978-3-642-01506-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Neutral differential systems, Delays, Impulses, existence |
12 | Jianli Ding, Xuesen Li, Guansheng Tong |
The Dynamic Immune Forecasting Method of the Airdrome Flight Delay under Considering the Stochastic Factors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HIS (3) ![In: 9th International Conference on Hybrid Intelligent Systems (HIS 2009), August 12-14, 2009, Shenyang, China, pp. 382-387, 2009, IEEE Computer Society, 978-0-7695-3745-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
flight delays, stochastic factors, negative selection algorithm, dynamic forecasting |
12 | Atif Nazir, Saqib Raza, Dhruv Gupta 0001, Chen-Nee Chuah, Balachander Krishnamurthy |
Network level footprints of facebook applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Internet Measurement Conference ![In: Proceedings of the 9th ACM SIGCOMM Internet Measurement Conference, IMC 2009, Chicago, Illinois, USA, November 4-6, 2009, pp. 63-75, 2009, ACM, 978-1-60558-771-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
delays, applications, platform, facebook, online social networks, social games |
12 | Bharadwaj Veeravalli, Jingxi Jia |
Design, Analysis, and Performance Evaluation of an Efficient Resource Unaware Scheduling Strategy for Processing Divisible Loads on Distributed Linear Daisy Chain Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2008, 15th International Conference, Bangalore, India, December 17-20, 2008. Proceedings, pp. 390-401, 2008, Springer, 978-3-540-89893-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
communication delays, Divisible Loads, processing time, Linear Networks |
12 | Wenwu Yu, Jinde Cao |
Robust Control of Uncertain Stochastic Recurrent Neural Networks with Time-varying Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Process. Lett. ![In: Neural Process. Lett. 26(2), pp. 101-119, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
LMI approach, Robust control, Lyapunov functional, Time-varying delays, Global asymptotical stability, Stochastic neural networks |
12 | Ruchir Shah, Bharadwaj Veeravalli, Manoj Misra |
On the Design of Adaptive and Decentralized Load Balancing Algorithms with Load Estimation for Computational Grid Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 18(12), pp. 1675-1686, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
load balancing, migration, communication delays, Grid systems, average response time |
12 | Maria Spyropoulou, Konstantinos Yiannopoulos, Stelios Sygletos, Kyriakos Vlachos, Ioannis Tomkos |
160 Gbps Simulation of a Quantum Dot Semiconductor Optical Amplifier Based Optical Buffer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ONDM ![In: Optical Network Design and Modeling, 11th International IFIP TC6 Conference, ONDM 2007, Athens, Greece, May 29-31, 2007., pp. 107-116, 2007, Springer, 978-3-540-72729-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Quantum Dot Semiconductor Optical Amplifiers, Programmable Delays, Optical packet switching, Optical buffers, Wavelength Converters |
12 | Bharadwaj Veeravalli, Wong Han Min |
Scheduling Divisible Loads on Heterogeneous Linear Daisy Chain Networks with Arbitrary Processor Release Times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 15(3), pp. 273-288, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
finish times, communication delays, divisible loads, processing times, release times, Linear networks |
12 | Jingnan Yao, Bharadwaj Veeravalli |
Design and Performance Analysis of Divisible Load Scheduling Strategies on Arbitrary Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Clust. Comput. ![In: Clust. Comput. 7(2), pp. 191-207, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
arbitrary graphs, spanning tree networks, communication delays, divisible loads, load distribution, processing time |
12 | Maciej Drozdowski, Pawel Wolniewicz |
Out-of-Core Divisible Load Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 14(10), pp. 1048-1056, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
scheduling, performance evaluation, memory hierarchy, communication delays, Divisible load theory |
12 | Zohreh Nazeri, Jianping Zhang |
Mining Aviation Data to Understand Impacts of Severe Weather On Airspace System Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCC ![In: 2002 International Symposium on Information Technology (ITCC 2002), 8-10 April 2002, Las Vegas, NV, USA, pp. 518-523, 2002, IEEE Computer Society, 0-7695-1506-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Flight Delays, Severe Weather Analysis, NAS performance, Data Mining, Aviation |
12 | Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang |
Charge sharing fault analysis and testing for CMOS domino logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 435-440, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
charge sharing fault analysis, CMOS domino logic circuits, domino logic design, sensitivity measurement, domino gate, fault diagnosis, logic testing, delays, delay, automatic testing, CMOS logic circuits, logic gates, test vectors |
12 | Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen |
Peak-power reduction for multiple-scan circuits during test application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 453-458, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
peak-power reduction, multiple scan chain based circuits, peak periodicity, peak width, power waveforms, scan-based circuits, delay buffers, interleaving scan technique, data output, logic testing, logic testing, delays, integrated circuit testing, application specific integrated circuits, SOC, boundary scan testing |
12 | Liang-Chi Chen, Sandeep K. Gupta 0001, Melvin A. Breuer |
A new framework for static timing analysis, incremental timing refinement, and timing simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 102-107, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
incremental timing refinement, signal arrival, target fault, test generation efficiency, logic testing, delays, timing, test generation, integrated circuit testing, computation, automatic test pattern generation, ATPG, static timing analysis, delay model, timing simulation |
12 | Abderrahim Doumar, Hideo Ito |
Testing approach within FPGA-based fault tolerant systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 411-416, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase |
12 | Libin Dong, Rami G. Melhem, Daniel Mossé |
Effect of scheduling jitter on end-to-end delay in TDMA protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 7th International Workshop on Real-Time Computing and Applications Symposium (RTCSA 2000), 12-14 December 2000, Cheju Island, South Korea, pp. 223-230, 2000, IEEE Computer Society, 0-7695-0930-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
scheduling jitter, TDMA protocols, time slot allocation algorithm, transmission rate, ETE delay bound, simulations, scheduling, distributed system, real-time systems, delays, time division multiple access, time division multiple access, jitter, real time communication, end-to-end delay, packet delay, destination node |
12 | Song Wang, Yu-Chung Wang, Kwei-Jay Lin |
Integrating the fixed priority scheduling and the total bandwidth server for aperiodic tasks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 7th International Workshop on Real-Time Computing and Applications Symposium (RTCSA 2000), 12-14 December 2000, Cheju Island, South Korea, pp. 215-222, 2000, IEEE Computer Society, 0-7695-0930-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
total bandwidth server, aperiodic job scheduling, priority-based weighted fair queueing schedule, session delay, leaky bucket model, scheduling, real-time systems, delays, computer networks, queueing theory, bandwidth, response time, bandwidth allocation, sliding window, fixed priority scheduling, real-time networks |
12 | Cumbur Aksoy, Abdelsalam Helal |
Optimising thin clients for wireless active-media applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WMCSA ![In: 3rd IEEE Workshop on Mobile Computing Systems and Applications (WMCSA 2000), 7-8 December 2000, Monterey, CA, USA, pp. 151-, 2000, IEEE Computer Society, 0-7695-0816-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
thin client optimization, wireless active media applications, low-bandwidth mobile environments, resource-poor devices, critical applications, thin client performance, mobile computing, wireless networks, localization, wireless LAN, delays, case studies, optimisation, network computers, network latency |
12 | Abby A. Ilumoka |
Efficient prediction of interconnect crosstalk using neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTAI ![In: 12th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2000), 13-15 November 2000, Vancouver, BC, Canada, pp. 122-125, 2000, IEEE Computer Society, 0-7695-0909-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
interconnect crosstalk prediction, deep submicron downscaling, wirecells, modular artificial neural networks, multiparadigm prototyping system, equicoupling contours, isocouples, transconductance amplifier, neural networks, delays, delay, finite element method, neural nets, crosstalk, experimental results, circuit CAD, finite element analysis, circuit simulation, circuit simulator, integrated circuit interconnections, wafer-scale integration, wafer scale integration |
12 | Matthew K. H. Leung, John C. S. Lui, David K. Y. Yau |
Characterization and Performance Evaluation for Proportional Delay Differentiated Services. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNP ![In: Eighth Annual International Conference on Network Protocols, ICNP 2000, 14-17 November, 2000, Osaka, Japan, pp. 295-304, 2000, IEEE Computer Society, 0-7695-0921-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
proportional delay differentiated services, Internet differentiated services, traffic classes, tariff rate, time-dependent priority scheduling, proportional delay model, delay ratios, scheduling parameters, efficient control algorithm, relative waiting time, performance evaluation, performance evaluation, Internet, delays, telecommunication traffic, waiting times, telecommunication services, ISP, feasible regions, average waiting time, service classes |
12 | Samuel T. Chanson, Wantao Deng, Chi-Chung Hui, Xueyan Tang, Ming Yan To |
Multidomain Load Balancing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNP ![In: Eighth Annual International Conference on Network Protocols, ICNP 2000, 14-17 November, 2000, Osaka, Japan, pp. 315-324, 2000, IEEE Computer Society, 0-7695-0921-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
multidomain load balancing, Internet communication speed, lag time, load information updating, job transfer, least load scheduler, update techniques, machine load, BALANCE testbed, performance evaluation, Internet, delays, local area networks, system performance, hierarchical structure, LAN interconnection, LAN interconnection, network cost, load balancing algorithms, limited bandwidth |
12 | Song Ci, Hamid Sharif |
Adaptive Approaches to Enhance Throughput of IEEE 802.11 Wireless LAN with Bursty Channel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: Proceedings 27th Conference on Local Computer Networks, Tampa, Florida, USA, 8-10 November, 2000, pp. 44-45, 2000, IEEE Computer Society, 0-7695-0912-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
bursty channel, back-off based fragment adaptive algorithms, channel throughput, system end-to-end delay reduction, wireless LAN, delays, throughput, noise, adaptive systems, simulation results, telecommunication standards, IEEE standards, telecommunication channels, IEEE 802.11 wireless LAN, noisy channel |
12 | Markus Albrecht, Michael Köster, Peter Martini, Matthias Frank 0001 |
End-to-End QoS Management for Delay-Sensitive Scalable Multimedia Streams over DiffServ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: Proceedings 27th Conference on Local Computer Networks, Tampa, Florida, USA, 8-10 November, 2000, pp. 314-323, 2000, IEEE Computer Society, 0-7695-0912-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
delay-sensitive scalable multimedia streams, network-level service, application level data streams, QoS management system, scaling properties, layered media streams, quality of service, quality of service, Internet, Internet, delays, multimedia communication, multimedia applications, Differentiated Services, DiffServ, real-time communication, computer network management, multimedia servers, multimedia servers, computer communication, network resources |
12 | Yutaka Ishibashi, Shuji Tasaka |
A Comparative Survey of Sychronization Algorithms for Continuous Media in Network Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: Proceedings 27th Conference on Local Computer Networks, Tampa, Florida, USA, 8-10 November, 2000, pp. 337-348, 2000, IEEE Computer Society, 0-7695-0912-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
comparative survey, media synchronization control techniques, basic control, preventive control, common control, network delay bounds, delays, multimedia systems, synchronisation, clocks, clocks, reviews, continuous media, telecommunication networks, algorithm design, telecommunication control, network environments, synchronization algorithms, reactive control |
12 | King-Shan Lui, Klara Nahrstedt, Shigang Chen |
Hierarchical QoS Routing in Delay-Bandwidth Sensitive Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: Proceedings 27th Conference on Local Computer Networks, Tampa, Florida, USA, 8-10 November, 2000, pp. 579-588, 2000, IEEE Computer Society, 0-7695-0912-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
hierarchical QoS routing, delay-bandwidth sensitive networks, scaling problem, topology information, hierarchical routing protocols, QoS-aware topology aggregation, aggregated network state, end-to-end route, aggregated information, network QoS representation, distributed routing mechanism, quality of service, delays, network topology, simulation results, telecommunication network routing, line segments, network nodes, topology aggregation, routing performance |
12 | Jorge Arellano-Cid, Horst H. von Brand |
Network Programming Internals of the Dillo Web Browser. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCCC ![In: 20st International Conference of the Chilean Computer Science Society (SCCC 2000), 16-18 November 2000, Santiago, Chile, pp. 178-182, 2000, IEEE Computer Society, 0-7695-0810-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Dillo, delay sources, signal driven input output, nonblocking main thread, overlapping waiting times, Internet, delays, programming, threads, Web browser, multi-threading, network programming, input-output programs, online front-ends |
12 | Michael Dahlin |
Interpreting Stale Load Information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS ![In: Proceedings of the 19th International Conference on Distributed Computing Systems, Austin, TX, USA, May 31 - June 4, 1999, pp. 285-296, 1999, IEEE Computer Society, 0-7695-0222-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
load interpretation, distributed systems, load balancing, queueing models, communication delays |
12 | Abdel Krim Amoura, Evripidis Bampis, Jean-Claude König |
Scheduling Algorithms for Parallel Gaussian Elimination With Communication Costs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 9(7), pp. 679-686, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Gaussian elimination method, scheduling, partitioning, mapping, Distributed architectures, communication delays |
12 | Guy E. Blelloch, Phillip B. Gibbons, Yossi Matias, Marco Zagha |
Accounting for Memory Bank Contention and Delay in High-Bandwidth Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 8(9), pp. 943-958, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Memory bank contention, memory delays, parallel machine models, parallel algorithms, performance analysis, multiprocessors, shared memory |
12 | Xiaohua Jia, Niki Pissinou, Kia Makki |
A distributed algorithm of delay bounded multicast routing for multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: Proceedings of the International Conference On Computer Communications and Networks (ICCCN 1997), September 22-25, 1997 Las Vegas, NV, USA, pp. 208-213, 1997, IEEE Computer Society, 0-8186-8186-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
delay bounded multicast routing, source node, multicast destinations, distributed heuristic algorithm, sub-optimal network cost, delay bound constraint, multicast membership changes, simulations, delays, multimedia applications, routing trees |
12 | Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch |
An optimized BIST test pattern generator for delay testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 94-100, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
BIST test pattern generator, robust delay fault coverage, single input change test sequence, compatible inputs, optimization, delays, built-in self-test, fault detection, delay testing, test length, area overhead, circuit under test |
12 | Jong Kim 0001, Kang G. Shin |
Execution Time Analysis of Communicating Tasks in Distributed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(5), pp. 572-579, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Task-execution time, communication and synchronization delays, distributed systems, queuing analysis |
12 | Byungho Kim, Boseob Kwon, Hyunsoo Yoon, Seungryul Maeng, Jung Wan Cho |
Performance Analysis of Multipath Multistage Interconnection Networks with Nonuniform Output Traffic Distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), January 24-26, 1996, Portugal, pp. 196-203, 1996, IEEE Computer Society, 0-8186-7376-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
buffer circuits, multipath multistage interconnection networks, nonuniform output traffic distribution, delay-throughput performance, packet arrival rates, output module., performance evaluation, performance analysis, delays, probability, packet switching, multistage interconnection networks, telecommunication traffic, packet delay, losses, output buffers, packet loss probability |
12 | Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal |
Segment delay faults: a new fault model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 32-41, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
segment delay faults, delay defect, distributed defect, rising transitions, falling transitions, transition tests, nonrobust tests, VLSI, fault diagnosis, logic testing, delays, integrated circuit testing, fault model, automatic testing, circuit analysis computing, robust tests, integrated circuit modelling, production testing, spot defect, manufacturing defects |
12 | S. Crepaux-Motte, Mireille Jacomino, Rene David |
An algebraic method for delay fault testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 308-315, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
input values, output function, robustly testable fault, nonrobustly testable fault, weakly verifiable, fault diagnosis, logic testing, delays, timing, Markov processes, random testing, delay fault testing, state transition, input vectors, algebraic method |
12 | S. Cremoux, Christophe Fagot, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch |
A new test pattern generation method for delay fault testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 296-301, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
test pattern generation method, directed random generation technique, random test vectors, test sequence length, delay fault coverage, learning (artificial intelligence), VLSI, logic testing, delays, built-in self test, integrated circuit testing, BIST, automatic testing, delay fault testing, digital integrated circuits, learning tool, high speed circuits |
12 | Mukund Sivaraman, Andrzej J. Strojwas |
A diagnosability metric for parametric path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 316-323, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
diagnosability metric, parametric path delay faults, test vector pairs, chip failure, fabrication process parameter variations, diagnosis framework, ISCAS'89 benchmark circuits, VLSI, fault diagnosis, logic testing, delays, timing, integrated circuit testing, failure analysis, diagnosability, delay fault testing, test set |
12 | Prasanti Uppaluri, Uwe Sparmann, Irith Pomeranz |
On minimizing the number of test points needed to achieve complete robust path delay fault testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 288-295, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
robust path delay fault testability, RD fault identification, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuit, test point insertion |
12 | Yuyun Liao, D. M. H. Walker |
Optimal voltage testing for physically-based faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 344-353, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise |
12 | Valery A. Vardanian |
On completely robust path delay fault testable realization of logic functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 302-307, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
robust path delay fault testable realization, two-level completely RPDFT realization, RPDFT-extension, input variables, VLSI, VLSI, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, integrated circuit testing, combinational circuits, combinational circuits, multivalued logic circuits, symmetric functions |
12 | Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal |
Improving accuracy in path delay fault coverage estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 422-425, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
fault coverage estimation, simulated vector pair, exact fault simulation, fixed-length path-segments, fan-in branches, fan-out branches, flagged path-segments, segment lengths, combinational paths, graph theory, fault diagnosis, logic testing, delays, combinational circuits, logic CAD, circuit analysis computing, path delay fault, approximate methods, CPU time |
12 | Prathima Agrawal, Balakrishnan Narendran, Narayanan Shivakumar |
Multi-way partitioning of VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 393-399, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multi-way partitioning, hierarchical design processes, nets cut metric, VLSI, delays, economics, logic CAD, VLSI layout, integrated circuit layout, VLSI circuits, logic partitioning, minimisation of switching nets, average delay, integrated circuit manufacture, cost metric |
12 | S. Ramanathan, V. Visvanathan |
A systolic architecture for LMS adaptive filtering with minimal adaptation delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 286-289, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
LMS adaptive filtering, minimal adaptation delay, convergence behaviour, function preserving transformations, SFG representation, carry-save arithmetic, systolic folded pipelined architecture, VLSI, delays, systolic arrays, pipeline processing, adaptive filters, digital filters, digital signal processing chips, convergence of numerical methods, systolic architecture, signal flow graphs, signal flow graph, least mean squares methods, LMS algorithm |
12 | Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal |
Parallel concurrent path-delay fault simulation using single-input change patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 426-431, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
concurrent path-delay fault simulation, single-input change patterns, singly-testable path-delay faults, random values, rising transitions, falling transitions, sixteen-valued algebra, machine word parallelism, ISCAS '85 benchmarks, ISCAS '89 benchmarks, parallel algorithms, fault diagnosis, logic testing, delays, Boolean functions, sequential circuits, logic CAD, circuit analysis computing, flip-flops, Boolean operations |
12 | G. Enrique Fernandez, R. Sridhar |
Dual rail static CMOS architecture for wave pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 335-336, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
dual rail static CMOS architecture, gate capacitance, storage elements, DRSCMOS, multi-functional basic building blocks, combinational logic block, delays, timing, throughput, combinational circuits, power consumption, pipeline processing, CMOS logic circuits, digital systems, capacitance, wave pipelining, delay variations |
12 | Mukund Sivaraman, Andrzej J. Strojwas |
Diagnosis of parametric path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 412-417, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
parametric path delay faults, chip failure, fabrication process parameter values, path sensitization mechanism, path delay conditions, ISCAS'89 benchmark circuits, path segment, circuit failure, fault diagnosis, logic testing, logic testing, delays, probability, probability, statistical analysis, statistical analysis, integrated circuit testing, failure analysis, diagnosability, delay fault testing, IC testing, production testing |
12 | Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal |
On test coverage of path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 418-421, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
two-pass test generation method, falling transition, line delay test, longest sensitizable path, decreasing length, redundant stuck-at fault, computational complexity, fault diagnosis, logic testing, delays, redundancy, combinational circuits, fault simulation, circuit analysis computing, test coverage, path delay faults, benchmark circuits, coverage metric, combinational logic circuits, longest paths |
12 | Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas |
Statistical path delay fault coverage estimation for synchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 290-295, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
path delay fault coverage estimation, multi-valued algebra, signal statistics, latch updating, fault diagnosis, logic testing, delays, probability, controllability, controllability, statistical analysis, sequential circuits, observability, observabilities, logic simulation, synchronous sequential circuits, statistical estimation |
12 | Nuno Vasconcelos, Andrew Lippman |
Spatiotemporal model-based optic flow estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP ![In: Proceedings 1995 International Conference on Image Processing, Washington, DC, USA, October 23-26, 1995, pp. 201-204, 1995, IEEE Computer Society, 0-8186-7310-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
spatiotemporal model based estimation, spatiotemporal model based algorithm, spatiotemporal motion model, quadratic constraint, affine constraint, space constraint, delayed decision process, classification, motion estimation, delays, interpolation, interpolation, data compression, image sequences, parameter estimation, video coding, video stream, image classification, time constraint, video compression, least squares approximations, correlation methods, temporal coherence, least squares fit, video frames, image correlation, optic flow estimation, interactive access |
12 | Baruch Awerbuch, Yossi Azar, Edward F. Grove, Ming-Yang Kao, P. Krishnan, Jeffrey Scott Vitter |
Load Balancing in the Lp Norm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 36th Annual Symposium on Foundations of Computer Science, Milwaukee, Wisconsin, USA, 23-25 October 1995, pp. 383-391, 1995, IEEE Computer Society, 0-8186-7183-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
L/sub p/ norm, job assignment, L/sub /spl infin// norm, maximum load, greedy load balancing algorithm, offline optimal, average job delay, sum of the squares, load balancing, resource allocation, delays, queueing theory, deterministic algorithms, deterministic algorithm, competitive algorithms, competitive algorithms, online operation, online operation, Euclidean norm |
12 | Meng-Lieh Sheu, Chung-Len Lee 0001 |
A programmable multiple-sequence generator for BIST applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 279-285, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
programmable multiple-sequence generator, BIST applications, two-dimension-like feedback shift register, deterministic sequence, pseudo-random vectors, sequence segmentation method, stuck-open fault testing, logic testing, delays, built-in self test, sequential circuits, shift registers, delay fault testing, binary sequences, sequential circuit testing, regular structure, MCM testing |
12 | Branka Medved Rogina, Bozidar Vojnovic |
Metastability evaluation method by propagation delay distribution measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 40-44, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
propagation delay distribution measurement, edge-triggered flip-flops, input signals time relationship, output signal timing characteristics, analytical representation, propagation delay density distribution function, fault events, integrated propagation delay density distribution function, flip-flop normal propagation delay, resolution time constant, automatic data acquisition, complex architecture microsystems, MTBF, latch devices, custom CMOS, VLSI, VLSI, fault diagnosis, logic testing, delays, logic design, asynchronous circuits, flip-flops, data acquisition, failure analysis, reliability analysis, graphical representation, metastability, PLD, asynchronous logic, integrated circuit reliability, statistical measurement |
12 | Jason P. Hurst, Nick Kanopoulos |
Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 346-352, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
flip-flop sharing, standard scan path, standard scan path design, two-vector test sets, VLSI, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, sequential circuits, flip-flops, integrated logic circuits, sequential machines, delay fault testing |
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