Search results for "VLSI"

Hits ?▲	Authors	Title	Venue	Year	Link
25	Wenao Xie, Haoyang Sang, Beomseok Kwon, Dongseok Im, Sangjin Kim, Sangyeob Kim, Hoi-Jun Yoo	A 709.3 TOPS/W Event-Driven Smart Vision SoC with High-Linearity and Reconfigurable MRAM PIM.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Hiroaki Arimura, S. Brus, Jacopo Franco, Y. Oniki, A. Vandooren, T. Conard, B. T. Chan, B. Kannan, M. Samiee, W. Li, P. Deminskyi, E. Shero, J. Bakke, N. Jourdan, G. Alessio Verni, J. W. Maes, M. Givens, Lars-Åke Ragnarsson, Jérôme Mitard, E. Dentoni Litta, N. Horiguchi	Molybdenum Nitride as a Scalable and Thermally Stable pWFM for CFET.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yutaro Fujisaki, Hidenobu Tsugawa, K. Sakai, H. Kumagai, R. Nakamura, Tomoharu Ogita, S. Endo, T. Iwase, H. Takase, K. Yokochi, S. Yoshida, S. Shimada, Y. Otake, T. Wakano, H. Hiyama, K. Hagiwara, M. Arakawal, S. Matsumotol, H. Maeda, K. Sugihara, K. Takabayashi, M. Ono, K. Ishibashi, K. Yamamoto	A back-illuminated 6 μm SPAD depth sensor with PDE 36.5% at 940 nm via combination of dual diffraction structure and 2×2 on-chip lens.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Sigang Ryu, Adou Sangbone Assoa, Shota Konno, Arijit Raychowdhury	A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Yun Zhou, Ivan Ciofi, Anne Jourdain, A. Veloso, Michele Stucchi, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert	Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Kai Xu, Bowen Yu, Jun Hu, Yubin Li, Robert Bogdan Staszewski, Hongtao Xu	A 50μW Ring-Type Complementary Inverse-Class-D Oscillator with 191.4dBc/Hz FoM and 205.6dBc/Hz FoMA.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	S. Yang, Pieter Schuddinck, Marie Garcia Bardon, Yang Xiang, Anabela Veloso, B. T. Chan, Gioele Mirabelli, Gaspard Hiblot, Geert Hellings, Julien Ryckaert	PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Junghyeon Hwang, Chaeheon Kim, Hunbeom Shin, Hwayoung Kim, Sang-Hee Ko Park, Sanghun Jeon	Ultra-high Tunneling Electroresistance Ratio (2 × 104) & Endurance (108) in Oxide Semiconductor-Hafnia Self-rectifying (1.5 × 103) Ferroelectric Tunnel Junction.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Hans Mertens, M. Hosseini, Thomas Chiarella, D. Zhou, S. Wang, G. Mannaert, E. Dupuy, D. Radisic, Z. Tao, Y. Oniki, Andriy Hikavyy, R. Rosseel, A. Mingardi, S. Choudhury, P. Puttarame Gowda, F. Sebaai, A. Peter, Kevin Vandersmissen, J. P. Soulie, An De Keersgieter, L. Petersen Barbosa Lima, C. Cavalcante, D. Batuk, G. T. Martinez, J. Geypen, F. Seidel, K. Paulussen, P. Favia, Jürgen Bömmels, Roger Loo, P. Wong, A. Sepulveda Marquez, B. T. Chan, Jérôme Mitard, S. Subramanian, S. Demuynck, E. Dentoni Litta, N. Horiguchi, S. Samavedam, S. Biesemans	Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	P. Guo, Zu-Yao Chang, Emile Noothout, Hendrik J. Vos, Johannes G. Bosch, Nico de Jong, Martin D. Verweij, Michiel A. P. Pertijs	A Pitch-Matched Transceiver ASIC for 3D Ultrasonography with Micro-Beamforming ADCs based on Passive Boxcar Integration and a Multi-Level Datalink.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Chun Wang, Ibrahim Abdo, Chenxin Liu, Carrel da Gomez, Hans Herdian, Wenqian Wang, Xi Fu, Dongwon You, Abanob Shehata, Sunghwan Park, Yun Wang 0008, Jian Pang, Hiroyuki Sakai 0009, Atsushi Shirane, Kenichi Okada	A Sub-THz Full-Duplex Phased-Array Transceiver with Self-Interference Cancellation and LO Feedthrough Suppression.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Luong Hung, Koji Matsuura, Hiroki Suto, Kazutoshi Kodama, Yosuke Tanaka, Toshiaki Ono, Junichiro Fujimagari, Kentaro Akiyama, Miho Akahide, Yoshiaki Inada	An 0.08 e-. pJ/step 14-bit gain-adaptive single-slope column ADC with enhanced HDR function for high-quality imagers.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yang Wang, Yubin Qin, Dazheng Deng, Xiaolong Yang, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Leibo Liu, Shaojun Wei, Yang Hu 0001, Shouyi Yin	A 28nm 77.35TOPS/W Similar Vectors Traceable Transformer Processor with Principal-Component-Prior Speculating and Dynamic Bit-wise Stationary Computing.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Song-Hyeon Kuk, Jae-Hoon Han, Bong Ho Kim, Joon Pyo Kim, Sang-Hyeon Kim	Strategy for 3D Ferroelectric Transistor: Critical Surface Orientation Dependence of HfZrOx on Si.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jinshan Yue, Mingtao Zhan, Zi Wang, Yifan He, Yaolei Li, Songming Yu, Wenyu Sun, Lu Jie 0008, Chunmeng Dou, Xueqing Li, Nan Sun 0001, Huazhong Yang, Ming Liu 0022, Yongpan Liu	A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Kasidit Toprasertpong, Shuhan Liu, Jian Chen, Sumaiya Wahid, Koustav Jana, Wei-Chen Chen, Shengman Li, Eric Pop, H.-S. Philip Wong	Co-designed Capacitive Coupling-Immune Sensing Scheme for Indium-Tin-Oxide (ITO) 2T Gain Cell Operating at Positive Voltage Below 2 V.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Tiancheng Gong, Lihua Xu, Wei Wei, Pengfei Jiang, Peng Yuan, Bowen Nie, Yuanquan Huang, Yuan Wang, Yang Yang, Jianfeng Gao 0005, Junfeng Li, Jun Luo, Lingfei Wang, Jianguo Yang, Qing Luo, Ling Li, Steve S. Chung, Ming Liu	First Demonstration of a Design Methodology for Highly Reliable Operation at High Temperature on 128kb 1T1C FeRAM Chip.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yiwei Du, Jianshi Tang, Yijun Li, Yue Xi, Bin Gao 0006, He Qian, Huaqiang Wu	Monolithic 3D Integration of FeFET, Hybrid CMOS Logic and Analog RRAM Array for Energy-Efficient Reconfigurable Computing-In-Memory Architecture.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Souvik Ghosh 0001, Quentin Smets, S. Banerjee, Tom Schram, K. Kennes, R. Verheyen, P. Kumar, M.-E. Boulon, Benjamin Groven, H. M. Silva, S. Kundu, Daire Cott, Dennis Lin, P. Favia, T. Nuytten, A. Phommahaxay, Inge Asselberghs, C. De La Rosa, Gouri Sankar Kar, Steven Brems	Integration of epitaxial monolayer MX₂ channels on 300mm wafers via Collective-Die-To-Wafer (CoD2W) transfer.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Victor Moroz, Alexei Svizhenko, Munkang Choi, Plamen Asenov, Jaehyun Lee	Exploring Power Savings of Gate-All-Around Cryogenic Technology.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jeongwon Choe, Youngjoo Lee	A 2.35 Gb/s/mm2 (7440, 6696) NB-LDPC Decoder over GF(32) using Memory-Reduced Column-Wise Trellis Min-Max Algorithm in 28nm CMOS Technology.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Ankur Agrawal, Monodeep Kar, Kyu-Hyoun Kim, Sergey V. Rylov, Jinwook Jung, Seiji Munetoh, Kohji Hosokawa, Xin Zhang, Bahman Hekmatshoartabari, Fabio Carta, Martin Cochet, Robert Casatuta, Mingu Kang, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang	A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Seungyoung Lee, Sungyup Jung, Yunkyeong Jang, Jungho Do, Jisu Yu, Hyeoungyu You, Minjae Jeong, Jinyoung Lim, Jiyun Han, Sangdo Park, Yongdeok Kim, Jooyeon Kwon, Hoonki Kim, Seiseung Yoon	Breakthrough Design Technology Co-optimization using BSPDN and Standard Cell Variants for Maximizing Block-level PPA.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Dongwan Ha, Ruida Yun, Kevin R. Wrenner	A 0.22mm2 per Channel Data Link for Reinforced Isolation with >25kVpk Surge Tolerance and >295kV/μs Common Mode Transient Immunity.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Kyu-Jin Choi, Seungnam Choi, Jae-Yoon Sim	A 110dB-TCMRR TDM-based 8-Channel Noncontact ECG Recording IC with Suppression of Motion-Induced Coupling in PP.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	N. Jungmann, R. Joshi, E. Kachir, K. Shimanovich, B. He, T. Cohen, T. Miller, D. Leu, Dinesh Kannambadi, I. Wagner, Kenneth Reyer, H. Konen, M. Suleiman, V. Sindhe, Y. Freiman	A 1.9GHz 0.57V Vmin 576Kb embedded product-ready L2 cache in 5nm FinFET technology.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yao-Hung Huang, Yu-Cheng Hsieh, Yu-Cheng Lin, Yue-Der Chih, Eric Wang, Jonathan Chang, Ya-Chin King, Chrong Jung Lin	High Density Embedded 3D Stackable Via RRAM in Advanced MCU Applications.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Joydeep Basu, Luigi Fassio, Karim Ali 0007, Massimo Alioto	Super-Cutoff Analog Building Blocks for pW/Stage Operation and Demonstration of 78-pW Battery-Less Light-Harvested Wake-Up Receiver down to Moonlight.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Mauro J. Kobrinsky, J. D. Silva, E. Mannebach, S. Mills, M. Abd El Qader, O. Adebayo, N. Arkali Radhakrishna, M. Beasley, J. Chawla, S. Chugh, A. Dasgupta, U. Desai, E. De Re, G. Dewey, T. Edwards, C. Engel, V. Gudmundsson, Jeffery Hicks, B. Krist, R. Mehandru, Inanc Meric, Patrick Morrow, D. Nandi, P. Patel, R. Ramamurthy, D. Samanta, L. Shoer, A. St Amour, L. H. Tan, Sukru Yemenicioglu, X. Wang, T. Ghani	Novel Cell Architectures with Back-side Transistor Contacts for Scaling and Performance.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Zuopu Zhou, Leming Jiao, Qiwen Kong, Zijie Zheng, Kaizhen Han, Yue Chen, Chen Sun 0010, Bich-Yen Nguyen, Xiao Gong	Non-Destructive-Read 1T1C Ferroelectric Capacitive Memory Cell with BEOL 3D Monolithically Integrated IGZO Access Transistor for 4F2 High-Density Integration.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Mohamed Badr Younis, Mostafa Gamal Ahmed, Tianyu Wang 0006, Ahmed E. AbdelRahman, Mahmoud A. Khalil, Anup P. Jose, Pavan Kumar Hanumolu	A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Kanguk Kim, Youngwoo Son, Hoin Ryu, Byunghyun Lee, Jooncheol Kim, Hyunsu Shin, Joonyoung Kang, Jihun Kim, Shinwoo Jeong, Kyosuk Chae, Dongkak Lee, Ilwoo Jung, Yongkwan Kim, Boyoung Song, Jeonghoon Oh, Jungwoo Song, Seguen Park, Keumjoo Lee, Hyodong Ban, Jiyoung Kim, Jooyoung Lee	14nm DRAM Development and Manufacturing.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Siva Sivaram, Alper Ilkbahar	Searching for Nonlinearity: Scaling Limits in NAND Flash.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Wei Tang 0010, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Kale, Mark Flannigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang	Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yu-Rui Chen, Yi-Chun Liu, Zefu Zhao, Wan-Hsuan Hsieh, Jia-Yang Lee, Chien-Te Tu, Bo-Wei Huang, Jer-Fu Wang, Shee-Jier Chueh, Yifan Xing, Guan-Hua Chen, Hung-Chun Chou, Dong Soo Woo, Min-Hung Lee, Chee Wee Liu	First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Changhwan Lee, Min-Tai Yu, Sejun Park, Hoki Lee, Bio Kim, Suhwan Lim, Jaeduk Lee, Sung-Hun Lee, Mincheol Park, Sujin Ahn, Sunghoi Hur	Novel Strategies for Highly Uniform and Reliable Cell Characteristics of 8th Generation 1Tb 3D-NAND Flash Memory.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Luigi Fassio, Orazio Aiello, Massimo Alioto	38.4-pW, 0.14-mm2 Body-Driven Temperature-to-Digital Converter and Voltage Reference with 0.6-1.6-V Unregulated Supply for Battery-Less Systems.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Y. Kwon, Y. Kwak, Y. Choi, K. Kim, S. Kim, W. Jang, J. Park, K. Ryu, S. Yoo, H. W. Lim, J. Y. Lee	A 16-channel Active-Matrix Mini-LED Driver with an USI-B for EMI noise reduction.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Li-Chen Wang, W. Li, Nirmaan Shanker, Suraj S. Cheema, Shang-Lin Hsu, S. Volkman, U. Sikder, C. Garg, J.-H. Park, Y.-H. Liao, Yen-Kai Lin, Chenming Hu, Sayeef S. Salahuddin	Record Transconductance in Leff~30 nm Self-Aligned Replacement Gate ETSOI nFETs Using Low EOT Negative Capacitance HfO2-ZrO2 Superlattice Gate Stack.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jih-Chao Chiu, Eknath Sarkar, Yuan-Ming Liu, Yu-Ciao Chen, Yu-Cheng Fan, C. W. Liu	First Demonstration of a-IGZO GAA Nanosheet FETs Featuring Achievable SS=61mV/dec, Ioff<10-7 μA/μm, DIBL =44mV/V, Positive VT, and Process Temp. of 300 °C.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Benjamin R. Moss, Christopher V. Poulton, Matthew J. Byrd, Peter Russo, Oleg Shatrovoy, David Paquette, Andrew Reardon, Michael R. Watts	A 2048-channel, 125μW/ch DAC Controlling a 9, 216-element Optical Phased Array Coherent Solid-State LiDAR.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Fan-Wei Liao, Shan-Chih Tsou, Chien-Sheng Chao	A 6nW 30.8kHz Relaxation Oscillator with Sampling Bias-Free RC Circuit and Dynamic Power Scaling in a 12nm FinFET.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Shiro Dosho, Ludovico Minati, Kazuki Maari, Hiroyuki Ito	A Compact 0.9uW Direct-Conversion Frequency Analyzer for Speech Recognition with Wide-Range Q-Controlable Bandpass Rectifier.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Luca Ricci, Lorenzo Scaletti, Gabriele Bè, Michele Rocco, Luca Bertulessi, Salvatore Levantino, Andrea L. Lacaita, Carlo Samori, Andrea Bonfanti	A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	J.-H. Yoo, H.-B. Jo, I.-G. Lee, S.-M. Choi, J.-M. Baek, S. T. Lee, H. Jang, M. W. Kong, H. H. Kim, H. J. Lee, H.-J. Kim, H.-S. Jeong, W.-S. Park, D.-H. Ko, S. H. Shin, H.-M. Kwon, S. K. Kim, J. G. Kim, J. Yun, T. Kim, K.-Y. Shin, T.-W. Kim, J.-K. Shin, J.-H. Lee, C.-S. Shin, K.-S. Seo, Dae-Hyun Kim	Lg = 60 nm In0.53 Ga0.47 As MBCFETs: From gm_max = 13.7 mS/üm and Q = 180 to virtual-source modeling.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Zuoyuan Dong, Zixuan Sun, Xin Yang, Xiaomei Li, Yongkang Xue, Chen Luo, Puyang Cai, Zirui Wang, Shuying Wang, Yewei Zhang, Chaolun Wang, Pengpeng Ren, Zhigang Ji, Xing Wu 0005, Runsheng Wang, Ru Huang	Catching the Missing EM Consequence in Soft Breakdown Reliability in Advanced FinFETs: Impacts of Self-heating, On-State TDDB, and Layout Dependence.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Aoyang Zhang, Daniel Krüger, Behdad Aghelnejad, Guang Yang, Henry Hinton, Yi-Qiao Song, Donhee Ham	A Wideband CMOS NMR Spectrometer for Multinuclear Molecular Fingerprinting.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	E. R. Hsieh, Y. T. Tang, C. R. Liu, S. M. Wang, Y. L. Hsueh, R. Q. Lin, Y. X. Huang, Y. T. Chen	3-bits-per-cell 2T32CFE nvTCAM by Angstrom-laminated Ferroelectric Layers with 10¹¹ Cycles of Endurance and 4.92V of Ultra-wide Memory-windows for In-memory-searching.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Nanyu Zeng, Taesung Jung, Mohit Sharma, Guy Eichler, Jason D. Fabbri, R. James Cotton, Eleonora Spinazzi, Brett Youngerman, Luca P. Carloni, Kenneth L. Shepard	A Wireless, Mechanically Flexible, 25μm-Thick, 65, 536-Channel Subdural Surface Recording and Stimulating Microelectrode Array with Integrated Antennas.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Seunghwa Shin, Gyeong-Gu Kang, Gyu-Wan Lim, Hyun-Sik Kim	A Mobile OLED Source-Driver IC featuring Ultra-Compact 3-Stage-Cascaded 10-Bit DAC and 42V/μs-Slew-Rate True-DC-Interpolative Super-OTA Buffer.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yan-Ting Hsiao, Shu-Yan Chuang, Hung-Yu Hou, Yun-Chun Su, Hsiu-Cheng Yeh, Hsin-Tzu Song, Yun-Jui Chang, Wei-Yang Weng, Ya-Chen Tsai, Pin-Yu Lin, Sih-Ying Chen, Yen-Ju Lin, Mei-Wei Lin, Jun-Chau Chien	A CMOS/Microfluidics Point-of-Care SoC employing Square-Wave Voltcoulometry for Biosensing with Aptamers and CRISPR-Cas12a Enzymes.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jacopo Franco, Hiroaki Arimura, J.-F. de Marneffe, S. Brus, Romain Ritzenthaler, E. Dentoni Litta, Kris Croes, Ben Kaczer, N. Horiguchi	Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho, Kimiyoshi Usami, Taku Umebayashi	A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Milad Haghi Kashani, Hossein Shakiba, Ali Sheikholeslami	A 0.32pJ/b 90Gbps PAM4 Optical Receiver Front-End with Automatic Gain Control in 12nm CMOS FinFET.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jung-Hoon Kim, Jaehoon Heo, Wontak Han, Jaeuk Kim, Joo-Young Kim 0001	SP-PIM: A 22.41TFLOPS/W, 8.81Epochs/Sec Super-Pipelined Processing-In-Memory Accelerator with Local Error Prediction for On-Device Learning.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Zijie Zheng, Leming Jiao, Zuopu Zhou, Yuxuan Wang, Long Liu, Kaizhen Han, Chen Sun 0010, Qiwen Kong, Dong Zhang, Xiaolin Wang, Kai Ni, Xiao Gong	First Demonstration of Work Function-Engineered BEOL-Compatible IGZO Non-Volatile MFMIS AFeFETs and Their Co-Integration with Volatile-AFeFETs.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Takashi Oshima, Keisuke Yamamoto, Goichi Ono	A 0.75V 0.016mm2 12ENOB 7nm CMOS cyclic ADC with 1.5bit passive amplification stage and dynamic capacitance scaling.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Geoffrey W. Burr, Pritish Narayanan, Stefano Ambrogio, Atsuya Okazaki, Hsinyu Tsai, Kohji Hosokawa, Charles Mackin, Akiyo Nomura, Takeo Yasuda, J. Demarest, Kevin Brew, Victor Chan, Samuel Choi, T. Gordon, T. M. Levin, Alexander M. Friz, Masatoshi Ishii, Yasuteru Kohda, An Chen, Andrea Fasoli, Jose Luquin, Nicole Saulnier, S. Teehan, Ishtiaq Ahsan, Vijay Narayanan	Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited).	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Ming-Hung Wu, Ming-Chun Hong, Ching Shih, Yao-Jen Chang, Yu-Chen Hsin, Shih-Ching Chiu, Kuan-Ming Chen, Yi-Hui Su, Chih-Yao Wang, Shan-Yi Yang, Guan-Long Chen, Hsin-Han Lee, Sk. Ziaur Rahaman, I-Jung Wang, Chen-Yi Shih, Tsun-Chun Chang, Jeng-Hua Wei, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Tuo-Hung Hou	U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	H.-L. Chiang, R. A. Hadi, J.-F. Wang, H.-C. Han, J.-J. Wu, H.-H. Hsieh, J.-J. Horng, W.-S. Chou, B.-S. Lien, C.-H. Chang, Y.-C. Chen, Yeong-Her Wang, T.-C. Chen, J.-C. Liu, Y.-C. Liu, Meng-Hsueh Chiang, K.-H. Kao, B. Pulicherla, J. Cai, C.-S. Chang, K.-W. Su, K.-L. Cheng, T.-J. Yeh, Y.-C. Peng, C. Enz, Mau-Chung Frank Chang, M.-F. Chang, H.-S. Philip Wong, Iuliana P. Radu	How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	C. A. Lu, H. P. Lee, H. C. Chen, Y. C. Lin, Y. H. Chung, S. H. Wang, J. Y. Yeh, V. S. Chang, M. C. Chiang, W. Chang, H. C. Chung, C. F. Cheng, H. H. Hsu, H. H. Liu, William P. N. Chen, C. Y. Lin	Characterizing and Reducing the Layout Dependent Effect and Gate Resistance to Enable Multiple-Vt Scaling for a 3nm CMOS Technology.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Sanghyun Ban, Jangseop Lee, Taehoon Kim, Hyunsang Hwang	Simple Binary In-Te OTS with Sub-nm HfOₓ Buffer Layer for 3D Vertical X-point Memory Applications.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yan He 0002, Kaiyuan Yang 0001	A Fully Synthesizable 100Mbps Edge-Chasing True Random Number Generator.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Zhe Xuan, Ganesh Balamurugan, Duanni Huang, Ranjeet Kumar, Jahnavi Sharma, Cooper Levy, Jinyong Kim, Chaoxuan Ma, Guan-Lin Su, Songtao Liu, Xinru Wu, Tolga Acikalin, Haisheng Rong, James E. Jaussi	A 256 Gbps Heterogeneously Integrated Silicon Photonic Microring-based DWDM Receiver Suitable for In-Package Optical I/O.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	S. Kundu, D. H. van Doip, Tom Schram, Quentin Smets, S. Banerjee, Benjamin Groven, Daire Cott, S. Decoster, P. Bezard, F. Lazzarino, K. Banerjee, Souvik Ghosh 0001, J. F. de Mamelfe, Pierre Morin, Cesar J. Lockhart de la Rosa, Inge Asselberghs, Gouri Sankar Kar	Towards low damage and fab-compatible top-contacts in MX2 transistors using a combined synchronous pulse atomic layer etch and wet-chemical etch approach.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Surya Bhattacharya, Vempati Srinivasa Rao	Multi-Chiplet Heterogeneous Integration Packaging for Semiconductor System Scaling.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jaeyun Yi, Myoungsub Kim, Jungwon Seo, Namkyun Park, Seungyun Lee, Jongil Kim, Gapsok Do, Hongjin Jang, Hyochol Koo, Sunglae Cho, Sujin Chae, Taehoon Kim, Myung-Hee Na, Seonyong Cha	The chalcogenide-based memory technology continues: beyond 20nm 4-deck 256Gb cross-point memory.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Dong Zhang, Jixuan Wu, Qiwen Kong, Zuopu Zhou, Long Liu, Kaizhen Han, Chen Sun 0010, Xiaolin Wang, Gan Liu, Leming Jiao, Zijie Zheng, Yuye Kang, Jiezhi Chen, Xiao Gong	Grain Size Reduction of Ferroelectric HZO Enabled by a Novel Solid Phase Epitaxy (SPE) Approach: Working Principle, Experimental Demonstration, and Theoretical Understanding.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Youngmin Jo, Anil Kavala, Tongsung Kim, Byung-Kwan Chun, Jungjune Park, Taesung Lee, Jungmin Seo, Manjae Yang, Taehyeon Park, Hyunjin Kwon, Cheolhui Lee, Younghoon Son, Junghwan Kwak, Younggyu Lee, Hwan-Seok Ku, Dae-Hoon Na, Changyeon Yu, Jonghoon Park, Jae-Hwan Kim, Hyojin Kwon, Chan-ho Kim, Moon-Ki Jung, Chanjin Park, Donghyun Seo, Moosung Kim, Seungjae Lee, Jin-Yub Lee, Dongku Kang, Chiweon Yoon, SungHoi Hur	A 3.0 Gb/s/pin 4th generation F-chip with Toggle 5.0 Specification for 16Tb NAND Flash Memory Multi chip Package.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Wei-Xiang You, Cheng-Yin Wang, Yih Wang, Tsung-Yung Jonathan Chang, Szuya Sandy Liao	Write-enhanced Single-ended 11T SRAM Enabling Single Bitcell Reconfigurable Compute-in-Memory Employing Complementary FETs.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yi Han, Jingxuan Sun, Jin Hee Bae, Detlev Grützmacher, Joachim Knoch, Qing-Tai Zhao	High Performance 5 nm Si Nanowire FETs with a Record Small SS = 2.3 mV/dec and High Transconductance at 5.5 K Enabled by Dopant Segregated Silicide Source/Drain.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	C. H. Naylor, Kirby Maxey, C. Jezewski, K. P. O'Brien, A. V. Penumatcha, M. S. Kavrik, B. Agrawal, C. V. Littlefield, J. Lux, B. Barley, Justin R. Weber, A. Sen Gupta, C. J. Dorow, N. Arefin, S. King, R. Chebiam, J. Plombon, S. B. Clendenning, U. E. Avci, Mauro J. Kobrinsky, M. Metz	2D Materials in the BEOL.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jun Yuan, Jie Deng, Vicki Lin, Ying Chen, Joseph Chiu, Minghuei Lin, Jun Chen, Deedee Zhang, Yukai Chen, David Liu, Bo Yu, Hao Wang, Giri Nallapati, Vivek Mohan, Venu Sanaka, Berkan Baran, Frank Dahan, Prasad Bhadri, Rajesh Geol, Venu Boynapalli, Seyfi Bazarjani, Paul Penzes, Parag Agashe, P. R. Chidambaram	High Performance 5G Mobile SOC Productization with 4nm EUV Fin-FET Technology.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yuhao Ju, Yijie Wei, Xi Chen, Jie Gu	A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Chan-Ho Lee, Hyo-Jin Park 0002, Joo-Mi Cho, Hyeon-Ji Choi, Young-Jun Jeon, Sung-Wan Hong	A 1V 20.7μW Four-Stage Amplifier Capable of Driving a 4-to-12nF Capacitive Load with >1.07MHz GBW with an Improved Active Zero.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yasunari Suzuki, Yosuke Ueno, Wang Liao, Masamitsu Tanaka, Teruo Tanimoto	Circuit designs for practical-scale fault-tolerant quantum computing.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Qiang Fang, Longyang Lin, Hui Zhang, Tianqi Wang, Massimo Alioto	Voltage Scaling-Agnostic Counteraction of Side-Channel Neural Net Reverse Engineering via Machine Learning Compensation and Multi-Level Shuffling.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yu-Cheng Lin, Chanmin Park, Wenda Zhao, Nan Sun 0001, Youngcheol Chae, Chia-Hsiang Yang	A 26.4mW, 18.6MS/s Image Reconstruction Processor for IoT Compressive Sensing.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Reza Mohammadi, Peter M. Levine, Karim S. Karim	A Monolithic Amorphous-Selenium/CMOS Small-Pixel-Effect-Enhanced X-Ray-Energy-Discriminating Quantum-Counting Pixel for Biomedical Imaging.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jaehong Jung, Kyungmin Lee, Gunwoo Kong, Baekmin Lim, Seungjin Kim, Seunghyun Oh, Jongwoo Lee	A 2.4-to-4.2GHz 440.2fsrms-Integrated-Jitter 4.3mW Ring-Oscillator-Based PLL Using a Switched-Capacitor-Bias-Based Sampling PD in 4nm FinFET CMOS.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Sein Oh, Seunga Park, Yoontae Jung, Jimin Koo, Donghee Cho, Sohmyung Ha, Minkyu Je	A 2.5mW 12MHz-BW 69dB SNDR Passive Bandpass ΔΣ ADC with Highpass Noise-Shaping SAR Quantizers.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Il-Min Yi, Srujan Kumar Kaile, Yuanming Zhu, Julian Camilo Gomez Diaz, Sebastian Hoyos, Samuel Palermo	A 50Gb/s DAC-Based Multicarrier Polar Transmitter in 22nm FinFET.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Qingyun Xie, Mengyang Yuan, John Niroula, Bejoy Sikder, Shisong Luo, Kai Fu, Nitul S. Rajput, Ayan Biswas Pranta, Pradyot Yadav, Yuji Zhao, Nadim Chowdhury, Tomás Palacios	Towards DTCO in High Temperature GaN-on-Si Technology: Arithmetic Logic Unit at 300 °C and CAD Framework up to 500 °C.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yi Zhu, Yuhan Hou, Jack Ji, Aaron Zhou, Andrew G. Richardson, Xilin Liu	A Wireless Sensor-Brain Interface System for Tracking and Guiding Animal Behaviors Through Goal-Directed Closed-loop Neuromodulation.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Xiongjie Zhang, Qiaobo Ma, Anyang Zhao, Yang Jiang 0002, Man-Kay Law, Pui-In Mak, Rui Paulo Martins	A 0.05-to-3.1A 585mA/mm3 97.3%-Efficiency Outphase Switched-Capacitor Hybrid Buck Converter with Relieved Capacitor Inrush Current and COUT-Free Operation.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yi Luo 0005, Shahriar Mirabbasi	A 60fps9.9nJ/frame·pixel CMOS Image Sensor with On-Chip Pixel-wise Conversion Gain Modulation for Per-frame Adaptive DCG-HDR Imaging.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Y. Kikuchi, M. Tomita, T. Hayashi, H. Chiba, T. Ogita, T. Okawa, K. Nishida, M. Sugimoto, D. Yoneyama, T. Umeki, H. Oishi, S. Miyake, K. Hiramatsu, H. Kumano, H. Kawashima, N. Yamada, M. Tamura, H. Ohnuma, K. Tatani	Noise Performance Improvements of 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Non-doped Pixel-FinFETs.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Animesh Gupta, Sayan Kumar, Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto	Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yaxin Ding, Jianguo Yang, Yu Liu, Jianfeng Gao 0005, Yuan Wang, Pengfei Jiang, Shuxian Lv, Yuting Chen, Boping Wang, Wei Wei, Tiancheng Gong, Kanhao Xue, Qing Luo, Xiangshui Miao, Ming Liu	16-layer 3D Vertical RRAM with Low Read Latency (18ns), High Nonlinearity (>5000) and Ultra-low Leakage Current (~pA) Self-Selective Cells.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	N. Grossier, Fabio Disegni, A. Ventre, A. Barcella, R. Mariani, V. Marino, S. Mazzara, A. Scavuzzo, M. Bansal, B. Soni, A. Anand, S. Banzal, D. Joshi, R. Narwal, M. Niranjani, K. Trivedi, P. Ferreira, Rossella Ranica, L. Vullo, Andreia Cathelin, Alfonso Maurelli, S. Pezzini, M. Peri	ASIL-D automotive-grade microcontroller in 28nm FD-SOI with full-OTA capable 21MB embedded PCM memory and highly scalable power management.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	A. Elsayed, Clement Godfrin, Nard I. Dumoulin Stuyck, M. M. K. Shehata, Stefan Kubicek, S. Massar, Yann Canvel, Julien Jussot, Andriy Hikavyy, Roger Loo, George Simion, Massimo Mongillo, D. Wan, Bogdan Govoreanu, R. Li, Iuliana P. Radu, P. Van Dorpe, Kristiaan De Greve	Comprehensive 300 mm process for Silicon spin qubits with modular integration.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	F. Huang, B. Saini, L. Wan, H. Lu, X. He, S. Qin, Wilman Tsai, A. Gruverman, Andrew C. Meng, H.-S. Philip Wong, Paul C. McIntyre, S. S. Wong	First Observation of Ultra-high Polarization (~ 108 μC/cm²) in Nanometer Scaled High Performance Ferroelectric HZO Capacitors with Mo Electrodes.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Kyungmoon Kim, Yujeong Seo, Sejun Park, Woojae Jang, Dongho Yoo, Joonsung Lim, Il-Han Park, Jaeduk Lee, Kyungyoon Noh, Sujin Ahn, Sunghoi Hur	High Bit Cost Scalability and Reliable Cell Characteristics for 7th Generation 1Tb 4Bit/Cell 3D-NAND Flash.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Yi-Chun Liu, Yu-Rui Chen, Yun-Wen Chen, Hsin-Cheng Lin, Wan-Hsuan Hsieh, Chien-Te Tu, Bo-Wei Huang, Wei-Jen Chen, Chun-Yi Cheng, Shee-Jier Chueh, Chee Wee Liu	Extremely High-κ Hf0.2Zr0.8O2 Gate Stacks Integrated into Ge0.95Si0.05 Nanowire and Nanosheet nFETs Featuring Respective Record Ion per Footprint of 9200μA/μm and Record Ion per Stack of 360μA at VOV=VDS=0.5V.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Mahdi Forghani, Yu Zhao, Pawan K. Khanna, Behzad Razavi	A 112-Gb/s 58-mW PAM4 Transmitter in 28-nm CMOS Technology.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Woojun Choi, Yiyang Chen, Donghwan Kim, Sean Weaver, Tilman Schlotter, Can Livanelioglu, Jiawei Liao, Rosario M. Incandela, Parham Davami, Gabriele Atzeni, Sina Arjmandpour, SeongHwan Cho, Taekwang Jang	A 1, 024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Dong Wang, Jiazheng Zhou, Hui Xu, Ningyuan Zhang, Xiaolei Su, Zhengkun Shen, Haoyun Jiang, Fan Yang 0077, Yixiao Wang, Junhua Liu, Huailin Liao	An All-Digital Outphasing Transmitter IC for Ka-Band Bit-to-RF Concurrent Multi-Beam DBF Array.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Sangjin Kim, Soyeon Um, Wooyoung Jo, Jingu Lee, Sangwoo Ha, Zhiyong Li, Hoi-Jun Yoo	Scaling-CIM: An eDRAM-based In-Memory-Computing Accelerator with Dynamic-Scaling ADC for SQNR-Boosting and Layer-wise Adaptive Bit-Truncation.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Sachin Taneja, Vikram B. Suresh, Raghavan Kumar, Vivek De, Sanu Mathew	218Kauth/s, 3nJ/auth SCA/ML-Resistant Privacy-Preserving Mutual Authentication Accelerator with a Crypto-Double-Coupled PUF in 4nm class CMOS.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Kaizhen Han, Yuye Kang, Yue Chen, Xiao Gong	Novel Bridge Transmission Line Method for Thin-Film Semiconductors: Modelling, Simulation Verification, and Experimental Demonstration.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF