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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 5686 publication records. Showing 5677 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
15 | Nicola Zingirian, Massimo Maresca |
Loop Regularization for Image and Video Processing on Instruction Level Parallel Architectures. |
CAMP |
2000 |
DBLP DOI BibTeX RDF |
loop regularization, instruction level parallel architectures, instruction reordering, image processing, embedded systems, embedded systems, video processing, digital signal processors, register renaming |
15 | Anne Canteaut, Eric Filiol |
Ciphertext Only Reconstruction of Stream Ciphers Based on Combination Generators. |
FSE |
2000 |
DBLP DOI BibTeX RDF |
ciphertext only reconstruction, Boolean function, stream cipher, correlation, linear feedback shift register |
15 | Eric Filiol |
Decimation Attack of Stream Ciphers. |
INDOCRYPT |
2000 |
DBLP DOI BibTeX RDF |
sequence decimation, multiple clocking, Stream cipher, linear feedback shift register, correlation attack, fast correlation attack |
15 | Ricardo Ferreira, Anne-Marie Trullemans, José C. Costa, José Monteiro 0001 |
Probabilistic Bottom-Up RTL Power Estimation. |
ISQED |
2000 |
DBLP DOI BibTeX RDF |
Register Tranfers Level, Power Estimation, Glitches, ZBDD |
15 | Ayoob E. Dooply, Kenneth Y. Yun |
Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines. |
ARVLSI |
1999 |
DBLP DOI BibTeX RDF |
Self-resetting domino, time borrowing, roadblock, skew tolerance design-for-testability, scan register, multiple stuck fault |
15 | Guido Araujo, Sharad Malik |
Code generation for fixed-point DSPs. |
ACM Trans. Design Autom. Electr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
scheduling, code generation, register allocation |
15 | Dusan Suvakovic, C. André T. Salama |
Guidelines for Use of Registers and Multiplexers in Low Power Low Voltage DSP Systems. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
low power, DSP, energy consumption, switching, multiplexer, low voltage, register, datapath |
15 | James J. Carrig Jr., Gerard G. L. Meyer |
Efficient Householder QR Factorization for Superscalar Processors. |
ACM Trans. Math. Softw. |
1997 |
DBLP DOI BibTeX RDF |
Householder QR factorization, register model, cache model |
15 | Yeong-Kang Lai, Liang-Gee Chen, Tsung-Han Tsai 0001, Po-Cheng Wu |
A Flexible High-Throughput VLSI Architecture with 2-D Data-Reuse for Full-Search Motion Estimation. |
ICIP (2) |
1997 |
DBLP DOI BibTeX RDF |
flexible high-throughput VLSI architecture, 2D data-reuse, full-search motion estimation, data-interlacing architecture, one-dimensional processing element array, data-interlacing shift-register arrays, external memory accesses, pin counts, search ranges, pixel rates, VLSI, block sizes, full-search block-matching algorithm |
15 | Gary S. Tyson, Todd M. Austin |
Improving the Accuracy and Performance of Memory Communication Through Renaming. |
MICRO |
1997 |
DBLP DOI BibTeX RDF |
data fetching, data value speculation, heap segment, instruction loading, memory access latency, memory communication, memory references, memory renaming, memory segments, processor pipeline, register access techniques, stores, performance, delays, accuracy, instruction-level parallelism, execution time, storage allocation, data dependence speculation, address calculation |
15 | Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic |
The Multicluster Architecture: Reducing Cycle Time Through Partitioning. |
MICRO |
1997 |
DBLP DOI BibTeX RDF |
partitioned architecture, static instruction scheduling, register allocation, decentralized architecture |
15 | Andrew Wolfe, Jason Fritts, Santanu Dutta, Edil S. T. Fernandes |
Datapath Design for a VLIW Video Signal Processor. |
HPCA |
1997 |
DBLP DOI BibTeX RDF |
datapath design, VLIW video signal processor, very long instruction word, high parallelism, high-level language programmability, high-bandwidth interconnect, high-connectivity register files, parameterizable versions, VLSI, video signal processing, VLIW architectures, compiler design |
15 | Aileen Cater-Steel, Edmond P. Fitzgerald |
Quality assurance certification: adoption by Australian software developers and its association with capability maturity. |
APSEC |
1997 |
DBLP DOI BibTeX RDF |
software quality assurance certification, Australian software developers, capability maturity, government purchasing policies, QA certification, JAS-ANZ register, organisational characteristics, software quality, survey, CMM, questionnaire, Australia, Hong Kong, research project, Singapore |
15 | Charles E. Molnar, Ian W. Jones, William S. Coates, Jon K. Lexau |
A FIFO Ring Performance Experiment. |
ASYNC |
1997 |
DBLP DOI BibTeX RDF |
FIFO ring performance experiment, high-speed FIFO circuit, asynchronous FIFO, clocked shift register, pulse-like protocol, two-phase clocked design, MOSIS, internal FIFO stages, 3.3 V, 1.67 to 4.8 V, 0.6 micron, pipeline, SPICE, data path, hSpice, circuit delays |
15 | Shu-Chin Su Chen, Ming-Feng Chang, Yi-Bing Lin |
Fault tolerance of PCS mobility databases. |
ICCCN |
1997 |
DBLP DOI BibTeX RDF |
PCS mobility databases, PCS network system, mobility management architecture, two-level database, mobile station location information, mobile station location update, call delivery procedure, location database failure, database failure restoration, fault tolerance, GSM, personal communication networks, personal communications services, mobile stations, home location register |
15 | Zdenek Kotásek, F. Zboril |
RT level testability analysis to reduce test application time. |
EUROMICRO |
1997 |
DBLP DOI BibTeX RDF |
register transfer level testability analysis, RTL element classification, RTL circuit transformation, labelled directed graph, PROLOG environment, implementation principles, logic testing, test application time reduction |
15 | Michael Weeks, M. B. Maaz, H. Krishnamurthy, Paul Shipley, Magdy A. Bayoumi |
A prototype chipset for a large scaleable ATM switching node. |
Great Lakes Symposium on VLSI |
1997 |
DBLP DOI BibTeX RDF |
prototype chipset, large scaleable ATM switching node, static logic, packet headers storage, dynamic logic, register file, CMOS digital integrated circuits, banyan network, CMOS IC, 1 micron |
15 | Andrzej Hlawiczka, Michael Gössel, Egor S. Sogomonyan |
A linear code-preserving signature analyzer COPMISR. |
VTS |
1997 |
DBLP DOI BibTeX RDF |
linear separable code, code preserving multi-input signature register, COPMISR, concurrent checking, parity code, group -parity code, BIST, linear codes, Hamming code, duplication code, XOR-gate, signature analyzer, on-line error detection |
15 | Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi |
Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling. |
VTS |
1997 |
DBLP DOI BibTeX RDF |
digital-compatible BIST scheme, pulse response sampling, low-cost BIST scheme, built-in self test scheme, rectangular pulses, digital linear feedback shift register, transient testing, synchronization circuitry, comparison circuitry, BIST hardware design, built-in self test, analog circuits |
15 | Joachim Althaler, Arne Dür |
Finite linear recurring sequences and homogeneous ideals. |
Appl. Algebra Eng. Commun. Comput. |
1996 |
DBLP DOI BibTeX RDF |
Linear Recurrence Relation, Annihilator Ideal, Inverse System, Shift Register Synthesis Problem, Berlekamp-Massey Algorithm |
15 | Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-Bin Liao |
Easily Testable Data Path Allocation Using Input/Output Registers. |
Asian Test Symposium |
1996 |
DBLP DOI BibTeX RDF |
testable data path allocation, behavioral synthesis systems, input/output registers, interconnection allocation, module allocation, higher fault coverage, lower hardware overhead, improved testability, VLSI synthesis, optimization, algorithms, benchmarks, ATPG, DFT, register allocation, circuit optimisation, RTL design |
15 | Min Xu, Fadi J. Kurdahi |
Layout-Driven RTL Binding Techniques for High-Level Synthesis. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
layout-driven register-transfer-level, binding techniques, chip level implementation, high level synthesis, high-level synthesis, design process |
15 | Amane Nakajima |
Fault-tolerant distributed match-making with weights. |
ICPADS |
1996 |
DBLP DOI BibTeX RDF |
distributed match-making, atomic shared register, cyclic communication structure, fault-tolerance, protocols, fault tolerant computing, distributed processing, mutual exclusion, weights, name service |
15 | Egor S. Sogomonyan, Michael Gössel |
Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
circuit feedback, concurrently self-testing embedded checker, ultra-reliable fault-tolerant system, parity codes, design, monitoring, built-in self test, integrated circuit testing, linear feedback shift register, error detection codes, error detection code, shift registers, arithmetic codes, Berger codes, duplication codes, integrated circuit reliability, corrector |
15 | Roger Espasa, Mateo Valero, David A. Padua, Marta Jiménez, Eduard Ayguadé |
Quantitative analysis of vector code. |
PDP |
1995 |
DBLP DOI BibTeX RDF |
Convex C3480, Perfect Club benchmarks, cost/performance tradeoffs, single bus memory architecture, slow-down, vector register, vector programs, performance evaluation, virtual machines, simulation study, vector processor systems, vector code |
15 | C. J. Elston, D. B. Christianson, Paul A. Findlay, Gordon B. Steven |
Hades-towards the design of an asynchronous superscalar processor. |
ASYNC |
1995 |
DBLP DOI BibTeX RDF |
asynchronous superscalar processor, Hades, generic processor architecture, asynchronous processor design, decoupled operand forwarding, register writeback, computer architecture, logic design |
15 | Shannon V. Morton, Sam S. Appleton, Michael J. Liebelt |
ECSTAC: a fast asynchronous microprocessor. |
ASYNC |
1995 |
DBLP DOI BibTeX RDF |
asynchronous microprocessor, ECSTAC, two-phase communication, processor pipeline, register tagging, branch techniques, block simulation, caches, logic design, asynchronous circuits, microprocessor chips |
15 | S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault |
Test configurations to enhance the testability of sequential circuits. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
shift operation, scan register, test operation, modified flip-flops, ISCAS89 benchmarks, multiconfiguration, triconfiguration, dynamic generation, logic testing, controllability, design for testability, design for testability, sequential circuits, sequential circuits, observability, observability, DFT, fault coverage, flip-flops, minimisation, scan designs, test application time, test vector |
15 | Meng-Lieh Sheu, Chung-Len Lee 0001 |
A programmable multiple-sequence generator for BIST applications. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
programmable multiple-sequence generator, BIST applications, two-dimension-like feedback shift register, deterministic sequence, pseudo-random vectors, sequence segmentation method, stuck-open fault testing, logic testing, delays, built-in self test, sequential circuits, shift registers, delay fault testing, binary sequences, sequential circuit testing, regular structure, MCM testing |
15 | Jacob Savir |
Module level weighted random patterns. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
module level self-test architecture, pseudorandom pattern generator, universal weighting generator, scan latch, near-optimal weight, signal pins, weight control function, self-test time, logic testing, probability, integrated circuit testing, automatic testing, multivalued logic circuits, boundary scan testing, scan test, weighted random patterns, multiple input signature register |
15 | Jing-Yang Jou |
An effective BIST design for PLA. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
BIST design, deterministic test pattern generator, cross point, AND array, fault detection capability, contact fault model, logic testing, built-in self test, integrated circuit testing, combinational circuits, automatic testing, programmable logic arrays, PLA, CMOS logic circuits, characteristic polynomial, stuck-at fault model, multiple input signature register |
15 | Janusz Rzeszut, Bozena Kaminska, Yvon Savaria |
A new method for testing mixed analog and digital circuits. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
charge-coupled device circuits, mixed analog and digital circuits, analog test points, simultaneous observation, analog multiplexer, signal path, analog shift register, input voltage, integrated circuit testing, shift registers, mixed analogue-digital integrated circuits, charge coupled device, analogue processing circuits |
15 | Santanu Dutta, Wayne H. Wolf, Andrew Wolfe |
VLSI issues in memory-system design for video signal processors. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
VLSI issues, video signal processors, memory-system architectures, circuit-level issues, register-cache based hierarchy, general-purpose programmable microprocessors, VLSI, system architecture, utilization, memory architecture, memory architecture, video signal processing, area, cycle time, memory-system design |
15 | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
design for hierarchical testability, gate-level sequential test generation, controller data path circuits, large data path bit-widths, minimal test hardware, system-level test set, logic testing, high level synthesis, high level synthesis, integrated circuit testing, design for testability, design for testability, automatic testing, logic CAD, integrated circuit design, behavioral synthesis, logic gates, register-transfer level design, RTL circuits |
15 | Kumar N. Lalgudi, Marios C. Papaefthymiou |
Efficient retiming under a general delay model. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
retiming algorithm, general delay model, edge-triggered circuits, load-dependent gate delays, register delays, integer linear programming constraints, integer phonotonic programming formulation, linear programming, delays, timing, integer programming, logic design, logic design, logic circuits, clock skew, propagation delays, interconnect delays |
15 | Sreeram Duvvuru, Siamak Arya |
Evaluation of a branch target address cache. |
HICSS (1) |
1995 |
DBLP DOI BibTeX RDF |
branch target address cache evaluation, sequential flow, pipeline bubbles, branch penalty, cycles per instruction, multiple instruction issue processors, branch resolution scheme, target instruction fetch, unpredictable branches, fully predicated processor architecture, fetch stage, branch target caching policies, branch target address cache, register-relative branches, performance evaluation, interrupts, interrupt, program compilers, pipeline processing, cache storage, storage allocation, instructions, program control structures, cache sizes |
15 | Chuck Monahan, Forrest Brewer |
Symbolic execution of data paths. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
combinational switching, data-path model, path constraints, bus hazards, register constraints, control encoding limitations, path-constrained model, DSP microprocessor, switching logic, connection constraints, operand constraints, scheduling, Boolean functions, Boolean functions, logic design, combinational circuits, data flow analysis, processor scheduling, symbolic execution, data flow graphs, digital signal processing chips, constraint handling, combinational logic, dataflow graphs, hazards and race conditions, memory elements |
15 | Zijian Zhou 0001, Xiaoyu Song, Francisco Corella, Eduard Cerny, Michel Langevin |
Partitioning transition relations efficiently and automatically. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
automatic partitioning, state transition relations, abstract implicit state enumeration procedure, automatic verification method, graph theory, finite state machines, logic CAD, state estimation, logic partitioning, extended finite state machines, register transfer level designs, multiway decision graphs |
15 | Nadime Zacharia, Janusz Rajski, Jerzy Tyszer |
Decompression of test data using variable-length seed LFSRs. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
test data decompression, variable-length seed LFSRs, deterministic test vectors, scan circuits, multiple polynomial LFSR, encoding efficiency, logic testing, built-in self test, integrated circuit testing, encoding, automatic testing, polynomials, linear feedback shift register, shift registers, modular design, digital integrated circuits |
15 | Shridhar K. Mukund, Edward J. McCluskey, T. R. N. Rao |
An apparatus for pseudo-deterministic testing. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
pseudo-deterministic testing, deterministic patterns, at-speed BIST, arbitrary length shift register, care bits, tap configurations, test segments, don't care bits, random pattern resistant faults, interconnected logic blocks, logic testing, built-in self test, integrated circuit testing, LFSR, shift registers, computational efficiency, test vector, pseudo-random sequences |
15 | B. Hamdi, Hakim Bederr, Michael Nicolaidis |
A tool for automatic generation of self-checking data paths. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
self-checking data paths, ALUs, shifters, double rail checkers, logic testing, built-in self test, microprocessors, adders, circuit CAD, multipliers, microcontrollers, register files, circuit design, CAD tools, automatic generation, automatic test software, dividers, circuit testing, parity checkers |
15 | André Seznec, Jacques Lenfant |
Interleaved Parallel Schemes. |
IEEE Trans. Parallel Distributed Syst. |
1994 |
DBLP DOI BibTeX RDF |
interleaved parallelschemes, vector supercomputers, vector register processors, global highly interleavedmemory, memory throughput, synchronization mode, interconnection network, parallel machines, synchronisation, vector processor systems |
15 | Krishna V. Palem, Barbara B. Simons |
Scheduling Time-Critical Instructions on RISC Machines. |
ACM Trans. Program. Lang. Syst. |
1993 |
DBLP DOI BibTeX RDF |
RISC machine scheduling, NP-complete, latency, compiler optimization, register allocation, greedy algorithm, instruction scheduling, deadline, RISC, pipeline processor |
15 | Slawomir Pilarski, Kevin James Wiebe |
Counter-based compaction: An analysis for BIST. |
J. Electron. Test. |
1992 |
DBLP DOI BibTeX RDF |
compaction by counter, edge counting, one's counting, transition counting, built-in self-test, linear feedback shift register, signature analysis, Aliasing probability, test response compaction |
15 | Karl J. Ottenstein |
A Simplified Framework for Reduction in Strength. |
IEEE Trans. Software Eng. |
1989 |
DBLP DOI BibTeX RDF |
loop execution, sequential processors, induction variable substitution, register requirements, array dependences, language fragments, iteration test replacement, target code, program compilers, parallelizing compilers, execution time, teaching tool, inverse transformation |
15 | Jean-Loup Baer, Yi-Bing Lin |
Improving Quicksort Performance with a Codewort Data Structure. |
IEEE Trans. Software Eng. |
1989 |
DBLP DOI BibTeX RDF |
codeword data structure, long, alphanumeric sequences, bytes, codeword generator, character count, first nonequal byte, quicksort algorithm, architecture-dependent parameters, in-line expansion, data structures, caches, sorting, compiler optimizations, register allocation, performance improvement, ordering, pointer, records, keys, swaps, write policies |
15 | Satish L. Rege, John Grason |
Computer aided design of digital systems: Data part exploration. |
ACM Annual Conference (2) |
1978 |
DBLP DOI BibTeX RDF |
Data operations, Register transfer system, Computer aided design |
15 | Vincent A. Busam, Donald E. Englund |
Optimization of expressions in Fortran. |
Commun. ACM |
1969 |
DBLP DOI BibTeX RDF |
DO loops, invariant calculations, optimization, compilation, compilers, FORTRAN, FORTRAN, register allocation, expressions, common subexpressions, subscripts |
15 | Xiangrong Zhou, Peter Petrov |
Cross-layer customization for rapid and low-cost task preemption in multitasked embedded systems. |
ACM Trans. Embed. Comput. Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Nathaniel Fairfield, David Wettergreen |
Evidence grid-based methods for 3D map matching. |
ICRA |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Yu-Ju Hong, Ya-Shih Huang, Juinn-Dar Huang |
Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Wen-Wen Hsieh, TingTing Hwang |
Thermal-aware post compilation for VLIW architectures. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Asadollah Shahbahrami, Ben H. H. Juurlink |
Performance Improvement of Multimedia Kernels by Alleviating Overhead Instructions on SIMD Devices. |
APPT |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Jih-Ching Chiu, Yu-Liang Chou, Hua-Yi Tzeng |
A multi-streaming SIMD architecture for multimedia applications. |
Conf. Computing Frontiers |
2009 |
DBLP DOI BibTeX RDF |
SIMD, streaming processing, streaming computing, processor-in-memory, mmx, multimedia extensions, pim |
15 | Chin-Teng Lin, Yuan-Chu Yu, Lan-Da Van |
Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Phan Cong Vinh, Jonathan P. Bowen |
Formalization of Data Flow Computing and a Coinductive Approach to Verifying Flowware Synthesis. |
Trans. Comput. Sci. |
2008 |
DBLP DOI BibTeX RDF |
Dynamically Programmable Field Array (DPGA), Flowware, Configware, Configware engineering, Embedded systems, Formal methods, Reconfigurable computing, Dynamic reconfiguration |
15 | Kun-Yuan Hsieh, Yung-Chia Lin, Chien-Ching Huang, Jenq Kuen Lee |
Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
VLIW DSP processor, optimizing context switch overhead, microkernel design |
15 | Wei-Sheng Huang, Yu-Ru Hong, Juinn-Dar Huang, Ya-Shih Huang |
A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Athinayaranan Vallavaraj, Brian G. Stewart, David K. Harrison, F. G. McIntosh |
Reducing the PAPR of OFDM Using a Simplified Scrambling SLM Technique with No Explicit Side Information. |
ICPADS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Jeonghun Noh, Sachin Deshpande |
Pseudo-DHT: Distributed Search Algorithm for P2P Video Streaming. |
ISM |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Rachid Guerraoui, Marko Vukolic |
A Scalable and Oblivious Atomicity Assertion. |
CONCUR |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Frank Bouwens, Mladen Berekovic, Bjorn De Sutter, Georgi Gaydadjiev |
Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array. |
HiPEAC |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Delong Shang, Alexandre Yakovlev, Albert Koelmans, Danil Sokolov, Alexandre V. Bystrov |
Registers for Phase Difference Based Logic. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Dennis K. Y. Tong, Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu |
Wire Retiming Problem With Net Topology Optimization. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Anup Gangwar, M. Balakrishnan, Anshul Kumar |
Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
performance evaluation, VLIW, ASIP, clustered VLIW processors |
15 | Sondre Rønjom, Tor Helleseth |
The Linear Vector Space Spanned by the Nonlinear Filter Generator. |
SSC |
2007 |
DBLP DOI BibTeX RDF |
cyclic vector spaces, stream ciphers, m-sequences |
15 | Sondre Rønjom, Tor Helleseth |
Attacking the Filter Generator over GF (2 m ). |
WAIFI |
2007 |
DBLP DOI BibTeX RDF |
solving nonlinear equations, Boolean functions, m-sequences, Filter generators |
15 | Sultan Al-Hinai, Lynn Margaret Batten, Bernard D. Colbert |
Mutually Clock-Controlled Feedback Shift Registers Provide Resistance to Algebraic Attacks. |
Inscrypt |
2007 |
DBLP DOI BibTeX RDF |
stream cipher, algebraic attacks, clock-control |
15 | Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar |
Optimizing instruction-set extensible processors under data bandwidth constraints. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Marcin Jurdzinski, Ranko Lazic 0001 |
Alternation-free modal mu-calculus for data trees. |
LICS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Taemin Kim, Xun Liu |
Compatibility path based binding algorithm for interconnect reduction in high level synthesis. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Yong Ki Lee, Ingrid Verbauwhede |
A Compact Architecture for Montgomery Elliptic Curve Scalar Multiplication Processor. |
WISA |
2007 |
DBLP DOI BibTeX RDF |
Compact Elliptic Curve Processor, Montgomery Scalar Multiplication |
15 | Xiang Gao 0002, Eric A. M. Klumperink, Bram Nauta |
Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Jae-Woo Lee |
A Model of Location Management Based on Broadcasting Visitor Location. |
MUE |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Ittai Abraham, Gregory V. Chockler, Idit Keidar, Dahlia Malkhi |
Byzantine disk paxos: optimal resilience with byzantine shared memory. |
Distributed Comput. |
2006 |
DBLP DOI BibTeX RDF |
T-tolerant object implementations, Lower bounds, Consensus, Byzantine failures, Wait freedom, Shared-memory emulations |
15 | Weihua Zhang, Xinglong Qian, Ye Wang, Binyu Zang, Chuanqi Zhu |
Optimizing compiler for shared-memory multiple SIMD architecture. |
LCTES |
2006 |
DBLP DOI BibTeX RDF |
multiple SIMD, optimization, locality, replication, shared memory |
15 | Md. Mafijul Islam, Per Stenström |
Reduction of Energy Consumption in Processors by Early Detection and Bypassing of Trivial Operations. |
ICSAMOS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Christoph Albrecht |
Efficient incremental clock latency scheduling for large circuits. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Hanno Scharwächter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
An interprocedural code optimization technique for network processors using hardware multi-threading support. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Jianhui Li, Qi Zhang, Shu Xu, Bo Huang 0002 |
Optimizing Dynamic Binary Translation for SIMD Instructions. |
CGO |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Naomi Fujimura, Zen-ichi Hirayama, Tatsuya Oka, Masato Komori |
Implementation and experience with the terminal registration system with web interface. |
SIGUCCS |
2006 |
DBLP DOI BibTeX RDF |
static IP address, terminal registration, networking, personal computing, web-based, system configuration, DHCP |
15 | Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu, Wen-Li Shih, Shih-Chang Chen, Chung-Kai Chen, Chien-Ching Huang, Yi-Ping You, Jenq Kuen Lee |
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors. |
RTCSA |
2006 |
DBLP DOI BibTeX RDF |
|
15 | William R. Roberts, Dimitrios Velenis |
Power supply variation effects on timing characteristics of clocked registers. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | William R. Roberts, Dimitrios Velenis |
Effects of process and environmental variations on timing characteristics of clocked registers. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Ranko Lazic 0001 |
Safely Freezing LTL. |
FSTTCS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang |
Visibility enhancement for silicon debug. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
silicon validation, functional verification, silicon debug |
15 | Lian Li 0002, Lin Gao 0002, Jingling Xue |
Memory Coloring: A Compiler Approach for Scratchpad Memory Management. |
IEEE PACT |
2005 |
DBLP DOI BibTeX RDF |
|
15 | William R. Roberts, Dimitrios Velenis |
Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Il-soo Lee, Jae-Hoon Jeong, Anthony P. Ambler |
Using the Nonlinear Property of FSR and Dictionary Coding for Reduction of Test Volume. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Stephen Hines, Gary S. Tyson, David B. Whalley |
Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows. |
MICRO |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Liang Huang, Yici Cai, Qiang Zhou 0001, Xianlong Hong, Jiang Hu, Yongqiang Lu 0001 |
Clock network minimization methodology based on incremental placement. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Jingling Xue |
Compiler-Directed Scratchpad Memory Management. |
ICESS |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Gregory V. Chockler, Nancy A. Lynch, Sayan Mitra, Joshua A. Tauber |
Proving Atomicity: An Assertional Approach. |
DISC |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Jason Baumgartner, Hari Mony |
Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies. |
CHARME |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Miquel Pericàs, Adrián Cristal, Rubén González 0001, Daniel A. Jiménez |
Chained In-Order/Out-of-Order DoubleCore Architecture. |
SBAC-PAD |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Andrei Sergeevich Terechko, Manish Garg, Henk Corporaal |
Evaluation of Speed and Area of Clustered VLIW Processors. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Yongqiang Lu 0001, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou 0001, Yici Cai, Liang Huang, Jiang Hu |
Navigating registers in placement for clock network minimization. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
low power, placement, clock network, variation tolerance |
15 | Jinson Koppanalil, Eric Rotenberg |
A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
slipstream, preexecution, chip multiprocessor, multithreading, Microarchitecture |
15 | Gurhan Kucuk, Dmitry Ponomarev 0001, Oguz Ergin, Kanad Ghose |
Complexity-Effective Reorder Buffer Designs for Superscalar Processors. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Dmitry V. Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose |
Isolating Short-Lived Operands for Energy Reduction. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
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