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Found 4878 publication records. Showing 4770 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
96S. Dabas, Ning Dong 0002, Jaijeet S. Roychowdhury Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF gate delay modelling, accurate delay/timing macromodels, digital gates, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, sequential latch, latches, full adder, current-source models, XOR gates
76Chris J. Myers, Peter A. Beerel, Teresa H.-Y. Meng Technology mapping of timed circuits. Search on Bibsonomy ASYNC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF gate library, C-elements, ATACS, timing, logic design, logic CAD, asynchronous circuits, asynchronous circuits, timing information, AND gates, synthesis tool, OR gates, timed circuits
68Nathan O. Scott, Gerhard W. Dueck Pairwise decomposition of toffoli gates in a quantum circuit. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF elementary quantum gates, synthesis, minimization, reversible logic, quantum circuits
64Shoujue Wang, Xunwei Wu, Hongjuan Feng The High-Speed Ternary Logic Gates Based on the Multiple beta Transistors. Search on Bibsonomy ISMVL The full citation details ... 1995 DBLP  DOI  BibTeX  RDF high speed ternary logic gates, multiple /spl beta/ transistors, multiple emitter transistor, current gain, linear AND/OR gates, multi valued literal circuits, high speed multi valued logic circuits, multivalued logic circuits, logic gates, ternary logic, transistors
56Stephen S. Bullock, Igor L. Markov An arbitrary twoqubit computation In 23 elementary gates or less. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF CNOT, circuit decomposition, elementary gates, lie theory, optimization, algorithms, lower bounds, synthesis, quantum circuits, qubit
54Vincenzo Catania, Marco Russo Analog gates for a VLSI fuzzy processor. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF VLSI fuzzy processor, synchronous fuzzy circuits, high noise immunity, fuzzy gates, VLSI, fuzzy logic, CMOS logic circuits, CMOS technology, logic gates, analogue processing circuits
53Ahmed N. Sulaiman, Patrick Olivier Attribute gates. Search on Bibsonomy UIST The full citation details ... 2008 DBLP  DOI  BibTeX  RDF crossing interfaces, large interactive displays, tabletop territories, pen-based input, digital tabletops, user interface components
51Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller Toffoli network synthesis with templates. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
51Mawahib Hussein Sulieman On the Reliability of Interconnected CMOS Gates Considering MOSFET Threshold-Voltage Variations. Search on Bibsonomy NanoNet The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Reliability, CMOS, threshold voltage, gates
47Stasys Jukna Finite Limits and Monotone Computations: The Lower Bounds Criterion. Search on Bibsonomy CCC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF real gates, lower bounds, threshold gates, monotone circuits
47Chris J. Myers, Tomas Rokicki, Teresa H.-Y. Meng Automatic synthesis of gate-level timed circuits with choice. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates
47Kristoffer Arnsfelt Hansen Depth Reduction for Circuits with a Single Layer of Modular Counting Gates. Search on Bibsonomy CSR The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
47Yu Hu 0002, Satyaki Das, Steven Trimberger, Lei He 0001 Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
47Rolando Ramírez Ortiz, John P. Knight Compatible cell connections for multifamily dynamic logic gates. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
47Sudhakar Bobba, Ibrahim N. Hajj Current-Mode Threshold Logic Gates. Search on Bibsonomy ICCD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
47Mitsuru Igusa, Mark Beardslee, Alberto L. Sangiovanni-Vincentelli ORCA a Sea-of-Gates Place and Route System. Search on Bibsonomy DAC The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
46Rajesh Garg, Sunil P. Khatri A novel, highly SEU tolerant digital circuit design approach. Search on Bibsonomy ICCD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
46Wolfgang Maass 0001, Georg Schnitger, Eduardo D. Sontag On the Computational Power of Sigmoid versus Boolean Threshold Circuits Search on Bibsonomy FOCS The full citation details ... 1991 DBLP  DOI  BibTeX  RDF polynomially bounded weights, sigmoid threshold gates, smooth threshold gates, depth 2 circuits, Boolean threshold circuits, constant size circuits, Boolean threshold gates, polynomial size sigmoid threshold circuits, Boolean functions, computational power, constant depth circuits
45Shane Greenstein The Long Arc Behind Bill Gates' Wealth. Search on Bibsonomy IEEE Micro The full citation details ... 2008 DBLP  DOI  BibTeX  RDF William Gates, antitrust, economics, competition, browser, Microsoft, bundling
45Thomas Flohr 0002 Defining Suitable Criteria for Quality Gates. Search on Bibsonomy IWSM/Metrikon/Mensura The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Practical measurement application, Measurement acceptance, Quality Gates
44Youngja Park, Christopher S. Gates, Stephen C. Gates Estimating Asset Sensitivity by Profiling Users. Search on Bibsonomy ESORICS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
43Hung Chi Lai, Saburo Muroga Minimum Parallel Binary Adders with NOR (NAND) Gates. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1979 DBLP  DOI  BibTeX  RDF NOR gates, carry-ripple adders, minimum adders, NAND gates, logic design, Adders
43Jay Niel Culliney, Ming Huei Young, Tomoyasu Nakagawa, Saburo Muroga Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1979 DBLP  DOI  BibTeX  RDF n-p-n-equivalence classes, four variable switching functions, optimal networks, logical design, branch-and-bound method, AND gates, OR gates
41Xiaojun Ma, Jing Huang 0001, Cecilia Metra, Fabrizio Lombardi Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA. Search on Bibsonomy J. Electron. Test. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Testing, Emerging technologies, Reversible computing, QCA
41Asif Islam Khan, Nadia Nusrat, Samira Manabi Khan, Masud Hasan, Mozammel H. A. Khan Quantum Realization of Some Ternary Circuits Using Muthukrishnan-Stroud Gates. Search on Bibsonomy ISMVL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
41William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang 0006, Marek A. Perkowski Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
41Pawel Kerntopf, Marek A. Perkowski, Mozammel H. A. Khan On Universality of General Reversible Multiple-Valued Logic Gates. Search on Bibsonomy ISMVL The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
40Marek A. Perkowski, Nouraddin Alhagi, Martin Lukac, Neha Saxena, Scott Blakely Synthesis of Small Reversible and Pseudo-Reversible Circuits Using Y-Gates and Inverse Y-Gates. Search on Bibsonomy ISMVL The full citation details ... 2010 DBLP  DOI  BibTeX  RDF pseudo-reversible logic gates, reversible circuits
40Mozammel H. A. Khan, Marek A. Perkowski GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic Circuits. Search on Bibsonomy ISMVL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
40Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller Synthesis of Fredkin-Toffoli reversible networks. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
40Märt Saarepera, Tomohiro Yoneda A Self-Timed Implementation of Boolean Functions. Search on Bibsonomy ASYNC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
40Kerry S. Lowe, P. Glenn Gulak A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
39Xinliang Zhang, Jing Xu, Jianji Dong, Dexiu Huang All-Optical Logic Gates Based on Semiconductor Optical Amplifiers and Tunable Filters. Search on Bibsonomy OSC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF all-optical logic gates, semiconductor optical amplifiers (SOAs), delay interferometer, bandpass filter
39Shane Greenstein The Long Arc Behind Bill Gates' Wealth, Part 2. Search on Bibsonomy IEEE Micro The full citation details ... 2008 DBLP  DOI  BibTeX  RDF William Gates, antitrust, economics, competition, browser, Microsoft, bundling
38Francisco J. Artigas, Soon Ae Chun, Yogi Sookhu Real-time ocean surge warning system, meadowlands district of New Jersey. Search on Bibsonomy D.GO The full citation details ... 2009 DBLP  BibTeX  RDF emergency management system, real-time ocean surge warnings, tide gates, sensor network, flood, information dissemination, emergency management, sensor system
38David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah Timing verification of sequential domino circuits. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF domino gates, sequential domino circuits, static timing verification, logic testing, input signals
36Yuri B. Boiko, Gabriel A. Wainer Modeling quantum dot devices in Cell-DEVS environment. Search on Bibsonomy SpringSim The full citation details ... 2008 DBLP  DOI  BibTeX  RDF majority vote gates, quantum wire, cellular automata, discrete event simulation, quantum dot, XOR gates, cell-DEVS, quantum automata
36Yuyun Liao, D. M. H. Walker Optimal voltage testing for physically-based faults. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise
36M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor Compact test sets for industrial circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF compact test sets, industrial circuits, binary logic elements, three-state elements, compaction oriented decision making, heuristics, logic testing, integrated circuit testing, automatic test pattern generation, combinational circuits, automatic testing, multivalued logic circuits, test patterns, bidirectionals, xor gates, or gates, test set size
36S. C. Prasad, Kaushik Roy 0001 Circuit optimization for minimisation of power consumption under delay constraint. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF power consumption minimisation, internal capacitances, series-connected transistors, multipass algorithm, transistor reordering, VLSI, delays, logic design, logic CAD, circuit layout CAD, CMOS logic circuits, minimisation, circuit optimisation, integrated circuit layout, VLSI circuits, logic gates, capacitance, circuit optimization, delay constraint, CMOS gates
35Falk Unger Noise Threshold for Universality of Two-Input Gates. Search on Bibsonomy IEEE Trans. Inf. Theory The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
35Yang Zhao 0001, Tao Xu 0002, Krishnendu Chakrabarty Digital Microfluidic Logic Gates. Search on Bibsonomy NanoNet The full citation details ... 2008 DBLP  DOI  BibTeX  RDF microfluidic computing, digital microfluidics, logic gate
35Krishna Santhanam, Kenneth S. Stevens Dynamic gates with hysteresis and configurable noise tolerance. Search on Bibsonomy VLSI-SoC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
35Jose M. Marulanda, Ashok Kumar Srivastava, Ashwani K. Sharma Transfer characteristics and high frequency modeling of logic gates using carbon nanotube field effect transistors (CNT-FETs). Search on Bibsonomy SBCCI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF CNT-logic, cut-off frequency, small signal model, transfer characteristics, carbon nanotubes
35Wenping Wang, Zile Wei, Shengqi Yang, Yu Cao 0001 An efficient method to identify critical gates under circuit aging. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
35Xiaoyu Song, Guowu Yang, Marek A. Perkowski, Yuke Wang Algebraic Characterization of Reversible Logic Gates. Search on Bibsonomy Theory Comput. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Josep Carmona 0001, Jordi Cortadella, Yousuke Takada, Ferdinand Peper From molecular interactions to gates: a systematic approach. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF nanocascades, formal methods, nanocomputing
35Sandeep Dechu, Manoj Kumar Goparaju, Spyros Tragoudas A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates. Search on Bibsonomy DFT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Wladyslaw Homenda, Witold Pedrycz Balanced Fuzzy Gates. Search on Bibsonomy RSCTC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Arkadev Chattopadhyay, Kristoffer Arnsfelt Hansen Lower Bounds for Circuits with Few Modular and Symmetric Gates. Search on Bibsonomy ICALP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
35Stefan Mangard, Thomas Popp, Berndt M. Gammel Side-Channel Leakage of Masked CMOS Gates. Search on Bibsonomy CT-RSA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
35M. Moiz Khan, Spyros Tragoudas, Magdy S. Abadir, Jiang Brandon Liu Identification of Gates for Covering all Critical Paths. Search on Bibsonomy MTV The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
35Peter M. Kelly, C. J. Thompson, T. Martin McGinnity, Liam P. Maguire A Binary Multiplier Using RTD Based Threshold Logic Gates. Search on Bibsonomy IWANN (2) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
35Pawel Kerntopf Synthesis of Multipurpose Reversible Logic Gates. Search on Bibsonomy DSD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
35Alexis De Vos, Bart Desoete, Artur Adamski, Piotr Pietrzak, Maciej Sibínski, Tomasz Widerski Design of Reversible Logic Circuits by Means of Control Gates. Search on Bibsonomy PATMOS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
35Mayukh Bhattacharya, Pinaki Mazumder Noise Margins of Threshold Logic Gates containing Resonant Tunneling Diodes. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Quantum devices, Digital circuits, Resonant Tunneling Diode, Noise margin, Threshold gate
35Nicholas Pippenger Invariance of complexity measures for networks with unreliable gates. Search on Bibsonomy J. ACM The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
35G. D. Adams, Carlo H. Séquin Template Style Considerations for Sea-of-Gates Layout Generation. Search on Bibsonomy DAC The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
35Donald L. Richards Efficient Exercising of Switching Elements in Nets of Identical Gates. Search on Bibsonomy J. ACM The full citation details ... 1973 DBLP  DOI  BibTeX  RDF
34Kazuo Iwama, Hiroki Morizumi, Jun Tarui Negation-Limited Complexity of Parity and Inverters. Search on Bibsonomy Algorithmica The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Negation-limited circuit, Parity function, Inversion complexity, Gate elimination, Circuit complexity, Inverter
34Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. Massoud Dual-threshold pass-transistor logic design. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF dual threshold, pass transistor, low power, leakage
34Chia-Ming Chang 0002, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang 0002, Yu-Sheng Lu Type-matching clock tree for zero skew clock gating. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF physical design, gated clock, clock network synthesis
34Wieland Fischer, Berndt M. Gammel Masking at Gate Level in the Presence of Glitches. Search on Bibsonomy CHES The full citation details ... 2005 DBLP  DOI  BibTeX  RDF random masking, masked logic circuits, Cryptanalysis, side-channel attacks, DPA, power analysis, logic circuits, digital circuits, masking, glitches
34Li Ding 0002, Pinaki Mazumder On circuit techniques to improve noise immunity of CMOS dynamic logic. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
34Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller Fredkin/Toffoli Templates for Reversible Logic Synthesis. Search on Bibsonomy ICCAD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
34Chuen-Der Huang, I-Fang Chung, Nikhil R. Pal, Chin-Teng Lin Machine Learning for Multi-class Protein Fold Classification Based on Neural Networks with Feature Gating. Search on Bibsonomy ICANN The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
34Jing Shen, Motoi Inaba, Koichi Tanno, Okihiko Ishizuka Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors. Search on Bibsonomy ISMVL The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
34Vince Grolmusz, Gábor Tardos Lower Bounds for (MOD p - MOD m) Circuits. Search on Bibsonomy FOCS The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
34Sorin Cotofana, Stamatis Vassiliadis On the Design Complexity of the Issue Logic of Superscalar Machines. Search on Bibsonomy EUROMICRO The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
34Rajesh S. Parthasarathy, Ramalingam Sridhar Double Pass Transistor Logic for High Performance Wave Pipeline Circuits. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
34Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF leakage estimation, logic design, cmos gates
34Leomar S. da Rosa Jr., André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Felipe Ribeiro Schneider A comparative study of CMOS gates with minimum transistor stacks. Search on Bibsonomy SBCCI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF PTL, unateness, BDDs, technology mapping, switch theory, logical effort, CMOS gates
34Frank Sill, Jiaxi You, Dirk Timmermann Design of mixed gates for leakage reduction. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF mixed gates, leakage current, threshold voltage, gate leakage
34Markus Dichtl, Jovan Dj. Golic High-Speed True Random Number Generation with Logic Gates Only. Search on Bibsonomy CHES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF generalized ring oscillators, true randomness, Random number generation, logic gates, ring oscillators
34Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF dynamic gates, keeper design, reliability, VLSI, robustness, low-power design, process variation
34Michal Koucký 0001, Pavel Pudlák, Denis Thérien Bounded-depth circuits: separating wires from gates. Search on Bibsonomy STOC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF communication, complexity, lower bounds, regular languages, wires, constant-depth circuits, gates
34Joshua Berman, Arthur Drisko, François Lemieux, Cristopher Moore, Denis Thérien Circuits and Expressions with NOn-Associative Gates. Search on Bibsonomy CCC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF non-associative gates, non-associative groupoid, polyabelian groupoids, arbitrary Boolean functions, NC/sup 1/-complete, CIRCUIT VALUE, Boolean functions, multiplication, P-complete, EXPRESSION EVALUATION
32Oriol Roig, Jordi Cortadella, Enric Pastor Hierarchical gate-level verification of speed-independent circuits. Search on Bibsonomy ASYNC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF hierarchical gate-level verification, state signals, computational complexity, logic testing, time complexity, asynchronous circuits, speed-independent circuits, complex gates
32Sandip Kundu, Sudhakar M. Reddy Robust tests for parity trees. Search on Bibsonomy J. Electron. Test. The full citation details ... 1990 DBLP  DOI  BibTeX  RDF linear gates, parity trees, URTS, robust tests, test length
31Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
31Esther Rodríguez-Villegas, José M. Quintana, Maria J. Avedillo, Adoración Rueda High-speed low-power logic gates using floating gates. Search on Bibsonomy ISCAS (5) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
30Guilu Long 0001, Yang Liu Duality quantum computing. Search on Bibsonomy Frontiers Comput. Sci. China The full citation details ... 2008 DBLP  DOI  BibTeX  RDF duality computer, duality quantum computer, duality parallelism, duality gates, duality mode, generalized quantum gates, combiner, divider
30Michel Renovell, P. Huc, Yves Bertrand The concept of resistance interval: a new parametric model for realistic resistive bridging fault. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF electric resistance, resistance interval, intrinsic resistance, logic behavior, 0 to 500 ohm, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, fault detection, automatic testing, fault coverage, bridging faults, parametric model, logic gates, logic gates, resistive bridging fault, faulty behavior
30Shyue-Win Wei A Systolic Power-Sum Circuit for GF(2^m). Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF systolic power-sum circuit, power-sum circuit, error correction codes, error-correcting codes, finite field, systolic arrays, decoding, logic circuits, logic gates, logical gates
30Ingo Wegener Comments on "A Characterization of Binary Decision Diagrams". Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF EXOR gates, NEXOR gates, free BDDs, ordered BDDs, repeated BDDs, computational complexity, complexity, Boolean functions, binary decision diagrams, decision tables, combinatorial circuits
30Niraj K. Jha Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF CVS parity trees, strongly self-checking parity, single stuck-at, stuck-open, stuck-on fault detection, cascode voltage switch, differential cascode voltage switch, EX-OR gates, single-ended cascode voltage switch, logic testing, fault location, logic gates, two-rail checkers
30Eric Allender A Note on the Power of Threshold Circuits Search on Bibsonomy FOCS The full citation details ... 1989 DBLP  DOI  BibTeX  RDF unbounded-fan-in circuits, depth-three threshold circuits, polynomial hierarchy, threshold circuits, AND gates, OR gates
30Hung Chi Lai, Saburo Muroga Logic Networks of Carry-Save Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1982 DBLP  DOI  BibTeX  RDF parallel adder in double-rail input logic, Carry?save adders, input bundles, multioperand adders, NAND gates, NOR gates, output bundles, logic design, multipliers, full adders
30Jing Wang 0001, Gianluca Meloni, Gianluca Berrettini, Luca Potì, Antonella Bogoni All-Optical Clocked Flip-Flops Exploiting SOA-Based SR Latches and Logic Gates. Search on Bibsonomy OSC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF optical flip-flop, optical logic gate, optical signal processing, semiconductor optical amplifier (SOA)
30Hagen Sämrow, Claas Cornelius, Frank Sill, Andreas Tockhorn, Dirk Timmermann Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown. Search on Bibsonomy SBCCI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF gate oxide breakdown, reliability, integrated circuit design, redundant systems
30Ashish Goel, Morteza Ibrahimi Renewable, Time-Responsive DNA Logic Gates for Scalable Digital Circuits. Search on Bibsonomy DNA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
30James Donald, Niraj K. Jha Reversible logic synthesis with Fredkin and Peres gates. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Quantum computing, reversible logic
30David Guerrero Martos, Alejandro Millán 0001, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo Static Power Consumption in CMOS Gates Using Independent Bodies. Search on Bibsonomy PATMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
30Mario Vélez, Juan Ospina Universal Quantum Gates Via Yang-Baxterization of Dihedral Quantum Double. Search on Bibsonomy ICANNGA (1) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
30Arkadev Chattopadhyay, Navin Goyal, Pavel Pudlák, Denis Thérien Lower bounds for circuits with MOD_m gates. Search on Bibsonomy FOCS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
30Kristian Granhaug, Snorre Aunet, Tor Sverre Lande Body-bias regulator for ultra low power multifunction CMOS gates. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
30Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson CMOS Realization of Online Testable Reversible Logic Gates. Search on Bibsonomy ISVLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
30Kazuyuki Amano, Akira Maruoka On the Complexity of Depth-2 Circuits with Threshold Gates. Search on Bibsonomy MFCS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
30Emanuele Viola Pseudorandom Bits for Constant Depth Circuits with Few Arbitrary Symmetric Gates. Search on Bibsonomy CCC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
30Geoff V. Merrett, Bashir M. Al-Hashimi Leakage Power Analysis and Comparison of Deep Submicron Logic Gates. Search on Bibsonomy PATMOS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
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