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1951-1986 (15) 1987-1989 (24) 1990-1992 (17) 1993-1994 (23) 1995 (22) 1996 (21) 1997 (33) 1998 (45) 1999 (67) 2000 (54) 2001 (72) 2002 (80) 2003 (94) 2004 (109) 2005 (132) 2006 (167) 2007 (121) 2008 (118) 2009 (98) 2010 (55) 2011 (57) 2012 (47) 2013 (69) 2014 (61) 2015 (80) 2016 (81) 2017 (87) 2018 (77) 2019 (106) 2020 (97) 2021 (109) 2022 (121) 2023 (132) 2024 (37)
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article(1062) data(3) incollection(2) inproceedings(1453) phdthesis(8)
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Found 2528 publication records. Showing 2528 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
99Youngmin Kim, Dusan Petranovic, Dennis Sylvester Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF capacitance increment, metal fill insertion, inter level dielectric thickness planarity, metal dummy, signal capacitance, electrical characteristic, signal dimensions, dummy shape, dummy dimensions, simple test patterns, benchmark circuits, weighting function
92Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa Interconnect capacitance extraction for system LCD circuits. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF interconnect capacitance, system LCD, capacitance extraction
80Carlos Fernando Teodósio Soares, Antonio Petraglia A systematic method to approximate capacitance ratios to improve capacitance matching in SC filters. Search on Bibsonomy SBCCI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF capacitance matching, design method, switched-capacitor filters
75Dukgwon Lee, Seunghyun Beak, Youngmin Lee, Eunser Lee, Jungkook Kim, Gyung-Leen Park, Taikyeong Jeong Minimize the delay of parasitic capacitance and modeling in RLC circuit. Search on Bibsonomy ICHIT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Elmore, parasitic capacitance, delay, interconnection, oscillator
74Hiroshi Yamamoto, Jeffrey A. Davis Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
74Andrew B. Kahng, Kambiz Samadi, Puneet Sharma Study of Floating Fill Impact on Interconnect Capacitance. Search on Bibsonomy ISQED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
70X. Cai, Keith Nabors, Jacob K. White 0001 Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF piecewise constant techniques, permittivity, Galerkin techniques, multipole-accelerated capacitance extraction, multiple dielectrics, arbitrary piecewise-constant dielectric medium, IC interconnections, VLSI, VLSI, integrated circuit design, circuit CAD, boundary-elements methods, boundary element method, capacitance, integrated circuit interconnections, Galerkin method, capacitance extraction, 3D structures
68Koichi Nose, Soo-Ik Chae, Takayasu Sakurai Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). Search on Bibsonomy ISLPED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF gate capacitance, low supply voltage, low-power design
66Andrew Labun Rapid method to account for process variation in full-chip capacitance extraction. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
64Srinivas Katkoori, Nand Kumar, Ranga Vemuri High level profiling based low power synthesis technique. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF high level profiling based low power synthesis technique, average switching capacitance, user-specified set, switching capacitance, VLSI, delay, logic design, power estimation, area
58Sadahiro Tani, Yoshihiro Uchida, Makoto Furuie, Shuji Tsukiyama, BuYeol Lee, Shuji Nishi, Yasushi Kubota, Isao Shirakawa, Shigeki Imai Parasitic capacitance modeling for multilevel interconnects. Search on Bibsonomy APCCAS (1) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
58Peter J. Wright, Yung-Che Albert Shih Capacitance of top leads metal - comparison between formula, simulation, and experiment. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
53Nihar R. Mohapatra, Arijit Dutta, Madhav P. Desai, V. Ramgopal Rao Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics. Search on Bibsonomy VLSI Design The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
52Jian Cui, Gengsheng Chen, Ruijing Shen, Sheldon X.-D. Tan, Wenjian Yu, Jiarong Tong Variational capacitance modeling using orthogonal polynomial method. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF random variable reduction, process variations, capacitance extraction, orthogonal decomposition
52Tarek A. El-Moselhy, Ibrahim M. Elfadel, David Widiger Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parameters. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF sensitivity analysis, capacitance extraction, adjoint method
52Haihua Su, David Widiger, Chandramouli V. Kashyap, Frank Liu 0001, Byron Krauter A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF glitch propagation, noise analysis, effective capacitance
52Yanhong Yuan, Prithviraj Banerjee A Parallel Implementation of a Fast Multipole Based 3-D Capacitance Extraction Program on Distributed Memory Multicomputer. Search on Bibsonomy IPDPS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF fast multipole algorithm, parallel algorithms, distributed memory multiprocessors, Capacitance extraction
52Jason Cong, Lei He 0001, Cheng-Kok Koh, David Zhigang Pan Global interconnect sizing and spacing with consideration of coupling capacitance. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF GISS solutions, asymmetric wire sizing, delay reduction, fringing capacitances, global interconnect sizing and spacing, global wire sizing, interconnect delay minimization, multiple nets, optimal wire sizing, spacing solution, symmetric effective fringing properties, VLSI, coupling capacitance
51Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
51Michael Ott, Jason Abt, Udit Sharma, Edward Keyes, Trevor J. Hall, Henry Schriemer Quantitative Capacitance Measurements of MOS Structures using a Scanning Probe Microscope. Search on Bibsonomy CCECE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
51Weiping Shi, Fangqing Yu A divide-and-conquer algorithm for 3-D capacitance extraction. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
51Fangqing Yu, Weiping Shi A Divide-and-Conquer Algorithm for 3D Capacitance Extraction. Search on Bibsonomy ISQED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
51Achintya Halder, Abhijit Chatterjee, Pramodchandran N. Variyam, John Ridley Measuring Stray Capacitance on Tester Hardware. Search on Bibsonomy VTS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
51Andrew B. Kahng, Sudhakar Muddu Improved Effective Capacitance Computations for Use in Logic and Layout Optimization. Search on Bibsonomy VLSI Design The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
51Muhammad M. Khellah, Mohamed I. Elmasry Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1998 DBLP  DOI  BibTeX  RDF low-power design, power estimation, high-level design
51Michael W. Beattie, Lawrence T. Pileggi Bounds for BEM Capacitance Extraction. Search on Bibsonomy DAC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
48Minoru Watanabe, Fuminori Kobayashi A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF 0.35 micron, zero-overhead dynamic optically reconfigurable gate array VLSI, ZO-DORGA-VLSI, junction capacitance, photodiodes, load capacitance, configuration memory, CMOS process chip
48Patrick F. Cummins, Geoffrey K. Vallis Algorithm 732; solvers for self-adjoint elliptic problems in irregular two-dimensional domains. Search on Bibsonomy ACM Trans. Math. Softw. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF capacitance iteration, capacitance matrix, fast Poisson solvers, Green's function, elliptic equations
47Michael W. Beattie, Hui Zheng, Anirudh Devgan, Byron Krauter Spatially distributed 3D circuit models. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF boundary element method (BEM), distributed circuit models, inverse inductance, capacitance
46Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey Yield evaluation of analog placement with arbitrary capacitor ratio. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
46Anand Ramalingam, Giri Devarayanadurg, David Z. Pan Accurate power grid analysis with behavioral transistor network modeling. Search on Bibsonomy ISPD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF RC model of transistor, behavioral modeling of switch, power grid
45Wenjian Yu, Chao Hu, Wangyang Zhang Variational capacitance extraction of on-chip interconnects based on continuous surface model. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF geometric variation modeling, hermite polynomial chaos method, quadratic variation model, variational capacitance extraction, spatial correlation
45Min Zhao 0001, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF sequence of linear programming, macromodeling, budgeting, decoupling capacitance
45Hua Xiang 0001, Kai-Yuan Chao, Martin D. F. Wong Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Layer migration, Max-cut, Capacitance coupling
45Rong Jiang 0002, Yi-Hao Chang, Charlie Chung-Ping Chen ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF interconnect, iterative methods, extraction, boundary element method, capacitance, parasitic
45Shu Yan, Vivek Sarin, Weiping Shi Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF interconnect, iterative methods, preconditioning, capacitance extraction
45Jinsong Hou, Zeyi Wang, Xianlong Hong The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance. Search on Bibsonomy ASP-DAC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Parasitic Capacitance, Hierarchical h-Adaptive Computation, VLSI, Boundary Element Method
43Rupesh S. Shelar An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors. Search on Bibsonomy ISPD The full citation details ... 2009 DBLP  DOI  BibTeX  RDF routing, power, clock distribution
43Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung On the feasibility of early routing capacitance estimation for FPGAs. Search on Bibsonomy FPL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
43Usha Narasimha, Anthony M. Hill, N. S. Nagaraj SmartExtract: Accurate Capacitance Extraction for SOC Designs. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43Di Wu 0017, Jiang Hu, Min Zhao 0001, Rabi N. Mahapatra Timing driven track routing considering coupling capacitance. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
43S. B. Prakash, Pamela Abshire, M. Urdaneta, Elisabeth Smela A CMOS capacitance sensor for cell adhesion characterization. Search on Bibsonomy ISCAS (4) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
43Jason Helge Anderson, Farid N. Najm Interconnect capacitance estimation for FPGAs. Search on Bibsonomy ASP-DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
43Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen Optimal spacing and capacitance padding for general clock structures. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
43Pratheep A. Nair, Anubhav Gupta, Madhav P. Desai An On-Chip Coupling Capacitance Measurement Technique. Search on Bibsonomy VLSI Design The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
43Michael W. Beattie, Lawrence T. Pileggi Error bounds for capacitance extraction via window techniques. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
43Andrew B. Kahng, Sudhakar Muddu New efficient algorithms for computing effective capacitance. Search on Bibsonomy ISPD The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
43Keith Nabors, Jacob K. White 0001 FastCap: a multipole accelerated 3-D capacitance extraction program. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
41Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda Scan insertion criteria for low design impact. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF scan insertion criteria, design impact, flip-flop ordering, capacitance constraints, layout information, Italtel Design Environment, logic testing, integrated circuit testing, sequential circuits, automatic testing, application specific integrated circuits, logic CAD, flip-flops, integrated circuit design, power dissipation, partial scan, design flow, boundary scan testing, scan chain, capacitance, full scan
41G. Enrique Fernandez, R. Sridhar Dual rail static CMOS architecture for wave pipelining. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF dual rail static CMOS architecture, gate capacitance, storage elements, DRSCMOS, multi-functional basic building blocks, combinational logic block, delays, timing, throughput, combinational circuits, power consumption, pipeline processing, CMOS logic circuits, digital systems, capacitance, wave pipelining, delay variations
41Stephen K. Sunter A low cost 100 MHz analog test bus. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF analog test bus, on-chip analog bus, digital three-state inverter, low-input capacitance, signal bandwidth, bus input, design for testability, DFT, integrated circuit design, mixed-signal circuits, capacitance, mixed analogue-digital integrated circuits, IC design, 100 MHz
39Bo Shen, Sunil P. Khatri, Takis Zourntos Implementation of MOSFET based capacitors for digital applications. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF MOSFET capacitor, constant capacitance, reference capacitor
39Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera Effects of on-chip inductance on power distribution grid. Search on Bibsonomy ISPD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF on-chip inductance, power supply noise, power distribution network, decoupling capacitance
38Xiangyin Zeng, Jiangqi He, M. N. Abdulla, Qing-Lun Chen Understanding and closed-form-formula determination of frequency-dependent bonding-pad characterization. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
38Mohsen Shavandi, Walied A. Moussa Investigation of a 3-D Capacitor Micro Strain Gauge for Applications in Biomedical and Industrial Health Monitoring. Search on Bibsonomy ICMENS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
38Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap RC delay metrics for performance optimization. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
38Murat R. Becer, Ibrahim N. Hajj An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling. Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF delay, analytical model, decoupling, Crosstalk noise
38Chris C. N. Chu, Martin D. F. Wong A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
38Chris C. N. Chu, D. F. Wong 0001 A new approach to simultaneous buffer insertion and wire sizing. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF interconnect delay minimization, interconnect area minimization, convex quadratic programming, buffer insertion, wire sizing
37Wenwen Chai, Dan Jiao, Cheng-Kok Koh A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF full wave, integral-equation-based methods, capacitance extraction, direct solver
37Fang Gong, Hao Yu 0001, Lei He 0001 PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF incremental precondition, parallel fast-multipole method, stochastic geometrical moments, capacitance extraction
37Vittorio Ricchiuti Power Bus Signal Integrity Improvement and EMI Mitigation on Multilayer High-Speed Digital PCBs with Embedded Capacitance. Search on Bibsonomy IEEE Trans. Mob. Comput. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Embedded capacitance, power bus, power/ground layers, power supply decoupling, electric field strength, S-parameters
37Wei Hong II, Weikai Sun, Zhenhai Zhu, Hao Ji, Ben Song, Wayne Wei-Ming Dai A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF 3D VLSI interconnects, DRT, Dimension Reduction Technique, FastCap, SPICELINK, dielectric layers, parallel signal lines, VLSI, capacitance extraction
36Mosaddequr Rahman, Sazzadur Chowdhury A Highly accurate method to calculate capacitance of MEMS sensors with circular membranes. Search on Bibsonomy EIT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
36Wangyang Zhang, Wenjian Yu, Zeyi Wang, Zhiping Yu, Rong Jiang, Jinjun Xiong An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Liu Cai-feng, Wang Zhong-yu A Novel Capacitance-Match Method for EAS Responder. Search on Bibsonomy CSSE (6) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud Impact of dummy filling techniques on interconnect capacitance and planarization in nano-scale process technology. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF design for manufacturability, dummy fill
36Glenn H. Chapman, Vijay K. Jain Defect Tolerance for a Capacitance Based Nanoscale Biosensor. Search on Bibsonomy DFT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Nima Shahbazi, Hamid Sarbazi-Azad Accelerating 3-D capacitance extraction in deep sub-micron VLSI design using vector/parallel computing. Search on Bibsonomy ICPADS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
36Tadashi Suetsugu, Marian K. Kazimierczuk Output Characteristics of Class E Amplifier With Nonlinear Shunt Capacitance Versus Supply Voltage. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
36Hua Xiang 0001, Kai-Yuan Chao, Martin D. F. Wong An ECO routing algorithm for eliminating coupling-capacitance violations. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
36Wenjian Yu, Mengsheng Zhang, Zeyi Wang Efficient 3-D extraction of interconnect capacitance considering floating metal fills with boundary element method. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
36Norberto Flores, Angel Fernando Kuri Morales, Carlos Gamio An Application of Neural Networks for Image Reconstruction in Electrical Capacitance Tomography Applied to Oil Industry. Search on Bibsonomy CIARP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
36Guoqing Chen, Eby G. Friedman Effective capacitance of RLC loads for estimating short-circuit power. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
36Sani R. Nassif, Kanak Agarwal, Emrah Acar Methods for estimating decoupling capacitance of nonswitching circuit blocks. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
36Su-Jeong Sim, Jeongmin Park, Sung Min Park 0001 A 1.8V, 60dB Omega 11 GHz transimpedance amplifier with strong immunity to input parasitic capacitance. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
36Randy Bach, Bob Davis, Rich Laubhan Improvements to CBCM (Charge-Based Capacitance Measurement) for Deep Submicron CMOS Technology. Search on Bibsonomy ISQED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
36Shabbir H. Batterywala, Rohit Ananthakrishna, Yansheng Luo, Alex Gyure A Statistical Method for Fast and Accurate Capacitance Extraction in the Presence of Floating Dummy Fills. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
36Grzegorz Tosik, Zbigniew Lisik, Malgorzata Langer, Janusz Wozny Simulation of Parasitic Interconnect Capacitance for Present and Future ICs. Search on Bibsonomy International Conference on Computational Science (1) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
36Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue Effective capacitance for gate delay with RC loads. Search on Bibsonomy ISCAS (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
36Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
36Wenjian Yu, Zeyi Wang, Xianlong Hong Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics. Search on Bibsonomy ICCD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
36Sudhakar Bobba, Ibrahim N. Hajj Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits. Search on Bibsonomy ISCAS (5) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
36Jessica Qian, Satyamurthy Pullela, Lawrence T. Pillage Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
36Tai-Yu Chou, Zoltan J. Cendes Capacitance calculation of IC packages using the finite element method and planes of symmetry. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
36Colin C. McAndrew, Bijan K. Bhattacharyya, Omar Wing A Cinfinity-continuous depletion capacitance model. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
36Taoyun Wang, Joseph R. Mautz, Roger F. Harrington The excess capacitance of a microstrip via in a dielectric substrate. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
36C. C. Christara, Elias N. Houstis, John R. Rice A parallel spline collocation-capacitance method for elliptic partial differential equations. Search on Bibsonomy ICS The full citation details ... 1988 DBLP  DOI  BibTeX  RDF VAX
33Jun Yang 0002, Rajiv Gupta 0001, Chuanjun Zhang Frequent value encoding for low power data buses. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF I/O pin capacitance, Low power data buses, internal capacitance, encoding, switching
32Youmin Guo, Zhenrui Peng Comparative Study on Three Voidage Measurement Methods for Two-Phase Flow. Search on Bibsonomy ISNN (3) The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Voidage measurement, Electrical Capacitance Tomography (ECT), Ant System Algorithm (ASA), Genetic Algorithm (GA), Least Squares Support Vector Machine (LS-SVM)
32Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee Prospect of ballistic CNFET in high performance applications: Modeling and analysis. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, process variability, circuit performance
32Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee Modeling and analysis of circuit performance of ballistic CNFET. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, circuit performance
32Anantha P. Chandrakasan Ultra low power digital signal processing. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF ultra low power digital signal processing, portable wireless device, capacitance minimization, spatial signal correlations, temporal signal correlations, re-synchronization, operation reduction, 1 V, logic design, DSP, power consumption, switching, integrated circuit design, voltage scaling, digital signal processing chips, circuit optimisation, circuit design, data representation, circuit optimization, glitching, architecture optimization
30Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer Power-delay optimization in VLSI microprocessors by wire spacing. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Wire spacing, power optimization, interconnect optimization, delay-optimization
30Zheng Li, Ahalapitiya H. Jayatissa, Lash Mapa, Ezzatollah Salari, A. C. Jayasuriya Electrochemical sensors for detection of biomolecules. Search on Bibsonomy EIT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
30Kang-Yeob Park, Wonseok Oh 0003, Boo-Young Choi, Jung-Won Han, S. M. Park A 4-channel 12.5Gb/s Common-Gate Transimpedance Amplifier Array for DVI/HDMI Applications. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
30Pilok Lim, Taewhan Kim Thermal-aware high-level synthesis based on network flow method. Search on Bibsonomy CODES+ISSS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF power consumption, temperature, binding
30Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. Search on Bibsonomy SLIP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF delay-balanced, minimal-power, interconnects, repeaters
30K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
30Jason Helge Anderson, Farid N. Najm Power estimation techniques for FPGAs. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
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open data data released under the ODC-BY 1.0 license