Search results for "circuit-level"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
40	Saket Srivastava, Sanjukta Bhanja	Hierarchical Probabilistic Macromodeling for QCA Circuits.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	QCA computing, QCA macromodel, Bayesian networks, Quantum-dot Cellular Automata, probabilistic computing
37	Wolfgang Borutzky	Combining Behavioral Block Diagram Modelling with Circuit Simulation.	EUROCAST	1989	DBLP DOI BibTeX RDF	mixed behavioral, circuit-level modelling, electrical macromodels, continuous system simulation, electronic control systems, circuit simulation, functional simulation, block diagrams, signal processing systems
28	Raoul F. Badaoui, Ranga Vemuri	Analog VLSI circuit-level synthesis using multi-placement structures.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
25	Basab Datta, Wayne P. Burleson	Circuit-level NBTI macro-models for collaborative reliability monitoring.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	macro-models, on-chip sensors, calibration, NBTI
24	Ying Wei 0002, Alex Doboli	Library of structural analog cell macromodels for design of continuous-time reconfigurable Delta Sigma modulators.	ISCAS	2006	DBLP DOI BibTeX RDF
24	David T. Blaauw, Anirudh Devgan, Farid N. Najm	Leakage power: trends, analysis and avoidance.	ASP-DAC	2005	DBLP DOI BibTeX RDF
24	Alan Marchiori, Douglas Hakkarinen, Qi Han 0001, Lieko Earle	Circuit-Level Load Monitoring for Household Energy Management.	IEEE Pervasive Comput.	2011	DBLP DOI BibTeX RDF	circuit-level load monitoring, nonintrusive load monitoring, NILM, ubiquitous computing, pervasive computing, energy savings, energy management, energy measurement
23	Mingjing Chen, Alex Orailoglu	Circuit-level mismatch modelling and yield optimization for CMOS analog circuits.	ICCD	2007	DBLP DOI BibTeX RDF
22	T. M. Mak, Subhasish Mitra	Should Logic SER be Solved at the Circuit Level?	IOLTS	2006	DBLP DOI BibTeX RDF
21	Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi	A design approach for radiation-hard digital electronics.	DAC	2006	DBLP DOI BibTeX RDF	radiation-hard, SEU
20	Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja	Yield-Driven, False-Path-Aware Clock Skew Scheduling.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	performance-related circuit yield loss, circuit-level parameters, DFM, clock skew scheduling
19	Koustav Bhattacharya, Nagarajan Ranganathan	RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits.	VLSI Design	2009	DBLP DOI BibTeX RDF
19	Zbigniew Kalbarczyk, Ravishankar K. Iyer, Gregory L. Ries, Jaqdish U. Patel, Myeong S. Lee, Yuxiao Xiao	Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation.	IEEE Trans. Software Eng.	1999	DBLP DOI BibTeX RDF	Hierarchical simulation, accurate fault modeling, dependability evaluation, fault dictionaries
19	Shambhu J. Upadhyaya, Nandakumar P. Venugopal, Nihal Shastry, Srinivasan Gopalakrishnan, Bharath V. Kuppuswamy, Rana Bhowmick, Prerna Mayor	Design Considerations for High Performance RF Cores Based on Process Variation Study.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Cascode LNA, Corner analysis, Differential CMOS LNA, Phase frequency detector (PFD), Reuse topology, Process variation, Jitter, Phase noise, Noise figure, S-parameters, Monte Carlo analysis
19	Luís Bica Oliveira, Jorge R. Fernandes, Michiel H. L. Kouwenhoven, Chris van den Bos, Chris J. M. Verhoeven	A quadrature relaxation oscillator-mixer in CMOS.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
19	Vittorio Rizzoli, Franco Mastri, Alessandra Costanzo, Diego Masotti	Harmonic-Balance Algorithms for the Circuit-Level Nonlinear Analysis of UWB Receivers in the Presence of Interfering Signals.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
19	Drew C. Ness, David J. Lilja	Guiding Circuit Level Fault-Tolerance Design with Statistical Methods.	DATE	2008	DBLP DOI BibTeX RDF
18	Yen-Jen Chang, Chia-Lin Yang, Feipei Lai	A power-aware SWDR cell for reducing cache write power.	ISLPED	2003	DBLP DOI BibTeX RDF	circuit-level, write power, low power, cache, SRAM
18	Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang	A realistic fault model for flash memories.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	NAND circuits, faulty behavior classification, NAND-type flash memory, SPICE models, flash cell models, circuit-level faulty behavior simulation, testing, fault model, fault modeling, fault simulation, flash memories, flash memories, circuit analysis computing, SPICE, integrated memory circuits
18	Weiguang Sheng, Liyi Xiao, Zhigang Mao	Versatile and Efficient Techniques for Speeding-Up Circuit Level Simulated Fault-Injection Campaigns.	PRDC	2008	DBLP DOI BibTeX RDF
17	Santanu Dutta, Wayne H. Wolf, Andrew Wolfe	VLSI issues in memory-system design for video signal processors.	ICCD	1995	DBLP DOI BibTeX RDF	VLSI issues, video signal processors, memory-system architectures, circuit-level issues, register-cache based hierarchy, general-purpose programmable microprocessors, VLSI, system architecture, utilization, memory architecture, memory architecture, video signal processing, area, cycle time, memory-system design
17	Shingo Watanabe, Masanori Hashimoto, Toshinori Sato	A case for exploiting complex arithmetic circuits towards performance yield enhancement.	ISQED	2009	DBLP DOI BibTeX RDF
17	Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy 0001	Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
17	Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy 0001	Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits.	DATE	2005	DBLP DOI BibTeX RDF
17	Mohammad Moradinezhad Maryan, Majid Amini Valashani, Seyed Javad Azhari	A New Circuit-Level Technique for Leakage and Short-Circuit Power Reduction of Static Logic Gates in 22-nm CMOS Technology.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
17	Feifei He, Cher Ming Tan	Circuit level interconnect reliability study using 3D circuit model.	Microelectron. Reliab.	2010	DBLP DOI BibTeX RDF
17	Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer	Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
17	Natarajan Mahadeva Iyer, M. K. Radhakrishnan	ESD Reliability Challenges for RF/Mixed Signal Design & Processing.	VLSI Design	2003	DBLP DOI BibTeX RDF
17	Chao Yan 0001, Mark R. Greenstreet	Circuit Level Verification of a High-Speed Toggle.	FMCAD	2007	DBLP DOI BibTeX RDF
16	Terry Lee, Weitong Chuang, Ibrahim N. Hajj, W. Kent Fuchs	Circuit-level dictionaries of CMOS bridging faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
16	Wendy Belluomini, Chris J. Myers, H. Peter Hofstee	Timed circuit verification using TEL structures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
15	Rajat Subhra Chakraborty, Swarup Bhunia	A study of asynchronous design methodology for robust CMOS-nano hybrid system design.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	CMOS-nano co-design, dual-rail circuits, logic degradation, nano-scale crossbar, Asynchronous design, robust design, micropipelines
15	Peter Odryna, Kevin Nazareth, Carl Christensen	A workstation-mixed model circuit simulator.	DAC	1986	DBLP DOI BibTeX RDF
14	Rikard Gannedahl, Javad Bagheri Asli, Henrik Sjöland, Atila Alvandpour	A Modular System-level Testbench for 6G Beamforming Applications with Near Circuit-Level Fidelity.	NEWCAS	2023	DBLP DOI BibTeX RDF
14	Victor M. van Santen, Hussam Amrouch, Jörg Henkel	Modeling and Mitigating Time-Dependent Variability From the Physical Level to the Circuit Level.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
14	Khalid Shahbar, Nur Zincir-Heywood	Benchmarking two techniques for Tor classification: Flow level and circuit level classification.	CICS	2014	DBLP DOI BibTeX RDF
14	Zhe Zhang 0002, Ole C. Thomsen, Michael A. E. Andersen	Discontinuous PWM Modulation Strategy With Circuit-Level Decoupling Concept of Three-Level Neutral-Point-Clamped (NPC) Inverter.	IEEE Trans. Ind. Electron.	2013	DBLP DOI BibTeX RDF
14	Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy 0001	Tolerance to Small Delay Defects by Adaptive Clock Stretching.	IOLTS	2007	DBLP DOI BibTeX RDF
14	Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell	Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program.	VLSI Design	2003	DBLP DOI BibTeX RDF
14	Yiran Chen 0001, Hai Li 0001, Xiaobin Wang, Wenzhong Zhu, Wei Xu 0021, Tong Zhang 0002	Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM.	ISLPED	2010	DBLP DOI BibTeX RDF	STT-RAM, emerging memory, spintronic
14	Tom J. Kazmierski, Dafeng Zhou, Bashir M. Al-Hashimi	Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge density.	DATE	2008	DBLP DOI BibTeX RDF
14	Mauro Olivieri, Mirko Scarana, Simone Smorfa	Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
14	Zhuo Li 0001, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker	A Circuit Level Fault Model for Resistive Opens and Bridges.	VTS	2003	DBLP DOI BibTeX RDF
14	Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury	Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
14	Hua Tang	Post-optimization of Delta-Sigma modulators considering circuit non-idealities.	ISCAS	2008	DBLP DOI BibTeX RDF
14	Rufus H. Cofer, T. J. Sanders	STADIUM: a new tool for high assurance in systems design.	ICECCS	1995	DBLP DOI BibTeX RDF	STADIUM high assurance tool, large system development, systems engineering phase, operational variabilities, system performance levels, search effects, worst-case system design, statistically based system level simulation, statistically based subsystem level simulation, dual-use technologies, defense conversions, complex commercial systems, design of experiments methodology, circuit level variabilities, subsystem level variabilities, system level variabilities, simulation, software tools, software tool, systems design, systems analysis, systems engineering, system performances, design of experiments, manufacturing variabilities, complex system development
14	Zhimin Chen 0002, Syed Haider, Patrick Schaumont	Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects.	ISA	2009	DBLP DOI BibTeX RDF
13	Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasaki, Tetsu Hosoki, Masaya Sumita	Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier".	ASP-DAC	2007	DBLP DOI BibTeX RDF
13	Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi	Error Tolerance of DNA Self-Healing Assemblies by Puncturing.	DFT	2007	DBLP DOI BibTeX RDF
13	Mark R. Greenstreet	Verifying VLSI Circuits.	ATVA	2009	DBLP DOI BibTeX RDF
13	Xin Fu, Tao Li, José A. B. Fortes	Combined circuit and microarchitecture techniques for effective soft error robustness in SMT processors.	DSN	2008	DBLP DOI BibTeX RDF
13	Rajesh Garg, Sunil P. Khatri	A novel, highly SEU tolerant digital circuit design approach.	ICCD	2008	DBLP DOI BibTeX RDF
13	Xiangdong Xuan, Adit D. Singh, Abhijit Chatterjee	Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	IC reliability, reliability simulation, design for reliability, interconnect, electromigration, defect modeling
13	Taikyeong T. Jeong, Jaemyoung Lee	Design and Verification for Hierarchical Power Efficiency System (HPES) Design Techniques Using Low Power CMOS Digital Logic.	International Conference on Computational Science (1)	2006	DBLP DOI BibTeX RDF
13	Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David T. Blaauw, Trevor N. Mudge	Circuit-aware architectural simulation.	DAC	2004	DBLP DOI BibTeX RDF	circuit simulation, architectural simulation, high-performance simulation, computer system simulation
13	Sung-Mo Kang	On-chip thermal engineering for peta-scale integration.	ISPD	2002	DBLP DOI BibTeX RDF
13	Marcelo Lubaszewski, Salvador Mir, Vladimir Kolarik, C. Nielsen, Bernard Courtois	Design of self-checking fully differential circuits and boards.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
13	Robert P. Kurshan, Kenneth L. McMillan	Analysis of digital circuits through symbolic reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
13	William S. Beckett	MOS circuit models in Network C.	DAC	1986	DBLP DOI BibTeX RDF	C
12	Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton	On breakable cyclic definitions.	ICCAD	2004	DBLP DOI BibTeX RDF
12	Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar	Reducing leakage in a high-performance deep-submicron instruction cache.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
12	Suganth Paul, Rajesh Garg, Sunil P. Khatri, Sheila Vaidya	Design and implementation of a sub-threshold BFSK transmitter.	ISQED	2009	DBLP DOI BibTeX RDF
12	Zhimin Chen 0002, Patrick Schaumont	Slicing Up a Perfect Hardware Masking Scheme.	HOST	2008	DBLP DOI BibTeX RDF
12	Kazuki Nakada, Jun Igarashi, A. Tetsuya, Hatsuo Hayashi	Noise Effects on Performance of Signal Detection in an Analog VLSI Resonate-And Fire Neuron.	ISCAS	2006	DBLP DOI BibTeX RDF
12	R. Jancke, P. Schwarz	Supporting analog synthesis by abstracting circuit behavior using a modeling methodology.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Haleh Vahedi, Radu Muresan, Stefano Gregori	On-chip current flattening circuit with dynamic voltage scaling.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy 0001	Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
12	Shaolei Quan, Qiang Qiang, Chin-Long Wey	Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
12	Sanjukta Bhanja, N. Ranganathan	Switching activity estimation of VLSI circuits using Bayesian networks.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
12	Santanu Mahapatra, Kaustav Banerjee, Florent Pegeon, Adrian M. Ionescu	A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits.	ICCAD	2003	DBLP DOI BibTeX RDF
12	Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy 0001	Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling.	DAC	2003	DBLP DOI BibTeX RDF	doping profiles, leakage, tunneling, threshold voltage
12	Ayman A. Fayed, Magdy A. Bayoumi	A low power 10-transistor full adder cell for embedded architectures.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
12	Ramakrishna Voorakaranam, Abhijit Chatterjee	Hierarchical Test Generation for Analog Circuits Using Incremental Test Development.	VTS	1999	DBLP DOI BibTeX RDF
12	Christer Svensson, Atila Alvandpour	Low power and low voltage CMOS digital circuit techniques.	ISLPED	1998	DBLP DOI BibTeX RDF	low power, CMOS, digital circuits, low voltage
12	Narain D. Arora, Kartik V. Raol, Reinhard Schumann, Llanda M. Richardson	Modeling and extraction of interconnect capacitances for multilayer VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
11	Taniya Siddiqua, Sudhanva Gurumurthi	A multi-level approach to reduce the impact of NBTI on processor functional units.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	reliability, NBTI
11	Ajay Joshi, Jeffrey A. Davis	Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	interconnect sharing, time division, wave-pipelining
11	Atul Maheshwari, Wayne P. Burleson, Russell Tessier	Trading off Reliability and Power-Consumption in Ultra-low Power Systems.	ISQED	2002	DBLP DOI BibTeX RDF
11	Young Hwan Kim, Seung Ho Hwang, A. Richard Newton	Electrical-logic simulation and its applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
10	Anqi Gong, Sebastian Cammerer, Joseph M. Renes	Toward Low-latency Iterative Decoding of QLDPC Codes Under Circuit-Level Noise.	CoRR	2024	DBLP DOI BibTeX RDF
10	Milad Mehri	A circuit level analysis of power distribution network on a PCB layout exposed to intentional/unintentional electromagnetic threats.	Integr.	2023	DBLP DOI BibTeX RDF
10	V. Bharath Sreenivasulu, Aruna Kumari Neelam, Sekhar Reddy Kola, Jawar Singh, Yiming Li 0005	Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison.	IEEE Access	2023	DBLP DOI BibTeX RDF
10	JongHyun Ko, Jongbeom Kim, TaeGam Jeong, Jaehoon Jeong, Taigon Song	Exploration of Ternary Logic Using T-CMOS for Circuit-Level Design.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
10	Nikita Mirchandani, Yuqing Zhang 0004, Safaa A. Abdelfattah, Marvin Onabajo, Aatmesh Shrivastava	Modeling and Simulation of Circuit-Level Nonidealities for an Analog Computing Design Approach With Application to EEG Feature Extraction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
10	Diptashree Das, Ziyue Xu 0003, Mehdi Nasrollahpour, Isabel Martos-Repath, Mohsen Zaeimbashi, Adam Khalifa, Ankit Mittal, Sydney S. Cash, Nian Xiang Sun, Aatmesh Shrivastava, Marvin Onabajo	Circuit-Level Modeling and Simulation of Wireless Sensing and Energy Harvesting With Hybrid Magnetoelectric Antennas for Implantable Neural Devices.	IEEE Open J. Circuits Syst.	2023	DBLP DOI BibTeX RDF
10	Sunitha Bhukya, Bheema Rao Nistala	Design optimization of junctionless bottom spacer tapered FinFET: Device to circuit level implementation.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
10	Pamela A. Riggs, Barry K. Gilbert, Erik S. Daniel	Efficient Circuit-Level Implementation of Knuth-Based Balanced and Nearly-Balanced Codes.	CoRR	2023	DBLP DOI BibTeX RDF
10	Md Hasibul Amin, Mohammed E. Elbtity, Ramtin Zand	IMAC-Sim: A Circuit-level Simulator For In-Memory Analog Computing Architectures.	CoRR	2023	DBLP DOI BibTeX RDF
10	Mashrafi Alam Kajol, Mohammad Mezanur Rahman Monjur, Qiaoyan Yu	A Circuit-Level Solution for Secure Temperature Sensor.	Sensors	2023	DBLP DOI BibTeX RDF
10	Badreddine Zerroumda, Hichem Ferhati, Fayçal Djeffal, Adel Bendjerad	A New Gate-Trench Junctionless SiC Power MOSFET: Performance Assessement and Circuit Level Investigation.	CCE	2023	DBLP DOI BibTeX RDF
10	Florian Klemme, Sami Salamin, Hussam Amrouch	Upheaving Self-Heating Effects from Transistor to Circuit Level using Conventional EDA Tool Flows.	DATE	2023	DBLP DOI BibTeX RDF
10	Md Hasibul Amin, Mohammed E. Elbtity, Ramtin Zand	IMAC-Sim: : A Circuit-level Simulator For In-Memory Analog Computing Architectures.	ACM Great Lakes Symposium on VLSI	2023	DBLP DOI BibTeX RDF
10	Jianwen Lin, Linlin Cai, Yutao Chen, Haoyu Zhang, Wangyong Chen	Machine Learning-Assisted Single-Event Transient Model of 12nm FinFETs for Circuit-Level Simulation.	ASICON	2023	DBLP DOI BibTeX RDF
10	Jeonggyu Yang, Hyundong Lee, Jaehoon Jeong, Taehak Kim, Sin-Hyung Lee, Taigon Song	Circuit-Level Exploration of Ternary Logic Using Memristors and MOSFETs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
10	Zilong Shen, Yize Wang, Yunhao Li, Xing Zhang 0002, Yuan Wang 0001	A Scalable Model for Snapback Characteristics of Circuit-Level ESD Simulation.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
10	I. Munavar Sheriff, R. Sakthivel 0002	Mathematical and Circuit Level Analysis Interpretation and Recommendations on Neuron Models.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
10	N. Aruna Kumari, Pothupogu Prithvi	Device and circuit-level performance comparison of GAA nanosheet FET with varied geometrical parameters.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
10	Fayçal Djeffal, Hichem Ferhati	New Ge-gate IR Phototransistor based on Doping Engineering Aspect: Photodetection Properties and Circuit Level Investigation.	CCE	2022	DBLP DOI BibTeX RDF
10	Jose Cayo, Ioannis Vourkas, Antonio Rubio 0001	A Circuit-Level SPICE Modeling Strategy for the Simulation of Behavioral Variability in ReRAM.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
10	Sebastian Mihai Ardelean, Mihai Udrescu	Circuit level implementation of the Reduced Quantum Genetic Algorithm using Qiskit.	SACI	2022	DBLP DOI BibTeX RDF