Search results for "field-programmable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
70	Wei-Kang Huang, Fabrizio Lombardi	An approach for testing programmable/configurable field programmable gate arrays.	VTS	1996	DBLP DOI BibTeX RDF	behavioral characterization, single fault detection, disjoint one-dimensional arrays, unilateral horizontal connections, common vertical input lines, array testing, logic blocks, field programmable gate arrays, field programmable gate arrays, VLSI, logic testing, integrated circuit testing, stuck-at fault, FPGA testing, functional fault, hybrid fault model
65	Bradly K. Fawcett, J. Watson	Reconfigurable Processing With Field Programmable Gate Arrays.	ASAP	1996	DBLP DOI BibTeX RDF	reconfigurable processing, internal architecture, computationally-intensive tasks, programmable solution, XC6200 FPGA architecture, SRAM control store, on-chip memory capability, field programmable gate arrays, interconnections, reconfigurable architectures, processors, coprocessors, coprocessors, SRAM chips, SRAM-based field programmable gate arrays
63	Vi Chi Chan, David Lewis	Hierarchical partitioning for field-programmable systems.	ICCAD	1997	DBLP DOI BibTeX RDF	FPGA partitioning problems, circuit structures, field-programmable systems, partitioning tree, recursive bipartitioning algorithm, field programmable gate arrays, VLSI, quality, logic CAD, hierarchical partitioning
58	Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto	Universal test complexity of field-programmable gate arrays.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	universal test complexity, arbitrary logic circuits, sequential loading, random access loading, programming schemes, block-sliced loading, configuration memory cells, field programmable gate arrays, field-programmable gate array, computational complexity, fault diagnosis, logic testing, design for testability, fault model, logic CAD, table lookup, look-up tables, automatic test software, C-testable
58	Zhuo Gao, Ji Luo 0003, Hu Huang 0001, Wei Zhang, Joseph B. Bernstein	Reliable Laser Programmable Gate Array Technology.	ISQED	2002	DBLP DOI BibTeX RDF	Laser Programmable Gate Array (LPGA), Laser Field-Programmable Gate Array (LFPGA), MakeLink technology, laser-induced/laser programmable anti-fuse, digital ASIC design, low electrical resistance anti-fuse, Field-Programmable Gate Array (FPGA)
56	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne	Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	Field Programmable Compressor Tree (FPCT), compressor tree, Field Programmable Gate Array (FPGA)
56	Jiri Stehlik, Daniel Becvar	Field Programmable Mixed-Signal Arrays (FPMA) Using Versatile Current/Voltage Conveyor Structures. (PDF / PS)	PWC	2007	DBLP DOI BibTeX RDF	Field Programmable Mixed-Signals Array, Programmable Universal Current Conveyor, Field Programmable Analog Array
56	Hardy J. Pottinger, Chien-Yuh Lin	Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education
54	Yao-Wen Chang, D. F. Wong 0001, C. K. Wong	Design and analysis of FPGA/FPIC switch modules.	ICCD	1995	DBLP DOI BibTeX RDF	FPGA/FPIC switch modules, routing resources, FPIC, network-flow techniques, field programmable interconnect chip, field programmable gate arrays, FPGA, field programmable gate arrays, logic design, heuristic algorithm, programmable logic arrays, routability
54	Uwe Meyer-Bäse, Antonio García 0001, Fred J. Taylor	Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	field-programmable logic (FPL), complex programmable logic devices (CPLD), zero-IF filter, field programmable gate array (FPGA), digital signal processing (DSP), residue number system (RNS), channelizer
52	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne	Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	field programmable counter array (FPCA), FPGA
52	Frank-Michael Renner, Jürgen Becker 0001, Manfred Glesner	Field Programmable Communication Emulation and Optimization for Embedded System Design.	FPL	2000	DBLP DOI BibTeX RDF	architecture-precise rapid prototyping, field programmable emulation, Hardware/software codesign, real-time embedded systems
47	Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici	Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!).	VTS	1996	DBLP DOI BibTeX RDF	BIST architecture, programmable logic blocks, field programmable gate arrays, VLSI, logic testing, built-in self test, built-in self-test, integrated circuit testing, automatic testing, FPGA testing, field programmable gate array testing
47	Wei-Kang Huang, Xiao-Tao Chen, Fabrizio Lombardi	On the diagnosis of programmable interconnect systems: Theory and application.	VTS	1996	DBLP DOI BibTeX RDF	field programmable interconnect system, switch grid, FPIS, Xilinx 3000, field programmable gate arrays, FPGA, fault diagnosis, logic testing, diagnosis, integrated circuit interconnections
47	John Y. Oliver, Venkatesh Akella	Improving DSP Performance with a Small Amount of Field Programmable Logic.	FPL	2003	DBLP DOI BibTeX RDF
47	Paul Chow, P. Glenn Gulak	A Field-Programmable Mixed-Analog-Digital Array.	FPGA	1995	DBLP DOI BibTeX RDF
47	Gerardo Orlando, Christof Paar	A Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms.	FCCM	1999	DBLP DOI BibTeX RDF	Galois Fields multiplier, field programmable gate array application, cryptography, elliptic curve cryptography
46	Yen-Tai Lai, Ping-Tsung Wang	Hierarchical interconnection structures for field programmable gate arrays.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
43	Seyed-Hosein Attarzadeh-Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne	Design space exploration for field programmable compressor trees.	CASES	2008	DBLP DOI BibTeX RDF	design space exploration (dse), field programmable compressor tree (fpct)
43	Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton	A synthesizable datapath-oriented embedded FPGA fabric.	FPGA	2007	DBLP DOI BibTeX RDF	embedded block, field programmable gate array, system-on-chip, synthesis, integrated circuit, datapath
43	I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, Tyson S. Hall, David V. Anderson	Mapping algorithm for large-scale field programmable analog array.	ISPD	2005	DBLP DOI BibTeX RDF	floating gates, mapping, field programmable analog array
43	Dinesh Bhatia, James Haralambides	Resource requirements for field programmable interconnection chips.	VLSI Design	1995	DBLP DOI BibTeX RDF	field programmable interconnection chips, n-permutation graph, network property, routing delays, programmable switches, routing paths, specific I/O permutations, user-configured interconnection, VLSI, VLSI, graph theory, network routing, permutation networks, integrated circuit interconnections, Benes network
43	Koray Öner, Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Krishnan Ramamurthy, Michel Dubois 0001	The Design of RPM: An FPGA-based Multiprocessor Emulator.	FPGA	1995	DBLP DOI BibTeX RDF	field-programmable gate arrays, VHDL, rapid prototyping, shared-memory multiprocessors, logic emulation, message-passing multicomputers
43	Neil W. Bergmann, Yuk Ying Chung	Video Compression on FPGA-Based Custom Computers.	ICIP (1)	1997	DBLP DOI BibTeX RDF	FPGA-based custom computers, 2D DCT algorithms, Scalable Parallel Architecture for Concurrency Experiments, field programmable gate arrays, field programmable gate array, video compression, experimental result, SPACE, workstation, distributed arithmetic, super-computer, processing speed
43	Yoshinori Yamaguchi, Kenji Toda, Kenji Nishida, Eiichi Takahashi	CODA-R: a reconfigurable testbed for real-time parallel computation.	RTCSA	1997	DBLP DOI BibTeX RDF	CODA-R, reconfigurable testbed, real-time parallel computation, reconfigurable field programmable gate arrays, total execution time, prototype reconfigurable real-time parallel system, real-time parallel architecture, field programmable gate arrays, real-time system, processing elements, computing engine
43	Shriram Kulkarni, Pinaki Mazumder, George I. Haddad	A high-speed 32-bit parallel correlator for spread spectrum communication.	VLSI Design	1996	DBLP DOI BibTeX RDF	pseudonoise codes, radio equipment, high speed pipelined digital parallel correlator, lattice field programmable gate array, 87 MHz, 11.5 ns, field programmable gate arrays, parallel processing, data stream, correlators, CDMA, pipeline processing, CMOS integrated circuit, CMOS digital integrated circuits, transceiver, spread spectrum communication, spread spectrum communication, digital radio, 32 bit, PN sequence
43	H. A. Xie, Kevin E. Forward, K. M. Adams, Suthikshn Kumar	An SBus Multi-Tracer and its applications.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	SBus Multi Tracer, SBus monitoring board, logic analyzer, bus analyzer, trace length, board memory, multi occurrences, trigger patterns, multiple partitions, tracing memory, systematic timing information, pattern occurrences, triggering patterns, SUN SPARC station, field programmable gate arrays, Field Programmable Gate Array, FPGA, logic testing, automatic test equipment, system buses, timing diagrams, computerised monitoring
43	John Schewel, Michael Thornburg, Steve Casselman	Transformable computers & hardware object technology.	IPPS	1995	DBLP DOI BibTeX RDF	transformable computers, hardware object technology, reconfigurable aspects, computationally intensive software algorithms, on-the-fly use, field programmable gate arrays, field programmable gate arrays, programming, reconfigurable architectures, programmable logic arrays, hardware design, performance gain
43	Akihiro Tsutsui, Toshiaki Miyazaki, Kazuhisa Yamada, Naohisa Ohta	Special purpose FPGA for high-speed digital telecommunication systems.	ICCD	1995	DBLP DOI BibTeX RDF	special purpose FPGA, high-speed digital telecommunication systems, high-speed transport data processing, inter-chip connection mechanism, dedicated CAD system, field programmable gate arrays, field programmable gate array, programmable logic arrays, digital communication
43	Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose	Logic synthesis for a single large look-up table.	ICCD	1995	DBLP DOI BibTeX RDF	single large look-up table, LUT-based field-programmable gate array architectures, simulation time minimisation, compile-code, software simulation, field programmable gate arrays, Boolean function, logic design, logic synthesis, hardware accelerator, programmable logic arrays, table lookup, logic simulation, FPGA architectures, logic functions, on-chip memory, memory constraint
43	Joseph L. Ganley, James P. Cohoon	Thumbnail rectilinear Steiner trees.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	full-set decomposition algorithm, minimum-length set, thumbnail rectilinear Steiner tree problem, VLSI placement algorithms, geometric partitioning, field programmable gate arrays, field-programmable gate arrays, VLSI, dynamic programming, network topology, logic CAD, trees (mathematics), network routing, circuit layout CAD, global routing, line segments
43	Jae-Tack Yoo, Erik Brunvand, Kent F. Smith	Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	automatic rapid prototyping, semicustom VLSI circuits, Actel FPGAs, cell-matrix based environment, synchronous pipelined version, asynchronous pipelined version, field programmable gate arrays, field programmable gate arrays, VLSI, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, array multiplier, CMOS IC
43	Jean-Francois Guillaud, Max Roger Pokam, Gérard Michel	An ATM-Based Multimedia Integrated Manufacturing System .	HPDC	1995	DBLP DOI BibTeX RDF	ATM-based multimedia integrated manufacturing system, high-speed communication technologies, intelligent network interface board, field programmable gate array component, high speed communication links, field programmable gate arrays, protocols, protocols, asynchronous transfer mode, multimedia systems, multimedia applications, computer integrated manufacturing, real time distributed systems
43	Dinesh Bhatia, James Haralambides	Resource requirements and layouts for field programmable interconnection chips.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
41	David W. Trainor, Roger F. Woods	Architectural Synthesis and Efficient Circuit Implementation for Field Programmable Gate Arrays.	FPL	1996	DBLP DOI BibTeX RDF
41	Abdellah Touhafi, Wouter Brissinck, Erik F. Dirkx	The Implementation of a Field Programmable Logic Based Co-Processor for the Acceleration of Discrete Event Simulators.	FPL	1996	DBLP DOI BibTeX RDF
41	C. P. Cowen, S. Monaghan	Performance Characteristics of the Monte-Carlo Clustering Processor (MCCP) - a Field Programmable Logic- based Custom Computing Machine.	FPL	1994	DBLP DOI BibTeX RDF
41	Jo Depreitere, Henk Neefs, Herwig Van Marck, Jan Van Campenhout, Roel Baets, Bart Dhoedt, Hugo Thienpont, Irina Veretennicoff	An Optoelectronic 3-D Field Programmable Gate Array.	FPL	1994	DBLP DOI BibTeX RDF
41	Tsuyoshi Isshiki, Wayne Wei-Ming Dai	Hight-Performance Datapath Implementation on Field-Programmable Multi-Chip Module (FPMCM).	FPL	1994	DBLP DOI BibTeX RDF
41	David C.-L. Lam	Educational Use of Field Programmable Gate Arrays.	FPL	1994	DBLP DOI BibTeX RDF
41	Juan J. Rodríguez-Andina, Jacobo Álvarez, Enrique Mandado	Design of Safety Systems Using Field Programmable Gate Arrays.	FPL	1994	DBLP DOI BibTeX RDF
41	Jouni Isoaho, Arto Nummela, Hannu Tenhunen	Technologies and Utilization fo Field Programmable Gate Arrays.	FPL	1992	DBLP DOI BibTeX RDF
41	Hartmut Surmann, Ansgar Ungering, Karl Goser	Optimized Fuzzy Controller Architecture for Field Programmable Gate Arrays.	FPL	1992	DBLP DOI BibTeX RDF
41	Alberto L. Sangiovanni-Vincentelli	Some Considerations on Field-Programmable Gate Arrays and Their Impact on System Design.	FPL	1992	DBLP DOI BibTeX RDF
40	Diego Pedro Morales, Antonio García 0001, Alberto J. Palma, Miguel A. Carvajal, Encarnación Castillo, Luis F. Capitán-Vallvey	Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration.	FPL	2008	DBLP DOI BibTeX RDF
40	John W. Lockwood, Naji Naufel, Jonathan S. Turner, David E. Taylor	Reprogrammable network packet processing on the field programmable port extender (FPX).	FPGA	2001	DBLP DOI BibTeX RDF	Internet, FPGA, routing, network, ATM, modularity, reconfiguration, processing, IP, hardware, packet
40	John W. Lockwood, Jonathan S. Turner, David E. Taylor	Field programmable port extender (FPX) for distributed routing and queuing.	FPGA	2000	DBLP DOI BibTeX RDF
38	Marios Iliopoulos, Theodore Antonakopoulos 0001	Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits.	FPL	2000	DBLP DOI BibTeX RDF
38	Behzad Mahdavikhah, Ramin Mafi, Shahin Sirouspour, Nicola Nicolici	Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture.	FPGA	2010	DBLP DOI BibTeX RDF	conjugate gradient (CG), finite-element modeling (FEM), field-programmable gate array (FPGA)
38	Qiang Wang, Subodh Gupta, Jason Helge Anderson	Clock power reduction for virtex-5 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
38	Didier Keymeulen, Adrian Stoica, Ricardo Salem Zebulum, Srinivas Katkoori, Pradeep Fernando, Hariharan Sankaran, Mohammad M. Mojarradi, Taher Daud	Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core.	ICES	2008	DBLP DOI BibTeX RDF	Self-Healing and Compensation, Self-reconfigurable, Field Programmable Analog Array
38	Javier Ramírez 0001, Antonio García 0001, Uwe Meyer-Bäse, Fred J. Taylor, Antonio Lloris-Ruíz	Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	field-programmable logic, digital signal processing, discrete wavelet transform, residue number system, distributed arithmetic
38	Paul Berube, Ashley Zinyk, José Nelson Amaral, Mike H. MacGregor	The Bank Nth Chance Replacement Policy for FPGA-Based CAMs.	FPL	2003	DBLP DOI BibTeX RDF	multizone cache, field programmable gate array, cache memories, memory systems, content addressable memories, replacement policy, digital design, Internet routing
38	Amit Chowdhary, John P. Hayes	General technology mapping for field-programmable gate arrays based on lookup tables.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	lookup tables (LUTs), multiple-LUT blocks, nonrooted trees, field-programmable gate arrays, mapping, synthesis, circuit partitioning, rooted trees, Basis
38	Pedro C. Diniz, Joonseok Park	Data reorganization engines for the next generation of system-on-a-chip FPGAs.	FPGA	2002	DBLP DOI BibTeX RDF	field-programmable-gate-arrays (FPGAs), high-level synthesis, data reorganization
38	Sriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne P. Burleson	A dynamically reconfigurable adaptive viterbi decoder.	FPGA	2002	DBLP DOI BibTeX RDF	field-programmable-gate-arrays (FPGAs), high-level synthesis, data reorganization
38	Stephen D. Scott 0001, Ashok Samal, Sharad C. Seth	HGA: A Hardware-Based Genetic Algorithm.	FPGA	1995	DBLP DOI BibTeX RDF	performance acceleration, performance evaluation, field programmable gate arrays, function optimization, parallel genetic algorithms
38	S. A. Rahim, Laurence E. Turner	A Field Programmable Bit-Serial Digital Signal Processor.	IWSOC	2004	DBLP DOI BibTeX RDF
38	Sushil Chandra Jain, Anshul Kumar, Shashi Kumar	Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards.	FPL	2000	DBLP DOI BibTeX RDF
36	Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, Kees A. Vissers	Field-Programmable Custom Computing Machines - A Taxonomy -.	FPL	2002	DBLP DOI BibTeX RDF
36	Tom Kean	Secure Configuration of Field Programmable Gate Arrays.	FPL	2001	DBLP DOI BibTeX RDF
35	Luca Macchiarulo, Consolato F. Caccamo, Davide Pandini	A comparison between mask- and field-programmable routing structures on industrial FPGA architectures.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	mask-programmable, FPGA, routing, interconnect architectures
35	A. Manoj Kumar, B. Jayaram 0002, V. Kamakoti 0001	SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis.	FPGA	2004	DBLP DOI BibTeX RDF
35	Binlin Guo, Jiarong Tong	A SC-based novel configurable analog cell.	FPGA	2003	DBLP DOI BibTeX RDF
35	Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama	High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph.	ISVLSI	2002	DBLP DOI BibTeX RDF	FPGA, Reconfigurable processor, Two-dimensional array, Bit-serial architecture
35	Peter Zipf, Manfred Glesner, Christine Bauer 0002, Hans Wojtkowiak	Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension.	FPL	2002	DBLP DOI BibTeX RDF
35	Tero Rissa, Tommi Mäkeläinen, Jarkko Niittylahti, Jouni Siirtola	Fast Prototyping Using System Emulators.	FPL	1998	DBLP DOI BibTeX RDF
34	Yee Jern Chong, Sri Parameswaran	Flexible multi-mode embedded floating-point unit for field programmable gate arrays.	FPGA	2009	DBLP DOI BibTeX RDF	dual-precision, embedded block, fpu, fpga, floating-point, fpga architecture
34	Theepan Moorthy, Andy Ye	A scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate Arrays.	FPL	2008	DBLP DOI BibTeX RDF
34	James W. Crouch, Hiren J. Patel, Yong C. Kim, Robert W. Bennington	Creating unique identifiers on field programmable gate arrays using natural processing variations.	FPL	2008	DBLP DOI BibTeX RDF
34	Ping Chen, Andy Ye	The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays.	FPL	2008	DBLP DOI BibTeX RDF
34	Pedro C. Diniz, Gokul Govindu	Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit.	FPL	2006	DBLP DOI BibTeX RDF
34	Julien Lamoureux, Steven J. E. Wilton	Activity Estimation for Field-Programmable Gate Arrays.	FPL	2006	DBLP DOI BibTeX RDF
34	Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle	A Field Programmable RFID Tag and Associated Design Flow.	FCCM	2006	DBLP DOI BibTeX RDF
34	Andy Gean Ye, Jonathan Rose	Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits.	FPGA	2005	DBLP DOI BibTeX RDF	datapath regularity, reconfigurable fabric, FPGA architecture, routing architecture, area efficiency
34	Arifur Rahman, Vijay Polavarapuv	Evaluation of low-leakage design techniques for field programmable gate arrays.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, leakage power, multiplexer
34	Pak K. Chan, Martine D. F. Schlag	Parallel placement for field-programmable gate arrays.	FPGA	2003	DBLP DOI BibTeX RDF	parallel placement, FPGAs, timing-driven placement, analytical placement
34	Peter Suaris, Dongsheng Wang 0012, Pei-Ning Guo, Nan-Chi Chou	A physical retiming algorithm for field programmable gate arrays.	FPGA	2003	DBLP DOI BibTeX RDF
34	L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti 0001	Testable Clock Routing Architecture for Field Programmable Gate Arrays.	FPL	2003	DBLP DOI BibTeX RDF
34	Deshanand P. Singh, Stephen Dean Brown	Integrated retiming and placement for field programmable gate arrays.	FPGA	2002	DBLP DOI BibTeX RDF
34	Paul M. Heysters, Jaap Smit, Gerard J. M. Smit, Paul J. M. Havinga	Mapping of DSP Algorithms on Field Programmable Function Arrays.	FPL	2000	DBLP DOI BibTeX RDF
34	Tyler J. Moeller, David R. Martinez	Field Programmable Gate Array Based Radar Front-End Digital Signal Processing.	FCCM	1999	DBLP DOI BibTeX RDF
34	Tsutomu Maruyama, Terunobu Funatsu, Tsutomu Hoshino	A Field-Programmable Gate-Array System for Evolutionary Computation.	FPL	1998	DBLP DOI BibTeX RDF
34	Gordon J. Brebner	Field-Programmable Logic: Catalyst for New Computing Paradigms.	FPL	1998	DBLP DOI BibTeX RDF
34	Qiang Wang, David M. Lewis	Automated field-programmable compute accelerator design using partial evaluation.	FCCM	1997	DBLP DOI BibTeX RDF
34	Tong Liu 0007, Wei-Kang Huang, Fabrizio Lombardi	Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays.	FPGA	1995	DBLP DOI BibTeX RDF	constant testability, FPGA, testing, manufacturing
34	Vijayshri Maheshwari, Joel Darnauer, John Ramirez, Wayne Wei-Ming Dai	Design of FPGAs with Area I/O for Field Programmable MCM.	FPGA	1995	DBLP DOI BibTeX RDF
34	Chen Chen 0018, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra	Efficient FPGAs using nanoelectromechanical relays.	FPGA	2010	DBLP DOI BibTeX RDF	CMOS-NEM FPGA, nanoelectromechanical relay
34	Yan Lin 0001, Fei Li 0003, Lei He 0001	Circuits and architectures for field programmable gate array with configurable supply voltage.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
34	Bogdan Pankiewicz, Marek Wójcikowski, Stanislaw Szczepanski, Yichuang Sun	A CMOS field programmable analog array and its application in continuous-time OTA-C filter design.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
34	Mohammed A. S. Khalid, Jonathan Rose	A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems.	FPGA	1998	DBLP DOI BibTeX RDF
33	Ming Liu, Hua Yu, Wei Wang 0003	FPAA Based on Integration of CMOS and Nanojunction Devices for Neuromorphic Applications.	NanoNet	2008	DBLP DOI BibTeX RDF	Field programmable analog arrays (FPAA), Nanojunction devices, Operational amplifier (Op-amp)
33	Amit Laknaur, Sai Raghuram Durbha, Haibo Wang 0005	Built-In-Self-Testing Techniques for Programmable Capacitor Arrays.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	programmable capacitor array, built-in-self-testing, analog testing, field programmable analog array
33	Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo	The design of dynamically reconfigurable datapath coprocessors.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	coarse-grain reconfigurable fabric, reconfigurable datapath, Loop pipelining, interconnection design, datapath synthesis
33	Zhining Huang, Sharad Malik	Exploiting operation level parallelism through dynamically reconfigurable datapaths.	DAC	2002	DBLP DOI BibTeX RDF
33	Diego Pedro Morales, Antonio García 0001, Alberto J. Palma, Antonio Martínez-Olmos, Encarnación Castillo	Exploiting Analog and Digital Reconfiguration for Smart Sensor Interfacing.	FPL	2007	DBLP DOI BibTeX RDF
33	Jianmin Li, Chung-Kuan Cheng	Routability improvement using dynamic interconnect architecture.	FCCM	1995	DBLP DOI BibTeX RDF
33	Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu 0001	Routing for symmetric FPGAs and FPICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
32	Florent Bruguier, Pascal Benoit, Philippe Maurine, Lionel Torres	A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis.	FPL	2011	DBLP DOI BibTeX RDF	ElectroMagnetic Analysis (EMA), Process Characterisation, Field-Programmable Gate Arrays (FPGAs), Ring Oscillator
32	Rehan Ahmed, Peter Hallschmid	Modeling and Evaluation of Dynamic Partial Reconfigurable Datapaths for FPGA-Based Systems Using Stochastic Networks.	FPL	2011	DBLP DOI BibTeX RDF	Modeling, Field-Programmable Gate Arrays, Reconfigurable Computing, Queueing Theory, Partial Reconfiguration